1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_DEEP_SLEEP 36 #if defined(CONFIG_DEEP_SLEEP) 37 #define CONFIG_SILENT_CONSOLE 38 #define CONFIG_BOARD_EARLY_INIT_F 39 #endif 40 41 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_SPL_LIBGENERIC_SUPPORT 51 #define CONFIG_SPL_LIBCOMMON_SUPPORT 52 #define CONFIG_FSL_LAW /* Use common FSL init code */ 53 #define CONFIG_SYS_TEXT_BASE 0x00201000 54 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 55 #define CONFIG_SPL_PAD_TO 0x40000 56 #define CONFIG_SPL_MAX_SIZE 0x28000 57 #define RESET_VECTOR_OFFSET 0x27FFC 58 #define BOOT_PAGE_OFFSET 0x27000 59 #ifdef CONFIG_SPL_BUILD 60 #define CONFIG_SPL_SKIP_RELOCATE 61 #define CONFIG_SPL_COMMON_INIT_DDR 62 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 63 #define CONFIG_SYS_NO_FLASH 64 #endif 65 66 #ifdef CONFIG_NAND 67 #define CONFIG_SPL_NAND_SUPPORT 68 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 69 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 70 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 71 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 72 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 73 #define CONFIG_SPL_NAND_BOOT 74 #endif 75 76 #ifdef CONFIG_SPIFLASH 77 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 78 #define CONFIG_SPL_SPI_SUPPORT 79 #define CONFIG_SPL_SPI_FLASH_SUPPORT 80 #define CONFIG_SPL_SPI_FLASH_MINIMAL 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #define CONFIG_SPL_SPI_BOOT 90 #endif 91 92 #ifdef CONFIG_SDCARD 93 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 94 #define CONFIG_SPL_MMC_SUPPORT 95 #define CONFIG_SPL_MMC_MINIMAL 96 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 97 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 98 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 99 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 100 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 101 #ifndef CONFIG_SPL_BUILD 102 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 103 #endif 104 #define CONFIG_SPL_MMC_BOOT 105 #endif 106 107 #endif /* CONFIG_RAMBOOT_PBL */ 108 109 #ifndef CONFIG_SYS_TEXT_BASE 110 #define CONFIG_SYS_TEXT_BASE 0xeff40000 111 #endif 112 113 #ifndef CONFIG_RESET_VECTOR_ADDRESS 114 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 115 #endif 116 117 #ifndef CONFIG_SYS_NO_FLASH 118 #define CONFIG_FLASH_CFI_DRIVER 119 #define CONFIG_SYS_FLASH_CFI 120 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 121 #endif 122 123 /* PCIe Boot - Master */ 124 #define CONFIG_SRIO_PCIE_BOOT_MASTER 125 /* 126 * for slave u-boot IMAGE instored in master memory space, 127 * PHYS must be aligned based on the SIZE 128 */ 129 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 131 #ifdef CONFIG_PHYS_64BIT 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 134 #else 135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 137 #endif 138 /* 139 * for slave UCODE and ENV instored in master memory space, 140 * PHYS must be aligned based on the SIZE 141 */ 142 #ifdef CONFIG_PHYS_64BIT 143 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 145 #else 146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 148 #endif 149 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 150 /* slave core release by master*/ 151 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 152 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 153 154 /* PCIe Boot - Slave */ 155 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 156 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 157 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 158 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 159 /* Set 1M boot space for PCIe boot */ 160 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 161 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 162 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 163 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 164 #define CONFIG_SYS_NO_FLASH 165 #endif 166 167 #if defined(CONFIG_SPIFLASH) 168 #define CONFIG_SYS_EXTRA_ENV_RELOC 169 #define CONFIG_ENV_IS_IN_SPI_FLASH 170 #define CONFIG_ENV_SPI_BUS 0 171 #define CONFIG_ENV_SPI_CS 0 172 #define CONFIG_ENV_SPI_MAX_HZ 10000000 173 #define CONFIG_ENV_SPI_MODE 0 174 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 175 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 176 #define CONFIG_ENV_SECT_SIZE 0x10000 177 #elif defined(CONFIG_SDCARD) 178 #define CONFIG_SYS_EXTRA_ENV_RELOC 179 #define CONFIG_ENV_IS_IN_MMC 180 #define CONFIG_SYS_MMC_ENV_DEV 0 181 #define CONFIG_ENV_SIZE 0x2000 182 #define CONFIG_ENV_OFFSET (512 * 0x800) 183 #elif defined(CONFIG_NAND) 184 #define CONFIG_SYS_EXTRA_ENV_RELOC 185 #define CONFIG_ENV_IS_IN_NAND 186 #define CONFIG_ENV_SIZE 0x2000 187 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 188 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 189 #define CONFIG_ENV_IS_IN_REMOTE 190 #define CONFIG_ENV_ADDR 0xffe20000 191 #define CONFIG_ENV_SIZE 0x2000 192 #elif defined(CONFIG_ENV_IS_NOWHERE) 193 #define CONFIG_ENV_SIZE 0x2000 194 #else 195 #define CONFIG_ENV_IS_IN_FLASH 196 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 197 #define CONFIG_ENV_SIZE 0x2000 198 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 199 #endif 200 201 #ifndef __ASSEMBLY__ 202 unsigned long get_board_sys_clk(void); 203 unsigned long get_board_ddr_clk(void); 204 #endif 205 206 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 207 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 208 209 /* 210 * These can be toggled for performance analysis, otherwise use default. 211 */ 212 #define CONFIG_SYS_CACHE_STASHING 213 #define CONFIG_BACKSIDE_L2_CACHE 214 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 215 #define CONFIG_BTB /* toggle branch predition */ 216 #define CONFIG_DDR_ECC 217 #ifdef CONFIG_DDR_ECC 218 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 219 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 220 #endif 221 222 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 223 #define CONFIG_SYS_MEMTEST_END 0x00400000 224 #define CONFIG_SYS_ALT_MEMTEST 225 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 226 227 /* 228 * Config the L3 Cache as L3 SRAM 229 */ 230 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 231 #define CONFIG_SYS_L3_SIZE (256 << 10) 232 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 233 #ifdef CONFIG_RAMBOOT_PBL 234 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 235 #endif 236 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 237 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 238 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 239 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 240 241 #ifdef CONFIG_PHYS_64BIT 242 #define CONFIG_SYS_DCSRBAR 0xf0000000 243 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 244 #endif 245 246 /* EEPROM */ 247 #define CONFIG_ID_EEPROM 248 #define CONFIG_SYS_I2C_EEPROM_NXID 249 #define CONFIG_SYS_EEPROM_BUS_NUM 0 250 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 254 255 /* 256 * DDR Setup 257 */ 258 #define CONFIG_VERY_BIG_RAM 259 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 260 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 261 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 262 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 263 #define CONFIG_DDR_SPD 264 #ifndef CONFIG_SYS_FSL_DDR4 265 #define CONFIG_SYS_FSL_DDR3 266 #endif 267 268 #define CONFIG_SYS_SPD_BUS_NUM 0 269 #define SPD_EEPROM_ADDRESS 0x51 270 271 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 272 273 /* 274 * IFC Definitions 275 */ 276 #define CONFIG_SYS_FLASH_BASE 0xe0000000 277 #ifdef CONFIG_PHYS_64BIT 278 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 279 #else 280 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 281 #endif 282 283 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 284 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 285 + 0x8000000) | \ 286 CSPR_PORT_SIZE_16 | \ 287 CSPR_MSEL_NOR | \ 288 CSPR_V) 289 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 290 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 291 CSPR_PORT_SIZE_16 | \ 292 CSPR_MSEL_NOR | \ 293 CSPR_V) 294 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 295 /* NOR Flash Timing Params */ 296 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 297 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 298 FTIM0_NOR_TEADC(0x5) | \ 299 FTIM0_NOR_TEAHC(0x5)) 300 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 301 FTIM1_NOR_TRAD_NOR(0x1A) |\ 302 FTIM1_NOR_TSEQRAD_NOR(0x13)) 303 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 304 FTIM2_NOR_TCH(0x4) | \ 305 FTIM2_NOR_TWPH(0x0E) | \ 306 FTIM2_NOR_TWP(0x1c)) 307 #define CONFIG_SYS_NOR_FTIM3 0x0 308 309 #define CONFIG_SYS_FLASH_QUIET_TEST 310 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 311 312 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 313 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 314 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 315 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 316 317 #define CONFIG_SYS_FLASH_EMPTY_INFO 318 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 319 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 320 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 321 #define QIXIS_BASE 0xffdf0000 322 #ifdef CONFIG_PHYS_64BIT 323 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 324 #else 325 #define QIXIS_BASE_PHYS QIXIS_BASE 326 #endif 327 #define QIXIS_LBMAP_SWITCH 0x06 328 #define QIXIS_LBMAP_MASK 0x0f 329 #define QIXIS_LBMAP_SHIFT 0 330 #define QIXIS_LBMAP_DFLTBANK 0x00 331 #define QIXIS_LBMAP_ALTBANK 0x04 332 #define QIXIS_RST_CTL_RESET 0x31 333 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 334 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 335 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 336 #define QIXIS_RST_FORCE_MEM 0x01 337 338 #define CONFIG_SYS_CSPR3_EXT (0xf) 339 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 340 | CSPR_PORT_SIZE_8 \ 341 | CSPR_MSEL_GPCM \ 342 | CSPR_V) 343 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 344 #define CONFIG_SYS_CSOR3 0x0 345 /* QIXIS Timing parameters for IFC CS3 */ 346 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 347 FTIM0_GPCM_TEADC(0x0e) | \ 348 FTIM0_GPCM_TEAHC(0x0e)) 349 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 350 FTIM1_GPCM_TRAD(0x3f)) 351 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 352 FTIM2_GPCM_TCH(0x8) | \ 353 FTIM2_GPCM_TWP(0x1f)) 354 #define CONFIG_SYS_CS3_FTIM3 0x0 355 356 #define CONFIG_NAND_FSL_IFC 357 #define CONFIG_SYS_NAND_BASE 0xff800000 358 #ifdef CONFIG_PHYS_64BIT 359 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 360 #else 361 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 362 #endif 363 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 364 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 365 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 366 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 367 | CSPR_V) 368 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 369 370 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 371 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 372 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 373 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 374 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 375 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 376 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 377 378 #define CONFIG_SYS_NAND_ONFI_DETECTION 379 380 /* ONFI NAND Flash mode0 Timing Params */ 381 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 382 FTIM0_NAND_TWP(0x18) | \ 383 FTIM0_NAND_TWCHT(0x07) | \ 384 FTIM0_NAND_TWH(0x0a)) 385 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 386 FTIM1_NAND_TWBE(0x39) | \ 387 FTIM1_NAND_TRR(0x0e) | \ 388 FTIM1_NAND_TRP(0x18)) 389 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 390 FTIM2_NAND_TREH(0x0a) | \ 391 FTIM2_NAND_TWHRE(0x1e)) 392 #define CONFIG_SYS_NAND_FTIM3 0x0 393 394 #define CONFIG_SYS_NAND_DDR_LAW 11 395 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 396 #define CONFIG_SYS_MAX_NAND_DEVICE 1 397 #define CONFIG_CMD_NAND 398 399 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 400 401 #if defined(CONFIG_NAND) 402 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 403 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 404 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 405 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 406 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 407 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 408 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 409 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 410 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 411 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 412 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 413 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 414 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 415 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 416 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 417 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 418 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 419 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 420 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 421 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 422 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 423 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 424 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 425 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 426 #else 427 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 428 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 429 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 430 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 431 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 432 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 433 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 434 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 435 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 436 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 437 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 438 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 439 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 440 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 441 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 442 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 443 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 444 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 445 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 446 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 447 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 448 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 449 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 450 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 451 #endif 452 453 #ifdef CONFIG_SPL_BUILD 454 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 455 #else 456 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 457 #endif 458 459 #if defined(CONFIG_RAMBOOT_PBL) 460 #define CONFIG_SYS_RAMBOOT 461 #endif 462 463 #define CONFIG_BOARD_EARLY_INIT_R 464 #define CONFIG_MISC_INIT_R 465 466 #define CONFIG_HWCONFIG 467 468 /* define to use L1 as initial stack */ 469 #define CONFIG_L1_INIT_RAM 470 #define CONFIG_SYS_INIT_RAM_LOCK 471 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 475 /* The assembler doesn't like typecast */ 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 477 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 478 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 479 #else 480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 481 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 483 #endif 484 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 485 486 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 487 GENERATED_GBL_DATA_SIZE) 488 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 489 490 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 491 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 492 493 /* Serial Port */ 494 #define CONFIG_CONS_INDEX 1 495 #define CONFIG_SYS_NS16550_SERIAL 496 #define CONFIG_SYS_NS16550_REG_SIZE 1 497 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 498 499 #define CONFIG_SYS_BAUDRATE_TABLE \ 500 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 501 502 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 503 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 504 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 505 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 506 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 507 508 /* Video */ 509 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 510 #define CONFIG_FSL_DIU_FB 511 #ifdef CONFIG_FSL_DIU_FB 512 #define CONFIG_FSL_DIU_CH7301 513 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 514 #define CONFIG_VIDEO 515 #define CONFIG_CMD_BMP 516 #define CONFIG_CFB_CONSOLE 517 #define CONFIG_VIDEO_SW_CURSOR 518 #define CONFIG_VGA_AS_SINGLE_DEVICE 519 #define CONFIG_VIDEO_LOGO 520 #define CONFIG_VIDEO_BMP_LOGO 521 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 522 /* 523 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 524 * disable empty flash sector detection, which is I/O-intensive. 525 */ 526 #undef CONFIG_SYS_FLASH_EMPTY_INFO 527 #endif 528 #endif 529 530 /* I2C */ 531 #define CONFIG_SYS_I2C 532 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 533 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 534 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 535 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 536 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 537 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 538 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 539 540 #define I2C_MUX_PCA_ADDR 0x77 541 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 542 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 543 #define I2C_RETIMER_ADDR 0x18 544 545 /* I2C bus multiplexer */ 546 #define I2C_MUX_CH_DEFAULT 0x8 547 #define I2C_MUX_CH_DIU 0xC 548 #define I2C_MUX_CH5 0xD 549 #define I2C_MUX_CH7 0xF 550 551 /* LDI/DVI Encoder for display */ 552 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 553 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 554 555 /* 556 * RTC configuration 557 */ 558 #define RTC 559 #define CONFIG_RTC_DS3231 1 560 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 561 562 /* 563 * eSPI - Enhanced SPI 564 */ 565 #ifndef CONFIG_SPL_BUILD 566 #endif 567 #define CONFIG_SPI_FLASH_BAR 568 #define CONFIG_SF_DEFAULT_SPEED 10000000 569 #define CONFIG_SF_DEFAULT_MODE 0 570 571 /* 572 * General PCIe 573 * Memory space is mapped 1-1, but I/O space must start from 0. 574 */ 575 #define CONFIG_PCI /* Enable PCI/PCIE */ 576 #define CONFIG_PCIE1 /* PCIE controller 1 */ 577 #define CONFIG_PCIE2 /* PCIE controller 2 */ 578 #define CONFIG_PCIE3 /* PCIE controller 3 */ 579 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 580 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 581 #define CONFIG_PCI_INDIRECT_BRIDGE 582 583 #ifdef CONFIG_PCI 584 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 585 #ifdef CONFIG_PCIE1 586 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 587 #ifdef CONFIG_PHYS_64BIT 588 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 589 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 590 #else 591 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 592 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 593 #endif 594 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 595 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 596 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 597 #ifdef CONFIG_PHYS_64BIT 598 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 599 #else 600 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 601 #endif 602 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 603 #endif 604 605 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 606 #ifdef CONFIG_PCIE2 607 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 608 #ifdef CONFIG_PHYS_64BIT 609 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 610 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 611 #else 612 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 613 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 614 #endif 615 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 616 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 617 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 618 #ifdef CONFIG_PHYS_64BIT 619 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 620 #else 621 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 622 #endif 623 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 624 #endif 625 626 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 627 #ifdef CONFIG_PCIE3 628 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 629 #ifdef CONFIG_PHYS_64BIT 630 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 631 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 632 #else 633 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 634 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 635 #endif 636 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 637 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 638 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 639 #ifdef CONFIG_PHYS_64BIT 640 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 641 #else 642 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 643 #endif 644 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 645 #endif 646 647 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 648 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 649 #define CONFIG_DOS_PARTITION 650 #endif /* CONFIG_PCI */ 651 652 /* 653 *SATA 654 */ 655 #define CONFIG_FSL_SATA_V2 656 #ifdef CONFIG_FSL_SATA_V2 657 #define CONFIG_LIBATA 658 #define CONFIG_FSL_SATA 659 #define CONFIG_SYS_SATA_MAX_DEVICE 1 660 #define CONFIG_SATA1 661 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 662 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 663 #define CONFIG_LBA48 664 #define CONFIG_CMD_SATA 665 #define CONFIG_DOS_PARTITION 666 #endif 667 668 /* 669 * USB 670 */ 671 #define CONFIG_HAS_FSL_DR_USB 672 673 #ifdef CONFIG_HAS_FSL_DR_USB 674 #define CONFIG_USB_EHCI 675 #define CONFIG_USB_EHCI_FSL 676 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 677 #endif 678 679 /* 680 * SDHC 681 */ 682 #define CONFIG_MMC 683 #ifdef CONFIG_MMC 684 #define CONFIG_FSL_ESDHC 685 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 686 #define CONFIG_GENERIC_MMC 687 #define CONFIG_DOS_PARTITION 688 #endif 689 690 /* Qman/Bman */ 691 #ifndef CONFIG_NOBQFMAN 692 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 693 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 694 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 695 #ifdef CONFIG_PHYS_64BIT 696 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 697 #else 698 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 699 #endif 700 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 701 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 702 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 703 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 704 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 705 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 706 CONFIG_SYS_BMAN_CENA_SIZE) 707 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 708 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 709 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 710 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 711 #ifdef CONFIG_PHYS_64BIT 712 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 713 #else 714 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 715 #endif 716 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 717 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 718 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 719 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 720 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 721 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 722 CONFIG_SYS_QMAN_CENA_SIZE) 723 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 724 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 725 726 #define CONFIG_SYS_DPAA_FMAN 727 728 #define CONFIG_QE 729 #define CONFIG_U_QE 730 /* Default address of microcode for the Linux FMan driver */ 731 #if defined(CONFIG_SPIFLASH) 732 /* 733 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 734 * env, so we got 0x110000. 735 */ 736 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 737 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 738 #define CONFIG_SYS_QE_FW_ADDR 0x130000 739 #elif defined(CONFIG_SDCARD) 740 /* 741 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 742 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 743 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 744 */ 745 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 746 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 747 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 748 #elif defined(CONFIG_NAND) 749 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 750 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 751 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 752 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 753 /* 754 * Slave has no ucode locally, it can fetch this from remote. When implementing 755 * in two corenet boards, slave's ucode could be stored in master's memory 756 * space, the address can be mapped from slave TLB->slave LAW-> 757 * slave SRIO or PCIE outbound window->master inbound window-> 758 * master LAW->the ucode address in master's memory space. 759 */ 760 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 761 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 762 #else 763 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 764 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 765 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 766 #endif 767 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 768 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 769 #endif /* CONFIG_NOBQFMAN */ 770 771 #ifdef CONFIG_SYS_DPAA_FMAN 772 #define CONFIG_FMAN_ENET 773 #define CONFIG_PHYLIB_10G 774 #define CONFIG_PHY_VITESSE 775 #define CONFIG_PHY_REALTEK 776 #define CONFIG_PHY_TERANETICS 777 #define RGMII_PHY1_ADDR 0x1 778 #define RGMII_PHY2_ADDR 0x2 779 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 780 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 781 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 782 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 783 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 784 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 785 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 786 #endif 787 788 #ifdef CONFIG_FMAN_ENET 789 #define CONFIG_MII /* MII PHY management */ 790 #define CONFIG_ETHPRIME "FM1@DTSEC4" 791 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 792 #endif 793 794 /* 795 * Dynamic MTD Partition support with mtdparts 796 */ 797 #ifndef CONFIG_SYS_NO_FLASH 798 #define CONFIG_MTD_DEVICE 799 #define CONFIG_MTD_PARTITIONS 800 #define CONFIG_CMD_MTDPARTS 801 #define CONFIG_FLASH_CFI_MTD 802 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 803 "spi0=spife110000.0" 804 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 805 "128k(dtb),96m(fs),-(user);"\ 806 "fff800000.flash:2m(uboot),9m(kernel),"\ 807 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 808 "2m(uboot),9m(kernel),128k(dtb),-(user)" 809 #endif 810 811 /* 812 * Environment 813 */ 814 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 815 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 816 817 /* 818 * Command line configuration. 819 */ 820 #define CONFIG_CMD_DATE 821 #define CONFIG_CMD_EEPROM 822 #define CONFIG_CMD_ERRATA 823 #define CONFIG_CMD_IRQ 824 #define CONFIG_CMD_REGINFO 825 826 #ifdef CONFIG_PCI 827 #define CONFIG_CMD_PCI 828 #endif 829 830 /* 831 * Miscellaneous configurable options 832 */ 833 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 834 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 835 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 836 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 837 #ifdef CONFIG_CMD_KGDB 838 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 839 #else 840 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 841 #endif 842 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 843 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 844 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 845 846 /* 847 * For booting Linux, the board info and command line data 848 * have to be in the first 64 MB of memory, since this is 849 * the maximum mapped by the Linux kernel during initialization. 850 */ 851 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 852 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 853 854 #ifdef CONFIG_CMD_KGDB 855 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 856 #endif 857 858 /* 859 * Environment Configuration 860 */ 861 #define CONFIG_ROOTPATH "/opt/nfsroot" 862 #define CONFIG_BOOTFILE "uImage" 863 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 864 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 865 #define CONFIG_BAUDRATE 115200 866 #define __USB_PHY_TYPE utmi 867 868 #define CONFIG_EXTRA_ENV_SETTINGS \ 869 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 870 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 871 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 872 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 873 "fdtfile=t1024qds/t1024qds.dtb\0" \ 874 "netdev=eth0\0" \ 875 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 876 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 877 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 878 "tftpflash=tftpboot $loadaddr $uboot && " \ 879 "protect off $ubootaddr +$filesize && " \ 880 "erase $ubootaddr +$filesize && " \ 881 "cp.b $loadaddr $ubootaddr $filesize && " \ 882 "protect on $ubootaddr +$filesize && " \ 883 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 884 "consoledev=ttyS0\0" \ 885 "ramdiskaddr=2000000\0" \ 886 "fdtaddr=d00000\0" \ 887 "bdev=sda3\0" 888 889 #define CONFIG_LINUX \ 890 "setenv bootargs root=/dev/ram rw " \ 891 "console=$consoledev,$baudrate $othbootargs;" \ 892 "setenv ramdiskaddr 0x02000000;" \ 893 "setenv fdtaddr 0x00c00000;" \ 894 "setenv loadaddr 0x1000000;" \ 895 "bootm $loadaddr $ramdiskaddr $fdtaddr" 896 897 #define CONFIG_NFSBOOTCOMMAND \ 898 "setenv bootargs root=/dev/nfs rw " \ 899 "nfsroot=$serverip:$rootpath " \ 900 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 901 "console=$consoledev,$baudrate $othbootargs;" \ 902 "tftp $loadaddr $bootfile;" \ 903 "tftp $fdtaddr $fdtfile;" \ 904 "bootm $loadaddr - $fdtaddr" 905 906 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 907 908 /* Hash command with SHA acceleration supported in hardware */ 909 #ifdef CONFIG_FSL_CAAM 910 #define CONFIG_CMD_HASH 911 #define CONFIG_SHA_HW_ACCEL 912 #endif 913 914 #include <asm/fsl_secure_boot.h> 915 916 #endif /* __T1024QDS_H */ 917