1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_DEEP_SLEEP 36 #if defined(CONFIG_DEEP_SLEEP) 37 #define CONFIG_SILENT_CONSOLE 38 #define CONFIG_BOARD_EARLY_INIT_F 39 #endif 40 41 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 46 #define CONFIG_SPL_SERIAL_SUPPORT 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_FSL_LAW /* Use common FSL init code */ 50 #define CONFIG_SYS_TEXT_BASE 0x00201000 51 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 52 #define CONFIG_SPL_PAD_TO 0x40000 53 #define CONFIG_SPL_MAX_SIZE 0x28000 54 #define RESET_VECTOR_OFFSET 0x27FFC 55 #define BOOT_PAGE_OFFSET 0x27000 56 #ifdef CONFIG_SPL_BUILD 57 #define CONFIG_SPL_SKIP_RELOCATE 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 60 #define CONFIG_SYS_NO_FLASH 61 #endif 62 63 #ifdef CONFIG_NAND 64 #define CONFIG_SPL_NAND_SUPPORT 65 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 66 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 67 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 68 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 69 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 70 #define CONFIG_SPL_NAND_BOOT 71 #endif 72 73 #ifdef CONFIG_SPIFLASH 74 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 75 #define CONFIG_SPL_SPI_SUPPORT 76 #define CONFIG_SPL_SPI_FLASH_SUPPORT 77 #define CONFIG_SPL_SPI_FLASH_MINIMAL 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 83 #ifndef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 85 #endif 86 #define CONFIG_SPL_SPI_BOOT 87 #endif 88 89 #ifdef CONFIG_SDCARD 90 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 91 #define CONFIG_SPL_MMC_MINIMAL 92 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 93 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 94 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 95 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 96 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 97 #ifndef CONFIG_SPL_BUILD 98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 99 #endif 100 #define CONFIG_SPL_MMC_BOOT 101 #endif 102 103 #endif /* CONFIG_RAMBOOT_PBL */ 104 105 #ifndef CONFIG_SYS_TEXT_BASE 106 #define CONFIG_SYS_TEXT_BASE 0xeff40000 107 #endif 108 109 #ifndef CONFIG_RESET_VECTOR_ADDRESS 110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 111 #endif 112 113 #ifndef CONFIG_SYS_NO_FLASH 114 #define CONFIG_FLASH_CFI_DRIVER 115 #define CONFIG_SYS_FLASH_CFI 116 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 117 #endif 118 119 /* PCIe Boot - Master */ 120 #define CONFIG_SRIO_PCIE_BOOT_MASTER 121 /* 122 * for slave u-boot IMAGE instored in master memory space, 123 * PHYS must be aligned based on the SIZE 124 */ 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 126 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 127 #ifdef CONFIG_PHYS_64BIT 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 129 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 130 #else 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 133 #endif 134 /* 135 * for slave UCODE and ENV instored in master memory space, 136 * PHYS must be aligned based on the SIZE 137 */ 138 #ifdef CONFIG_PHYS_64BIT 139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 140 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 141 #else 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 143 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 144 #endif 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 146 /* slave core release by master*/ 147 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 148 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 149 150 /* PCIe Boot - Slave */ 151 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 152 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 153 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 154 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 155 /* Set 1M boot space for PCIe boot */ 156 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 157 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 158 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 159 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 160 #define CONFIG_SYS_NO_FLASH 161 #endif 162 163 #if defined(CONFIG_SPIFLASH) 164 #define CONFIG_SYS_EXTRA_ENV_RELOC 165 #define CONFIG_ENV_IS_IN_SPI_FLASH 166 #define CONFIG_ENV_SPI_BUS 0 167 #define CONFIG_ENV_SPI_CS 0 168 #define CONFIG_ENV_SPI_MAX_HZ 10000000 169 #define CONFIG_ENV_SPI_MODE 0 170 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 171 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 172 #define CONFIG_ENV_SECT_SIZE 0x10000 173 #elif defined(CONFIG_SDCARD) 174 #define CONFIG_SYS_EXTRA_ENV_RELOC 175 #define CONFIG_ENV_IS_IN_MMC 176 #define CONFIG_SYS_MMC_ENV_DEV 0 177 #define CONFIG_ENV_SIZE 0x2000 178 #define CONFIG_ENV_OFFSET (512 * 0x800) 179 #elif defined(CONFIG_NAND) 180 #define CONFIG_SYS_EXTRA_ENV_RELOC 181 #define CONFIG_ENV_IS_IN_NAND 182 #define CONFIG_ENV_SIZE 0x2000 183 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 184 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 185 #define CONFIG_ENV_IS_IN_REMOTE 186 #define CONFIG_ENV_ADDR 0xffe20000 187 #define CONFIG_ENV_SIZE 0x2000 188 #elif defined(CONFIG_ENV_IS_NOWHERE) 189 #define CONFIG_ENV_SIZE 0x2000 190 #else 191 #define CONFIG_ENV_IS_IN_FLASH 192 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 193 #define CONFIG_ENV_SIZE 0x2000 194 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 195 #endif 196 197 #ifndef __ASSEMBLY__ 198 unsigned long get_board_sys_clk(void); 199 unsigned long get_board_ddr_clk(void); 200 #endif 201 202 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 203 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 204 205 /* 206 * These can be toggled for performance analysis, otherwise use default. 207 */ 208 #define CONFIG_SYS_CACHE_STASHING 209 #define CONFIG_BACKSIDE_L2_CACHE 210 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 211 #define CONFIG_BTB /* toggle branch predition */ 212 #define CONFIG_DDR_ECC 213 #ifdef CONFIG_DDR_ECC 214 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 215 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 216 #endif 217 218 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 219 #define CONFIG_SYS_MEMTEST_END 0x00400000 220 #define CONFIG_SYS_ALT_MEMTEST 221 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 222 223 /* 224 * Config the L3 Cache as L3 SRAM 225 */ 226 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 227 #define CONFIG_SYS_L3_SIZE (256 << 10) 228 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 229 #ifdef CONFIG_RAMBOOT_PBL 230 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 231 #endif 232 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 233 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 234 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 235 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 236 237 #ifdef CONFIG_PHYS_64BIT 238 #define CONFIG_SYS_DCSRBAR 0xf0000000 239 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 240 #endif 241 242 /* EEPROM */ 243 #define CONFIG_ID_EEPROM 244 #define CONFIG_SYS_I2C_EEPROM_NXID 245 #define CONFIG_SYS_EEPROM_BUS_NUM 0 246 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 247 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 248 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 250 251 /* 252 * DDR Setup 253 */ 254 #define CONFIG_VERY_BIG_RAM 255 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 256 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 257 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 258 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 259 #define CONFIG_DDR_SPD 260 #ifndef CONFIG_SYS_FSL_DDR4 261 #define CONFIG_SYS_FSL_DDR3 262 #endif 263 264 #define CONFIG_SYS_SPD_BUS_NUM 0 265 #define SPD_EEPROM_ADDRESS 0x51 266 267 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 268 269 /* 270 * IFC Definitions 271 */ 272 #define CONFIG_SYS_FLASH_BASE 0xe0000000 273 #ifdef CONFIG_PHYS_64BIT 274 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 275 #else 276 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 277 #endif 278 279 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 280 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 281 + 0x8000000) | \ 282 CSPR_PORT_SIZE_16 | \ 283 CSPR_MSEL_NOR | \ 284 CSPR_V) 285 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 286 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 287 CSPR_PORT_SIZE_16 | \ 288 CSPR_MSEL_NOR | \ 289 CSPR_V) 290 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 291 /* NOR Flash Timing Params */ 292 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 293 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 294 FTIM0_NOR_TEADC(0x5) | \ 295 FTIM0_NOR_TEAHC(0x5)) 296 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 297 FTIM1_NOR_TRAD_NOR(0x1A) |\ 298 FTIM1_NOR_TSEQRAD_NOR(0x13)) 299 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 300 FTIM2_NOR_TCH(0x4) | \ 301 FTIM2_NOR_TWPH(0x0E) | \ 302 FTIM2_NOR_TWP(0x1c)) 303 #define CONFIG_SYS_NOR_FTIM3 0x0 304 305 #define CONFIG_SYS_FLASH_QUIET_TEST 306 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 307 308 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 309 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 310 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 311 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 312 313 #define CONFIG_SYS_FLASH_EMPTY_INFO 314 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 315 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 316 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 317 #define QIXIS_BASE 0xffdf0000 318 #ifdef CONFIG_PHYS_64BIT 319 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 320 #else 321 #define QIXIS_BASE_PHYS QIXIS_BASE 322 #endif 323 #define QIXIS_LBMAP_SWITCH 0x06 324 #define QIXIS_LBMAP_MASK 0x0f 325 #define QIXIS_LBMAP_SHIFT 0 326 #define QIXIS_LBMAP_DFLTBANK 0x00 327 #define QIXIS_LBMAP_ALTBANK 0x04 328 #define QIXIS_RST_CTL_RESET 0x31 329 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 330 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 331 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 332 #define QIXIS_RST_FORCE_MEM 0x01 333 334 #define CONFIG_SYS_CSPR3_EXT (0xf) 335 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 336 | CSPR_PORT_SIZE_8 \ 337 | CSPR_MSEL_GPCM \ 338 | CSPR_V) 339 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 340 #define CONFIG_SYS_CSOR3 0x0 341 /* QIXIS Timing parameters for IFC CS3 */ 342 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 343 FTIM0_GPCM_TEADC(0x0e) | \ 344 FTIM0_GPCM_TEAHC(0x0e)) 345 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 346 FTIM1_GPCM_TRAD(0x3f)) 347 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 348 FTIM2_GPCM_TCH(0x8) | \ 349 FTIM2_GPCM_TWP(0x1f)) 350 #define CONFIG_SYS_CS3_FTIM3 0x0 351 352 #define CONFIG_NAND_FSL_IFC 353 #define CONFIG_SYS_NAND_BASE 0xff800000 354 #ifdef CONFIG_PHYS_64BIT 355 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 356 #else 357 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 358 #endif 359 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 360 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 361 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 362 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 363 | CSPR_V) 364 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 365 366 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 367 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 368 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 369 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 370 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 371 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 372 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 373 374 #define CONFIG_SYS_NAND_ONFI_DETECTION 375 376 /* ONFI NAND Flash mode0 Timing Params */ 377 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 378 FTIM0_NAND_TWP(0x18) | \ 379 FTIM0_NAND_TWCHT(0x07) | \ 380 FTIM0_NAND_TWH(0x0a)) 381 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 382 FTIM1_NAND_TWBE(0x39) | \ 383 FTIM1_NAND_TRR(0x0e) | \ 384 FTIM1_NAND_TRP(0x18)) 385 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 386 FTIM2_NAND_TREH(0x0a) | \ 387 FTIM2_NAND_TWHRE(0x1e)) 388 #define CONFIG_SYS_NAND_FTIM3 0x0 389 390 #define CONFIG_SYS_NAND_DDR_LAW 11 391 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 392 #define CONFIG_SYS_MAX_NAND_DEVICE 1 393 #define CONFIG_CMD_NAND 394 395 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 396 397 #if defined(CONFIG_NAND) 398 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 399 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 400 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 401 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 402 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 403 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 404 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 405 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 406 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 407 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 408 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 409 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 410 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 411 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 412 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 413 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 414 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 415 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 416 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 417 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 418 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 419 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 420 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 421 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 422 #else 423 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 424 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 425 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 426 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 427 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 428 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 429 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 430 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 431 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 432 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 433 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 434 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 435 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 436 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 437 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 438 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 439 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 440 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 441 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 442 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 443 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 444 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 445 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 446 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 447 #endif 448 449 #ifdef CONFIG_SPL_BUILD 450 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 451 #else 452 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 453 #endif 454 455 #if defined(CONFIG_RAMBOOT_PBL) 456 #define CONFIG_SYS_RAMBOOT 457 #endif 458 459 #define CONFIG_BOARD_EARLY_INIT_R 460 #define CONFIG_MISC_INIT_R 461 462 #define CONFIG_HWCONFIG 463 464 /* define to use L1 as initial stack */ 465 #define CONFIG_L1_INIT_RAM 466 #define CONFIG_SYS_INIT_RAM_LOCK 467 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 471 /* The assembler doesn't like typecast */ 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 473 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 474 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 475 #else 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 479 #endif 480 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 481 482 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 483 GENERATED_GBL_DATA_SIZE) 484 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 485 486 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 487 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 488 489 /* Serial Port */ 490 #define CONFIG_CONS_INDEX 1 491 #define CONFIG_SYS_NS16550_SERIAL 492 #define CONFIG_SYS_NS16550_REG_SIZE 1 493 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 494 495 #define CONFIG_SYS_BAUDRATE_TABLE \ 496 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 497 498 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 499 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 500 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 501 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 502 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 503 504 /* Video */ 505 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 506 #define CONFIG_FSL_DIU_FB 507 #ifdef CONFIG_FSL_DIU_FB 508 #define CONFIG_FSL_DIU_CH7301 509 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 510 #define CONFIG_VIDEO 511 #define CONFIG_CMD_BMP 512 #define CONFIG_CFB_CONSOLE 513 #define CONFIG_VIDEO_SW_CURSOR 514 #define CONFIG_VGA_AS_SINGLE_DEVICE 515 #define CONFIG_VIDEO_LOGO 516 #define CONFIG_VIDEO_BMP_LOGO 517 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 518 /* 519 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 520 * disable empty flash sector detection, which is I/O-intensive. 521 */ 522 #undef CONFIG_SYS_FLASH_EMPTY_INFO 523 #endif 524 #endif 525 526 /* I2C */ 527 #define CONFIG_SYS_I2C 528 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 529 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 530 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 531 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 532 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 533 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 534 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 535 536 #define I2C_MUX_PCA_ADDR 0x77 537 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 538 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 539 #define I2C_RETIMER_ADDR 0x18 540 541 /* I2C bus multiplexer */ 542 #define I2C_MUX_CH_DEFAULT 0x8 543 #define I2C_MUX_CH_DIU 0xC 544 #define I2C_MUX_CH5 0xD 545 #define I2C_MUX_CH7 0xF 546 547 /* LDI/DVI Encoder for display */ 548 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 549 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 550 551 /* 552 * RTC configuration 553 */ 554 #define RTC 555 #define CONFIG_RTC_DS3231 1 556 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 557 558 /* 559 * eSPI - Enhanced SPI 560 */ 561 #ifndef CONFIG_SPL_BUILD 562 #endif 563 #define CONFIG_SPI_FLASH_BAR 564 #define CONFIG_SF_DEFAULT_SPEED 10000000 565 #define CONFIG_SF_DEFAULT_MODE 0 566 567 /* 568 * General PCIe 569 * Memory space is mapped 1-1, but I/O space must start from 0. 570 */ 571 #define CONFIG_PCI /* Enable PCI/PCIE */ 572 #define CONFIG_PCIE1 /* PCIE controller 1 */ 573 #define CONFIG_PCIE2 /* PCIE controller 2 */ 574 #define CONFIG_PCIE3 /* PCIE controller 3 */ 575 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 576 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 577 #define CONFIG_PCI_INDIRECT_BRIDGE 578 579 #ifdef CONFIG_PCI 580 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 581 #ifdef CONFIG_PCIE1 582 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 583 #ifdef CONFIG_PHYS_64BIT 584 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 585 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 586 #else 587 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 588 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 589 #endif 590 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 591 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 592 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 593 #ifdef CONFIG_PHYS_64BIT 594 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 595 #else 596 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 597 #endif 598 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 599 #endif 600 601 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 602 #ifdef CONFIG_PCIE2 603 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 606 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 607 #else 608 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 609 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 610 #endif 611 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 612 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 613 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 614 #ifdef CONFIG_PHYS_64BIT 615 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 616 #else 617 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 618 #endif 619 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 620 #endif 621 622 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 623 #ifdef CONFIG_PCIE3 624 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 625 #ifdef CONFIG_PHYS_64BIT 626 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 627 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 628 #else 629 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 630 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 631 #endif 632 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 633 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 634 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 635 #ifdef CONFIG_PHYS_64BIT 636 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 637 #else 638 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 639 #endif 640 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 641 #endif 642 643 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 644 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 645 #define CONFIG_DOS_PARTITION 646 #endif /* CONFIG_PCI */ 647 648 /* 649 *SATA 650 */ 651 #define CONFIG_FSL_SATA_V2 652 #ifdef CONFIG_FSL_SATA_V2 653 #define CONFIG_LIBATA 654 #define CONFIG_FSL_SATA 655 #define CONFIG_SYS_SATA_MAX_DEVICE 1 656 #define CONFIG_SATA1 657 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 658 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 659 #define CONFIG_LBA48 660 #define CONFIG_CMD_SATA 661 #define CONFIG_DOS_PARTITION 662 #endif 663 664 /* 665 * USB 666 */ 667 #define CONFIG_HAS_FSL_DR_USB 668 669 #ifdef CONFIG_HAS_FSL_DR_USB 670 #define CONFIG_USB_EHCI 671 #define CONFIG_USB_EHCI_FSL 672 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 673 #endif 674 675 /* 676 * SDHC 677 */ 678 #define CONFIG_MMC 679 #ifdef CONFIG_MMC 680 #define CONFIG_FSL_ESDHC 681 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 682 #define CONFIG_GENERIC_MMC 683 #define CONFIG_DOS_PARTITION 684 #endif 685 686 /* Qman/Bman */ 687 #ifndef CONFIG_NOBQFMAN 688 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 689 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 690 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 691 #ifdef CONFIG_PHYS_64BIT 692 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 693 #else 694 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 695 #endif 696 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 697 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 698 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 699 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 700 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 701 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 702 CONFIG_SYS_BMAN_CENA_SIZE) 703 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 704 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 705 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 706 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 707 #ifdef CONFIG_PHYS_64BIT 708 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 709 #else 710 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 711 #endif 712 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 713 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 714 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 715 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 716 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 717 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 718 CONFIG_SYS_QMAN_CENA_SIZE) 719 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 720 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 721 722 #define CONFIG_SYS_DPAA_FMAN 723 724 #define CONFIG_QE 725 #define CONFIG_U_QE 726 /* Default address of microcode for the Linux FMan driver */ 727 #if defined(CONFIG_SPIFLASH) 728 /* 729 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 730 * env, so we got 0x110000. 731 */ 732 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 733 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 734 #define CONFIG_SYS_QE_FW_ADDR 0x130000 735 #elif defined(CONFIG_SDCARD) 736 /* 737 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 738 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 739 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 740 */ 741 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 742 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 743 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 744 #elif defined(CONFIG_NAND) 745 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 746 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 747 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 748 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 749 /* 750 * Slave has no ucode locally, it can fetch this from remote. When implementing 751 * in two corenet boards, slave's ucode could be stored in master's memory 752 * space, the address can be mapped from slave TLB->slave LAW-> 753 * slave SRIO or PCIE outbound window->master inbound window-> 754 * master LAW->the ucode address in master's memory space. 755 */ 756 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 757 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 758 #else 759 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 760 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 761 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 762 #endif 763 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 764 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 765 #endif /* CONFIG_NOBQFMAN */ 766 767 #ifdef CONFIG_SYS_DPAA_FMAN 768 #define CONFIG_FMAN_ENET 769 #define CONFIG_PHYLIB_10G 770 #define CONFIG_PHY_VITESSE 771 #define CONFIG_PHY_REALTEK 772 #define CONFIG_PHY_TERANETICS 773 #define RGMII_PHY1_ADDR 0x1 774 #define RGMII_PHY2_ADDR 0x2 775 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 776 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 777 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 778 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 779 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 780 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 781 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 782 #endif 783 784 #ifdef CONFIG_FMAN_ENET 785 #define CONFIG_MII /* MII PHY management */ 786 #define CONFIG_ETHPRIME "FM1@DTSEC4" 787 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 788 #endif 789 790 /* 791 * Dynamic MTD Partition support with mtdparts 792 */ 793 #ifndef CONFIG_SYS_NO_FLASH 794 #define CONFIG_MTD_DEVICE 795 #define CONFIG_MTD_PARTITIONS 796 #define CONFIG_CMD_MTDPARTS 797 #define CONFIG_FLASH_CFI_MTD 798 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 799 "spi0=spife110000.0" 800 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 801 "128k(dtb),96m(fs),-(user);"\ 802 "fff800000.flash:2m(uboot),9m(kernel),"\ 803 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 804 "2m(uboot),9m(kernel),128k(dtb),-(user)" 805 #endif 806 807 /* 808 * Environment 809 */ 810 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 811 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 812 813 /* 814 * Command line configuration. 815 */ 816 #define CONFIG_CMD_DATE 817 #define CONFIG_CMD_EEPROM 818 #define CONFIG_CMD_ERRATA 819 #define CONFIG_CMD_IRQ 820 #define CONFIG_CMD_REGINFO 821 822 #ifdef CONFIG_PCI 823 #define CONFIG_CMD_PCI 824 #endif 825 826 /* 827 * Miscellaneous configurable options 828 */ 829 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 830 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 831 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 832 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 833 #ifdef CONFIG_CMD_KGDB 834 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 835 #else 836 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 837 #endif 838 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 839 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 840 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 841 842 /* 843 * For booting Linux, the board info and command line data 844 * have to be in the first 64 MB of memory, since this is 845 * the maximum mapped by the Linux kernel during initialization. 846 */ 847 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 848 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 849 850 #ifdef CONFIG_CMD_KGDB 851 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 852 #endif 853 854 /* 855 * Environment Configuration 856 */ 857 #define CONFIG_ROOTPATH "/opt/nfsroot" 858 #define CONFIG_BOOTFILE "uImage" 859 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 860 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 861 #define CONFIG_BAUDRATE 115200 862 #define __USB_PHY_TYPE utmi 863 864 #define CONFIG_EXTRA_ENV_SETTINGS \ 865 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 866 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 867 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 868 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 869 "fdtfile=t1024qds/t1024qds.dtb\0" \ 870 "netdev=eth0\0" \ 871 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 872 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 873 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 874 "tftpflash=tftpboot $loadaddr $uboot && " \ 875 "protect off $ubootaddr +$filesize && " \ 876 "erase $ubootaddr +$filesize && " \ 877 "cp.b $loadaddr $ubootaddr $filesize && " \ 878 "protect on $ubootaddr +$filesize && " \ 879 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 880 "consoledev=ttyS0\0" \ 881 "ramdiskaddr=2000000\0" \ 882 "fdtaddr=d00000\0" \ 883 "bdev=sda3\0" 884 885 #define CONFIG_LINUX \ 886 "setenv bootargs root=/dev/ram rw " \ 887 "console=$consoledev,$baudrate $othbootargs;" \ 888 "setenv ramdiskaddr 0x02000000;" \ 889 "setenv fdtaddr 0x00c00000;" \ 890 "setenv loadaddr 0x1000000;" \ 891 "bootm $loadaddr $ramdiskaddr $fdtaddr" 892 893 #define CONFIG_NFSBOOTCOMMAND \ 894 "setenv bootargs root=/dev/nfs rw " \ 895 "nfsroot=$serverip:$rootpath " \ 896 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 897 "console=$consoledev,$baudrate $othbootargs;" \ 898 "tftp $loadaddr $bootfile;" \ 899 "tftp $fdtaddr $fdtfile;" \ 900 "bootm $loadaddr - $fdtaddr" 901 902 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 903 904 /* Hash command with SHA acceleration supported in hardware */ 905 #ifdef CONFIG_FSL_CAAM 906 #define CONFIG_CMD_HASH 907 #define CONFIG_SHA_HW_ACCEL 908 #endif 909 910 #include <asm/fsl_secure_boot.h> 911 912 #endif /* __T1024QDS_H */ 913