1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_BOOKE 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #define CONFIG_E500MC /* BOOKE e500mc family */ 18 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 19 #define CONFIG_MP /* support multiple processors */ 20 #define CONFIG_ENABLE_36BIT_PHYS 21 22 #ifdef CONFIG_PHYS_64BIT 23 #define CONFIG_ADDR_MAP 1 24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 29 #define CONFIG_FSL_IFC /* Enable IFC Support */ 30 31 #define CONFIG_FSL_LAW /* Use common FSL init code */ 32 #define CONFIG_ENV_OVERWRITE 33 34 #define CONFIG_DEEP_SLEEP 35 #if defined(CONFIG_DEEP_SLEEP) 36 #define CONFIG_SILENT_CONSOLE 37 #define CONFIG_BOARD_EARLY_INIT_F 38 #endif 39 40 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 41 42 #ifdef CONFIG_RAMBOOT_PBL 43 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 44 #define CONFIG_SPL_FLUSH_IMAGE 45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 46 #define CONFIG_FSL_LAW /* Use common FSL init code */ 47 #define CONFIG_SYS_TEXT_BASE 0x00201000 48 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 49 #define CONFIG_SPL_PAD_TO 0x40000 50 #define CONFIG_SPL_MAX_SIZE 0x28000 51 #define RESET_VECTOR_OFFSET 0x27FFC 52 #define BOOT_PAGE_OFFSET 0x27000 53 #ifdef CONFIG_SPL_BUILD 54 #define CONFIG_SPL_SKIP_RELOCATE 55 #define CONFIG_SPL_COMMON_INIT_DDR 56 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 57 #define CONFIG_SYS_NO_FLASH 58 #endif 59 60 #ifdef CONFIG_NAND 61 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 62 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 63 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 64 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 65 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 67 #define CONFIG_SPL_NAND_BOOT 68 #endif 69 70 #ifdef CONFIG_SPIFLASH 71 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 72 #define CONFIG_SPL_SPI_FLASH_MINIMAL 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 78 #ifndef CONFIG_SPL_BUILD 79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 80 #endif 81 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 82 #define CONFIG_SPL_SPI_BOOT 83 #endif 84 85 #ifdef CONFIG_SDCARD 86 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 87 #define CONFIG_SPL_MMC_MINIMAL 88 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 89 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 90 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 91 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 92 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 93 #ifndef CONFIG_SPL_BUILD 94 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 95 #endif 96 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 97 #define CONFIG_SPL_MMC_BOOT 98 #endif 99 100 #endif /* CONFIG_RAMBOOT_PBL */ 101 102 #ifndef CONFIG_SYS_TEXT_BASE 103 #define CONFIG_SYS_TEXT_BASE 0xeff40000 104 #endif 105 106 #ifndef CONFIG_RESET_VECTOR_ADDRESS 107 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 108 #endif 109 110 #ifndef CONFIG_SYS_NO_FLASH 111 #define CONFIG_FLASH_CFI_DRIVER 112 #define CONFIG_SYS_FLASH_CFI 113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 114 #endif 115 116 /* PCIe Boot - Master */ 117 #define CONFIG_SRIO_PCIE_BOOT_MASTER 118 /* 119 * for slave u-boot IMAGE instored in master memory space, 120 * PHYS must be aligned based on the SIZE 121 */ 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 124 #ifdef CONFIG_PHYS_64BIT 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 126 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 127 #else 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 129 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 130 #endif 131 /* 132 * for slave UCODE and ENV instored in master memory space, 133 * PHYS must be aligned based on the SIZE 134 */ 135 #ifdef CONFIG_PHYS_64BIT 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 137 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 138 #else 139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 140 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 141 #endif 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 143 /* slave core release by master*/ 144 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 145 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 146 147 /* PCIe Boot - Slave */ 148 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 149 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 150 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 151 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 152 /* Set 1M boot space for PCIe boot */ 153 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 154 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 155 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 156 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 157 #define CONFIG_SYS_NO_FLASH 158 #endif 159 160 #if defined(CONFIG_SPIFLASH) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_IS_IN_SPI_FLASH 163 #define CONFIG_ENV_SPI_BUS 0 164 #define CONFIG_ENV_SPI_CS 0 165 #define CONFIG_ENV_SPI_MAX_HZ 10000000 166 #define CONFIG_ENV_SPI_MODE 0 167 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 168 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 169 #define CONFIG_ENV_SECT_SIZE 0x10000 170 #elif defined(CONFIG_SDCARD) 171 #define CONFIG_SYS_EXTRA_ENV_RELOC 172 #define CONFIG_ENV_IS_IN_MMC 173 #define CONFIG_SYS_MMC_ENV_DEV 0 174 #define CONFIG_ENV_SIZE 0x2000 175 #define CONFIG_ENV_OFFSET (512 * 0x800) 176 #elif defined(CONFIG_NAND) 177 #define CONFIG_SYS_EXTRA_ENV_RELOC 178 #define CONFIG_ENV_IS_IN_NAND 179 #define CONFIG_ENV_SIZE 0x2000 180 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 181 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 182 #define CONFIG_ENV_IS_IN_REMOTE 183 #define CONFIG_ENV_ADDR 0xffe20000 184 #define CONFIG_ENV_SIZE 0x2000 185 #elif defined(CONFIG_ENV_IS_NOWHERE) 186 #define CONFIG_ENV_SIZE 0x2000 187 #else 188 #define CONFIG_ENV_IS_IN_FLASH 189 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 190 #define CONFIG_ENV_SIZE 0x2000 191 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 192 #endif 193 194 #ifndef __ASSEMBLY__ 195 unsigned long get_board_sys_clk(void); 196 unsigned long get_board_ddr_clk(void); 197 #endif 198 199 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 200 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 201 202 /* 203 * These can be toggled for performance analysis, otherwise use default. 204 */ 205 #define CONFIG_SYS_CACHE_STASHING 206 #define CONFIG_BACKSIDE_L2_CACHE 207 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 208 #define CONFIG_BTB /* toggle branch predition */ 209 #define CONFIG_DDR_ECC 210 #ifdef CONFIG_DDR_ECC 211 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 212 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 213 #endif 214 215 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 216 #define CONFIG_SYS_MEMTEST_END 0x00400000 217 #define CONFIG_SYS_ALT_MEMTEST 218 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 219 220 /* 221 * Config the L3 Cache as L3 SRAM 222 */ 223 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 224 #define CONFIG_SYS_L3_SIZE (256 << 10) 225 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 226 #ifdef CONFIG_RAMBOOT_PBL 227 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 228 #endif 229 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 230 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 231 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 232 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 233 234 #ifdef CONFIG_PHYS_64BIT 235 #define CONFIG_SYS_DCSRBAR 0xf0000000 236 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 237 #endif 238 239 /* EEPROM */ 240 #define CONFIG_ID_EEPROM 241 #define CONFIG_SYS_I2C_EEPROM_NXID 242 #define CONFIG_SYS_EEPROM_BUS_NUM 0 243 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 244 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 245 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 247 248 /* 249 * DDR Setup 250 */ 251 #define CONFIG_VERY_BIG_RAM 252 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 253 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 254 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 255 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 256 #define CONFIG_DDR_SPD 257 #ifndef CONFIG_SYS_FSL_DDR4 258 #define CONFIG_SYS_FSL_DDR3 259 #endif 260 261 #define CONFIG_SYS_SPD_BUS_NUM 0 262 #define SPD_EEPROM_ADDRESS 0x51 263 264 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 265 266 /* 267 * IFC Definitions 268 */ 269 #define CONFIG_SYS_FLASH_BASE 0xe0000000 270 #ifdef CONFIG_PHYS_64BIT 271 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 272 #else 273 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 274 #endif 275 276 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 277 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 278 + 0x8000000) | \ 279 CSPR_PORT_SIZE_16 | \ 280 CSPR_MSEL_NOR | \ 281 CSPR_V) 282 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 283 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 284 CSPR_PORT_SIZE_16 | \ 285 CSPR_MSEL_NOR | \ 286 CSPR_V) 287 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 288 /* NOR Flash Timing Params */ 289 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 290 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 291 FTIM0_NOR_TEADC(0x5) | \ 292 FTIM0_NOR_TEAHC(0x5)) 293 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 294 FTIM1_NOR_TRAD_NOR(0x1A) |\ 295 FTIM1_NOR_TSEQRAD_NOR(0x13)) 296 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 297 FTIM2_NOR_TCH(0x4) | \ 298 FTIM2_NOR_TWPH(0x0E) | \ 299 FTIM2_NOR_TWP(0x1c)) 300 #define CONFIG_SYS_NOR_FTIM3 0x0 301 302 #define CONFIG_SYS_FLASH_QUIET_TEST 303 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 304 305 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 306 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 307 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 308 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 309 310 #define CONFIG_SYS_FLASH_EMPTY_INFO 311 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 312 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 313 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 314 #define QIXIS_BASE 0xffdf0000 315 #ifdef CONFIG_PHYS_64BIT 316 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 317 #else 318 #define QIXIS_BASE_PHYS QIXIS_BASE 319 #endif 320 #define QIXIS_LBMAP_SWITCH 0x06 321 #define QIXIS_LBMAP_MASK 0x0f 322 #define QIXIS_LBMAP_SHIFT 0 323 #define QIXIS_LBMAP_DFLTBANK 0x00 324 #define QIXIS_LBMAP_ALTBANK 0x04 325 #define QIXIS_RST_CTL_RESET 0x31 326 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 327 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 328 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 329 #define QIXIS_RST_FORCE_MEM 0x01 330 331 #define CONFIG_SYS_CSPR3_EXT (0xf) 332 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 333 | CSPR_PORT_SIZE_8 \ 334 | CSPR_MSEL_GPCM \ 335 | CSPR_V) 336 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 337 #define CONFIG_SYS_CSOR3 0x0 338 /* QIXIS Timing parameters for IFC CS3 */ 339 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 340 FTIM0_GPCM_TEADC(0x0e) | \ 341 FTIM0_GPCM_TEAHC(0x0e)) 342 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 343 FTIM1_GPCM_TRAD(0x3f)) 344 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 345 FTIM2_GPCM_TCH(0x8) | \ 346 FTIM2_GPCM_TWP(0x1f)) 347 #define CONFIG_SYS_CS3_FTIM3 0x0 348 349 #define CONFIG_NAND_FSL_IFC 350 #define CONFIG_SYS_NAND_BASE 0xff800000 351 #ifdef CONFIG_PHYS_64BIT 352 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 353 #else 354 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 355 #endif 356 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 357 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 358 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 359 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 360 | CSPR_V) 361 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 362 363 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 364 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 365 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 366 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 367 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 368 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 369 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 370 371 #define CONFIG_SYS_NAND_ONFI_DETECTION 372 373 /* ONFI NAND Flash mode0 Timing Params */ 374 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 375 FTIM0_NAND_TWP(0x18) | \ 376 FTIM0_NAND_TWCHT(0x07) | \ 377 FTIM0_NAND_TWH(0x0a)) 378 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 379 FTIM1_NAND_TWBE(0x39) | \ 380 FTIM1_NAND_TRR(0x0e) | \ 381 FTIM1_NAND_TRP(0x18)) 382 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 383 FTIM2_NAND_TREH(0x0a) | \ 384 FTIM2_NAND_TWHRE(0x1e)) 385 #define CONFIG_SYS_NAND_FTIM3 0x0 386 387 #define CONFIG_SYS_NAND_DDR_LAW 11 388 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 389 #define CONFIG_SYS_MAX_NAND_DEVICE 1 390 #define CONFIG_CMD_NAND 391 392 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 393 394 #if defined(CONFIG_NAND) 395 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 396 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 397 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 398 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 399 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 400 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 401 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 402 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 403 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 404 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 405 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 406 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 407 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 408 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 409 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 410 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 411 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 412 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 413 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 414 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 415 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 416 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 417 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 418 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 419 #else 420 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 421 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 422 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 423 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 424 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 425 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 426 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 427 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 428 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 429 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 430 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 431 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 432 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 433 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 434 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 435 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 436 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 437 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 438 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 439 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 440 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 441 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 442 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 443 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 444 #endif 445 446 #ifdef CONFIG_SPL_BUILD 447 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 448 #else 449 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 450 #endif 451 452 #if defined(CONFIG_RAMBOOT_PBL) 453 #define CONFIG_SYS_RAMBOOT 454 #endif 455 456 #define CONFIG_BOARD_EARLY_INIT_R 457 #define CONFIG_MISC_INIT_R 458 459 #define CONFIG_HWCONFIG 460 461 /* define to use L1 as initial stack */ 462 #define CONFIG_L1_INIT_RAM 463 #define CONFIG_SYS_INIT_RAM_LOCK 464 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 465 #ifdef CONFIG_PHYS_64BIT 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 468 /* The assembler doesn't like typecast */ 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 470 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 471 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 472 #else 473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 476 #endif 477 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 478 479 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 480 GENERATED_GBL_DATA_SIZE) 481 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 482 483 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 484 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 485 486 /* Serial Port */ 487 #define CONFIG_CONS_INDEX 1 488 #define CONFIG_SYS_NS16550_SERIAL 489 #define CONFIG_SYS_NS16550_REG_SIZE 1 490 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 491 492 #define CONFIG_SYS_BAUDRATE_TABLE \ 493 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 494 495 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 496 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 497 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 498 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 499 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 500 501 /* Video */ 502 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 503 #define CONFIG_FSL_DIU_FB 504 #ifdef CONFIG_FSL_DIU_FB 505 #define CONFIG_FSL_DIU_CH7301 506 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 507 #define CONFIG_VIDEO 508 #define CONFIG_CMD_BMP 509 #define CONFIG_CFB_CONSOLE 510 #define CONFIG_VIDEO_SW_CURSOR 511 #define CONFIG_VGA_AS_SINGLE_DEVICE 512 #define CONFIG_VIDEO_LOGO 513 #define CONFIG_VIDEO_BMP_LOGO 514 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 515 /* 516 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 517 * disable empty flash sector detection, which is I/O-intensive. 518 */ 519 #undef CONFIG_SYS_FLASH_EMPTY_INFO 520 #endif 521 #endif 522 523 /* I2C */ 524 #define CONFIG_SYS_I2C 525 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 526 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 527 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 528 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 529 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 530 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 531 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 532 533 #define I2C_MUX_PCA_ADDR 0x77 534 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 535 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 536 #define I2C_RETIMER_ADDR 0x18 537 538 /* I2C bus multiplexer */ 539 #define I2C_MUX_CH_DEFAULT 0x8 540 #define I2C_MUX_CH_DIU 0xC 541 #define I2C_MUX_CH5 0xD 542 #define I2C_MUX_CH7 0xF 543 544 /* LDI/DVI Encoder for display */ 545 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 546 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 547 548 /* 549 * RTC configuration 550 */ 551 #define RTC 552 #define CONFIG_RTC_DS3231 1 553 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 554 555 /* 556 * eSPI - Enhanced SPI 557 */ 558 #ifndef CONFIG_SPL_BUILD 559 #endif 560 #define CONFIG_SPI_FLASH_BAR 561 #define CONFIG_SF_DEFAULT_SPEED 10000000 562 #define CONFIG_SF_DEFAULT_MODE 0 563 564 /* 565 * General PCIe 566 * Memory space is mapped 1-1, but I/O space must start from 0. 567 */ 568 #define CONFIG_PCI /* Enable PCI/PCIE */ 569 #define CONFIG_PCIE1 /* PCIE controller 1 */ 570 #define CONFIG_PCIE2 /* PCIE controller 2 */ 571 #define CONFIG_PCIE3 /* PCIE controller 3 */ 572 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 573 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 574 #define CONFIG_PCI_INDIRECT_BRIDGE 575 576 #ifdef CONFIG_PCI 577 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 578 #ifdef CONFIG_PCIE1 579 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 582 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 583 #else 584 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 585 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 586 #endif 587 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 588 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 589 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 590 #ifdef CONFIG_PHYS_64BIT 591 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 592 #else 593 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 594 #endif 595 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 596 #endif 597 598 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 599 #ifdef CONFIG_PCIE2 600 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 601 #ifdef CONFIG_PHYS_64BIT 602 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 603 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 604 #else 605 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 606 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 607 #endif 608 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 609 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 610 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 611 #ifdef CONFIG_PHYS_64BIT 612 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 613 #else 614 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 615 #endif 616 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 617 #endif 618 619 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 620 #ifdef CONFIG_PCIE3 621 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 622 #ifdef CONFIG_PHYS_64BIT 623 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 624 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 625 #else 626 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 627 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 628 #endif 629 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 630 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 631 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 632 #ifdef CONFIG_PHYS_64BIT 633 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 634 #else 635 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 636 #endif 637 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 638 #endif 639 640 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 641 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 642 #define CONFIG_DOS_PARTITION 643 #endif /* CONFIG_PCI */ 644 645 /* 646 *SATA 647 */ 648 #define CONFIG_FSL_SATA_V2 649 #ifdef CONFIG_FSL_SATA_V2 650 #define CONFIG_LIBATA 651 #define CONFIG_FSL_SATA 652 #define CONFIG_SYS_SATA_MAX_DEVICE 1 653 #define CONFIG_SATA1 654 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 655 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 656 #define CONFIG_LBA48 657 #define CONFIG_CMD_SATA 658 #define CONFIG_DOS_PARTITION 659 #endif 660 661 /* 662 * USB 663 */ 664 #define CONFIG_HAS_FSL_DR_USB 665 666 #ifdef CONFIG_HAS_FSL_DR_USB 667 #define CONFIG_USB_EHCI 668 #define CONFIG_USB_EHCI_FSL 669 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 670 #endif 671 672 /* 673 * SDHC 674 */ 675 #define CONFIG_MMC 676 #ifdef CONFIG_MMC 677 #define CONFIG_FSL_ESDHC 678 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 679 #define CONFIG_GENERIC_MMC 680 #define CONFIG_DOS_PARTITION 681 #endif 682 683 /* Qman/Bman */ 684 #ifndef CONFIG_NOBQFMAN 685 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 686 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 687 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 688 #ifdef CONFIG_PHYS_64BIT 689 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 690 #else 691 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 692 #endif 693 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 694 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 695 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 696 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 697 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 698 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 699 CONFIG_SYS_BMAN_CENA_SIZE) 700 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 701 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 702 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 703 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 704 #ifdef CONFIG_PHYS_64BIT 705 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 706 #else 707 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 708 #endif 709 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 710 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 711 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 712 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 713 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 714 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 715 CONFIG_SYS_QMAN_CENA_SIZE) 716 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 717 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 718 719 #define CONFIG_SYS_DPAA_FMAN 720 721 #define CONFIG_QE 722 #define CONFIG_U_QE 723 /* Default address of microcode for the Linux FMan driver */ 724 #if defined(CONFIG_SPIFLASH) 725 /* 726 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 727 * env, so we got 0x110000. 728 */ 729 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 730 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 731 #define CONFIG_SYS_QE_FW_ADDR 0x130000 732 #elif defined(CONFIG_SDCARD) 733 /* 734 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 735 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 736 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 737 */ 738 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 739 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 740 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 741 #elif defined(CONFIG_NAND) 742 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 743 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 744 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 745 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 746 /* 747 * Slave has no ucode locally, it can fetch this from remote. When implementing 748 * in two corenet boards, slave's ucode could be stored in master's memory 749 * space, the address can be mapped from slave TLB->slave LAW-> 750 * slave SRIO or PCIE outbound window->master inbound window-> 751 * master LAW->the ucode address in master's memory space. 752 */ 753 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 754 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 755 #else 756 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 757 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 758 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 759 #endif 760 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 761 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 762 #endif /* CONFIG_NOBQFMAN */ 763 764 #ifdef CONFIG_SYS_DPAA_FMAN 765 #define CONFIG_FMAN_ENET 766 #define CONFIG_PHYLIB_10G 767 #define CONFIG_PHY_VITESSE 768 #define CONFIG_PHY_REALTEK 769 #define CONFIG_PHY_TERANETICS 770 #define RGMII_PHY1_ADDR 0x1 771 #define RGMII_PHY2_ADDR 0x2 772 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 773 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 774 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 775 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 776 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 777 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 778 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 779 #endif 780 781 #ifdef CONFIG_FMAN_ENET 782 #define CONFIG_MII /* MII PHY management */ 783 #define CONFIG_ETHPRIME "FM1@DTSEC4" 784 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 785 #endif 786 787 /* 788 * Dynamic MTD Partition support with mtdparts 789 */ 790 #ifndef CONFIG_SYS_NO_FLASH 791 #define CONFIG_MTD_DEVICE 792 #define CONFIG_MTD_PARTITIONS 793 #define CONFIG_CMD_MTDPARTS 794 #define CONFIG_FLASH_CFI_MTD 795 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 796 "spi0=spife110000.0" 797 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 798 "128k(dtb),96m(fs),-(user);"\ 799 "fff800000.flash:2m(uboot),9m(kernel),"\ 800 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 801 "2m(uboot),9m(kernel),128k(dtb),-(user)" 802 #endif 803 804 /* 805 * Environment 806 */ 807 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 808 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 809 810 /* 811 * Command line configuration. 812 */ 813 #define CONFIG_CMD_DATE 814 #define CONFIG_CMD_EEPROM 815 #define CONFIG_CMD_ERRATA 816 #define CONFIG_CMD_IRQ 817 #define CONFIG_CMD_REGINFO 818 819 #ifdef CONFIG_PCI 820 #define CONFIG_CMD_PCI 821 #endif 822 823 /* 824 * Miscellaneous configurable options 825 */ 826 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 827 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 828 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 829 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 830 #ifdef CONFIG_CMD_KGDB 831 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 832 #else 833 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 834 #endif 835 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 836 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 837 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 838 839 /* 840 * For booting Linux, the board info and command line data 841 * have to be in the first 64 MB of memory, since this is 842 * the maximum mapped by the Linux kernel during initialization. 843 */ 844 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 845 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 846 847 #ifdef CONFIG_CMD_KGDB 848 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 849 #endif 850 851 /* 852 * Environment Configuration 853 */ 854 #define CONFIG_ROOTPATH "/opt/nfsroot" 855 #define CONFIG_BOOTFILE "uImage" 856 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 857 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 858 #define CONFIG_BAUDRATE 115200 859 #define __USB_PHY_TYPE utmi 860 861 #define CONFIG_EXTRA_ENV_SETTINGS \ 862 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 863 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 864 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 865 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 866 "fdtfile=t1024qds/t1024qds.dtb\0" \ 867 "netdev=eth0\0" \ 868 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 869 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 870 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 871 "tftpflash=tftpboot $loadaddr $uboot && " \ 872 "protect off $ubootaddr +$filesize && " \ 873 "erase $ubootaddr +$filesize && " \ 874 "cp.b $loadaddr $ubootaddr $filesize && " \ 875 "protect on $ubootaddr +$filesize && " \ 876 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 877 "consoledev=ttyS0\0" \ 878 "ramdiskaddr=2000000\0" \ 879 "fdtaddr=d00000\0" \ 880 "bdev=sda3\0" 881 882 #define CONFIG_LINUX \ 883 "setenv bootargs root=/dev/ram rw " \ 884 "console=$consoledev,$baudrate $othbootargs;" \ 885 "setenv ramdiskaddr 0x02000000;" \ 886 "setenv fdtaddr 0x00c00000;" \ 887 "setenv loadaddr 0x1000000;" \ 888 "bootm $loadaddr $ramdiskaddr $fdtaddr" 889 890 #define CONFIG_NFSBOOTCOMMAND \ 891 "setenv bootargs root=/dev/nfs rw " \ 892 "nfsroot=$serverip:$rootpath " \ 893 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 894 "console=$consoledev,$baudrate $othbootargs;" \ 895 "tftp $loadaddr $bootfile;" \ 896 "tftp $fdtaddr $fdtfile;" \ 897 "bootm $loadaddr - $fdtaddr" 898 899 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 900 901 /* Hash command with SHA acceleration supported in hardware */ 902 #ifdef CONFIG_FSL_CAAM 903 #define CONFIG_CMD_HASH 904 #define CONFIG_SHA_HW_ACCEL 905 #endif 906 907 #include <asm/fsl_secure_boot.h> 908 909 #endif /* __T1024QDS_H */ 910