1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 #define CONFIG_DEEP_SLEEP 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 33 #define CONFIG_SPL_FLUSH_IMAGE 34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 35 #define CONFIG_SYS_TEXT_BASE 0x00201000 36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 37 #define CONFIG_SPL_PAD_TO 0x40000 38 #define CONFIG_SPL_MAX_SIZE 0x28000 39 #define RESET_VECTOR_OFFSET 0x27FFC 40 #define BOOT_PAGE_OFFSET 0x27000 41 #ifdef CONFIG_SPL_BUILD 42 #define CONFIG_SPL_SKIP_RELOCATE 43 #define CONFIG_SPL_COMMON_INIT_DDR 44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 45 #endif 46 47 #ifdef CONFIG_NAND 48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 50 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 54 #define CONFIG_SPL_NAND_BOOT 55 #endif 56 57 #ifdef CONFIG_SPIFLASH 58 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 59 #define CONFIG_SPL_SPI_FLASH_MINIMAL 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 65 #ifndef CONFIG_SPL_BUILD 66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 67 #endif 68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 69 #define CONFIG_SPL_SPI_BOOT 70 #endif 71 72 #ifdef CONFIG_SDCARD 73 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 74 #define CONFIG_SPL_MMC_MINIMAL 75 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 76 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 77 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 78 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 80 #ifndef CONFIG_SPL_BUILD 81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 82 #endif 83 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 84 #define CONFIG_SPL_MMC_BOOT 85 #endif 86 87 #endif /* CONFIG_RAMBOOT_PBL */ 88 89 #ifndef CONFIG_SYS_TEXT_BASE 90 #define CONFIG_SYS_TEXT_BASE 0xeff40000 91 #endif 92 93 #ifndef CONFIG_RESET_VECTOR_ADDRESS 94 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 95 #endif 96 97 #ifdef CONFIG_MTD_NOR_FLASH 98 #define CONFIG_FLASH_CFI_DRIVER 99 #define CONFIG_SYS_FLASH_CFI 100 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 101 #endif 102 103 /* PCIe Boot - Master */ 104 #define CONFIG_SRIO_PCIE_BOOT_MASTER 105 /* 106 * for slave u-boot IMAGE instored in master memory space, 107 * PHYS must be aligned based on the SIZE 108 */ 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 111 #ifdef CONFIG_PHYS_64BIT 112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 114 #else 115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 117 #endif 118 /* 119 * for slave UCODE and ENV instored in master memory space, 120 * PHYS must be aligned based on the SIZE 121 */ 122 #ifdef CONFIG_PHYS_64BIT 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 124 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 125 #else 126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 128 #endif 129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 130 /* slave core release by master*/ 131 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 132 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 133 134 /* PCIe Boot - Slave */ 135 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 137 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 138 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 139 /* Set 1M boot space for PCIe boot */ 140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 141 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 142 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 143 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 144 #endif 145 146 #if defined(CONFIG_SPIFLASH) 147 #define CONFIG_SYS_EXTRA_ENV_RELOC 148 #define CONFIG_ENV_SPI_BUS 0 149 #define CONFIG_ENV_SPI_CS 0 150 #define CONFIG_ENV_SPI_MAX_HZ 10000000 151 #define CONFIG_ENV_SPI_MODE 0 152 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 153 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 154 #define CONFIG_ENV_SECT_SIZE 0x10000 155 #elif defined(CONFIG_SDCARD) 156 #define CONFIG_SYS_EXTRA_ENV_RELOC 157 #define CONFIG_SYS_MMC_ENV_DEV 0 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_OFFSET (512 * 0x800) 160 #elif defined(CONFIG_NAND) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 164 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 165 #define CONFIG_ENV_IS_IN_REMOTE 166 #define CONFIG_ENV_ADDR 0xffe20000 167 #define CONFIG_ENV_SIZE 0x2000 168 #elif defined(CONFIG_ENV_IS_NOWHERE) 169 #define CONFIG_ENV_SIZE 0x2000 170 #else 171 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 172 #define CONFIG_ENV_SIZE 0x2000 173 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 174 #endif 175 176 #ifndef __ASSEMBLY__ 177 unsigned long get_board_sys_clk(void); 178 unsigned long get_board_ddr_clk(void); 179 #endif 180 181 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 182 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 183 184 /* 185 * These can be toggled for performance analysis, otherwise use default. 186 */ 187 #define CONFIG_SYS_CACHE_STASHING 188 #define CONFIG_BACKSIDE_L2_CACHE 189 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 190 #define CONFIG_BTB /* toggle branch predition */ 191 #define CONFIG_DDR_ECC 192 #ifdef CONFIG_DDR_ECC 193 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 194 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 195 #endif 196 197 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 198 #define CONFIG_SYS_MEMTEST_END 0x00400000 199 #define CONFIG_SYS_ALT_MEMTEST 200 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 201 202 /* 203 * Config the L3 Cache as L3 SRAM 204 */ 205 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 206 #define CONFIG_SYS_L3_SIZE (256 << 10) 207 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 208 #ifdef CONFIG_RAMBOOT_PBL 209 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 210 #endif 211 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 212 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 213 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 214 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 215 216 #ifdef CONFIG_PHYS_64BIT 217 #define CONFIG_SYS_DCSRBAR 0xf0000000 218 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 219 #endif 220 221 /* EEPROM */ 222 #define CONFIG_ID_EEPROM 223 #define CONFIG_SYS_I2C_EEPROM_NXID 224 #define CONFIG_SYS_EEPROM_BUS_NUM 0 225 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 226 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 229 230 /* 231 * DDR Setup 232 */ 233 #define CONFIG_VERY_BIG_RAM 234 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 235 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 236 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 237 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 238 #define CONFIG_DDR_SPD 239 240 #define CONFIG_SYS_SPD_BUS_NUM 0 241 #define SPD_EEPROM_ADDRESS 0x51 242 243 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 244 245 /* 246 * IFC Definitions 247 */ 248 #define CONFIG_SYS_FLASH_BASE 0xe0000000 249 #ifdef CONFIG_PHYS_64BIT 250 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 251 #else 252 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 253 #endif 254 255 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 256 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 257 + 0x8000000) | \ 258 CSPR_PORT_SIZE_16 | \ 259 CSPR_MSEL_NOR | \ 260 CSPR_V) 261 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 262 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 263 CSPR_PORT_SIZE_16 | \ 264 CSPR_MSEL_NOR | \ 265 CSPR_V) 266 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 267 /* NOR Flash Timing Params */ 268 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 269 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 270 FTIM0_NOR_TEADC(0x5) | \ 271 FTIM0_NOR_TEAHC(0x5)) 272 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 273 FTIM1_NOR_TRAD_NOR(0x1A) |\ 274 FTIM1_NOR_TSEQRAD_NOR(0x13)) 275 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 276 FTIM2_NOR_TCH(0x4) | \ 277 FTIM2_NOR_TWPH(0x0E) | \ 278 FTIM2_NOR_TWP(0x1c)) 279 #define CONFIG_SYS_NOR_FTIM3 0x0 280 281 #define CONFIG_SYS_FLASH_QUIET_TEST 282 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 283 284 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 285 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 286 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 287 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 288 289 #define CONFIG_SYS_FLASH_EMPTY_INFO 290 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 291 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 292 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 293 #define QIXIS_BASE 0xffdf0000 294 #ifdef CONFIG_PHYS_64BIT 295 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 296 #else 297 #define QIXIS_BASE_PHYS QIXIS_BASE 298 #endif 299 #define QIXIS_LBMAP_SWITCH 0x06 300 #define QIXIS_LBMAP_MASK 0x0f 301 #define QIXIS_LBMAP_SHIFT 0 302 #define QIXIS_LBMAP_DFLTBANK 0x00 303 #define QIXIS_LBMAP_ALTBANK 0x04 304 #define QIXIS_RST_CTL_RESET 0x31 305 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 306 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 307 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 308 #define QIXIS_RST_FORCE_MEM 0x01 309 310 #define CONFIG_SYS_CSPR3_EXT (0xf) 311 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 312 | CSPR_PORT_SIZE_8 \ 313 | CSPR_MSEL_GPCM \ 314 | CSPR_V) 315 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 316 #define CONFIG_SYS_CSOR3 0x0 317 /* QIXIS Timing parameters for IFC CS3 */ 318 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 319 FTIM0_GPCM_TEADC(0x0e) | \ 320 FTIM0_GPCM_TEAHC(0x0e)) 321 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 322 FTIM1_GPCM_TRAD(0x3f)) 323 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 324 FTIM2_GPCM_TCH(0x8) | \ 325 FTIM2_GPCM_TWP(0x1f)) 326 #define CONFIG_SYS_CS3_FTIM3 0x0 327 328 #define CONFIG_NAND_FSL_IFC 329 #define CONFIG_SYS_NAND_BASE 0xff800000 330 #ifdef CONFIG_PHYS_64BIT 331 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 332 #else 333 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 334 #endif 335 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 336 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 337 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 338 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 339 | CSPR_V) 340 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 341 342 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 343 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 344 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 345 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 346 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 347 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 348 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 349 350 #define CONFIG_SYS_NAND_ONFI_DETECTION 351 352 /* ONFI NAND Flash mode0 Timing Params */ 353 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 354 FTIM0_NAND_TWP(0x18) | \ 355 FTIM0_NAND_TWCHT(0x07) | \ 356 FTIM0_NAND_TWH(0x0a)) 357 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 358 FTIM1_NAND_TWBE(0x39) | \ 359 FTIM1_NAND_TRR(0x0e) | \ 360 FTIM1_NAND_TRP(0x18)) 361 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 362 FTIM2_NAND_TREH(0x0a) | \ 363 FTIM2_NAND_TWHRE(0x1e)) 364 #define CONFIG_SYS_NAND_FTIM3 0x0 365 366 #define CONFIG_SYS_NAND_DDR_LAW 11 367 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 368 #define CONFIG_SYS_MAX_NAND_DEVICE 1 369 #define CONFIG_CMD_NAND 370 371 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 372 373 #if defined(CONFIG_NAND) 374 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 375 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 376 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 377 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 378 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 379 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 380 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 381 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 382 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 383 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 384 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 385 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 386 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 387 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 388 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 389 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 390 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 391 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 392 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 393 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 394 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 395 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 396 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 397 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 398 #else 399 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 400 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 401 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 402 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 403 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 404 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 405 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 406 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 407 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 408 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 409 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 410 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 411 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 412 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 413 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 414 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 415 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 416 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 417 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 418 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 419 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 420 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 421 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 422 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 423 #endif 424 425 #ifdef CONFIG_SPL_BUILD 426 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 427 #else 428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 429 #endif 430 431 #if defined(CONFIG_RAMBOOT_PBL) 432 #define CONFIG_SYS_RAMBOOT 433 #endif 434 435 #define CONFIG_BOARD_EARLY_INIT_R 436 #define CONFIG_MISC_INIT_R 437 438 #define CONFIG_HWCONFIG 439 440 /* define to use L1 as initial stack */ 441 #define CONFIG_L1_INIT_RAM 442 #define CONFIG_SYS_INIT_RAM_LOCK 443 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 447 /* The assembler doesn't like typecast */ 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 449 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 450 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 451 #else 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 455 #endif 456 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 457 458 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 459 GENERATED_GBL_DATA_SIZE) 460 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 461 462 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 463 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 464 465 /* Serial Port */ 466 #define CONFIG_CONS_INDEX 1 467 #define CONFIG_SYS_NS16550_SERIAL 468 #define CONFIG_SYS_NS16550_REG_SIZE 1 469 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 470 471 #define CONFIG_SYS_BAUDRATE_TABLE \ 472 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 473 474 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 475 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 476 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 477 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 478 479 /* Video */ 480 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 481 #define CONFIG_FSL_DIU_FB 482 #ifdef CONFIG_FSL_DIU_FB 483 #define CONFIG_FSL_DIU_CH7301 484 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 485 #define CONFIG_VIDEO_LOGO 486 #define CONFIG_VIDEO_BMP_LOGO 487 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 488 /* 489 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 490 * disable empty flash sector detection, which is I/O-intensive. 491 */ 492 #undef CONFIG_SYS_FLASH_EMPTY_INFO 493 #endif 494 #endif 495 496 /* I2C */ 497 #define CONFIG_SYS_I2C 498 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 499 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 500 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 501 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 502 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 503 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 504 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 505 506 #define I2C_MUX_PCA_ADDR 0x77 507 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 508 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 509 #define I2C_RETIMER_ADDR 0x18 510 511 /* I2C bus multiplexer */ 512 #define I2C_MUX_CH_DEFAULT 0x8 513 #define I2C_MUX_CH_DIU 0xC 514 #define I2C_MUX_CH5 0xD 515 #define I2C_MUX_CH7 0xF 516 517 /* LDI/DVI Encoder for display */ 518 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 519 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 520 521 /* 522 * RTC configuration 523 */ 524 #define RTC 525 #define CONFIG_RTC_DS3231 1 526 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 527 528 /* 529 * eSPI - Enhanced SPI 530 */ 531 #ifndef CONFIG_SPL_BUILD 532 #endif 533 #define CONFIG_SPI_FLASH_BAR 534 #define CONFIG_SF_DEFAULT_SPEED 10000000 535 #define CONFIG_SF_DEFAULT_MODE 0 536 537 /* 538 * General PCIe 539 * Memory space is mapped 1-1, but I/O space must start from 0. 540 */ 541 #define CONFIG_PCIE1 /* PCIE controller 1 */ 542 #define CONFIG_PCIE2 /* PCIE controller 2 */ 543 #define CONFIG_PCIE3 /* PCIE controller 3 */ 544 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 545 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 546 #define CONFIG_PCI_INDIRECT_BRIDGE 547 548 #ifdef CONFIG_PCI 549 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 550 #ifdef CONFIG_PCIE1 551 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 552 #ifdef CONFIG_PHYS_64BIT 553 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 554 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 555 #else 556 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 557 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 558 #endif 559 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 560 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 561 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 562 #ifdef CONFIG_PHYS_64BIT 563 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 564 #else 565 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 566 #endif 567 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 568 #endif 569 570 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 571 #ifdef CONFIG_PCIE2 572 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 573 #ifdef CONFIG_PHYS_64BIT 574 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 575 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 576 #else 577 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 578 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 579 #endif 580 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 581 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 582 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 583 #ifdef CONFIG_PHYS_64BIT 584 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 585 #else 586 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 587 #endif 588 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 589 #endif 590 591 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 592 #ifdef CONFIG_PCIE3 593 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 594 #ifdef CONFIG_PHYS_64BIT 595 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 596 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 597 #else 598 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 599 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 600 #endif 601 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 602 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 603 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 606 #else 607 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 608 #endif 609 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 610 #endif 611 612 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 613 #endif /* CONFIG_PCI */ 614 615 /* 616 *SATA 617 */ 618 #define CONFIG_FSL_SATA_V2 619 #ifdef CONFIG_FSL_SATA_V2 620 #define CONFIG_LIBATA 621 #define CONFIG_FSL_SATA 622 #define CONFIG_SYS_SATA_MAX_DEVICE 1 623 #define CONFIG_SATA1 624 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 625 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 626 #define CONFIG_LBA48 627 #endif 628 629 /* 630 * USB 631 */ 632 #define CONFIG_HAS_FSL_DR_USB 633 634 #ifdef CONFIG_HAS_FSL_DR_USB 635 #define CONFIG_USB_EHCI_FSL 636 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 637 #endif 638 639 /* 640 * SDHC 641 */ 642 #ifdef CONFIG_MMC 643 #define CONFIG_FSL_ESDHC 644 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 645 #endif 646 647 /* Qman/Bman */ 648 #ifndef CONFIG_NOBQFMAN 649 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 650 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 651 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 652 #ifdef CONFIG_PHYS_64BIT 653 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 654 #else 655 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 656 #endif 657 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 658 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 659 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 660 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 661 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 662 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 663 CONFIG_SYS_BMAN_CENA_SIZE) 664 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 665 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 666 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 667 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 668 #ifdef CONFIG_PHYS_64BIT 669 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 670 #else 671 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 672 #endif 673 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 674 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 675 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 676 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 677 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 678 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 679 CONFIG_SYS_QMAN_CENA_SIZE) 680 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 681 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 682 683 #define CONFIG_SYS_DPAA_FMAN 684 685 #define CONFIG_QE 686 #define CONFIG_U_QE 687 /* Default address of microcode for the Linux FMan driver */ 688 #if defined(CONFIG_SPIFLASH) 689 /* 690 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 691 * env, so we got 0x110000. 692 */ 693 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 694 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 695 #define CONFIG_SYS_QE_FW_ADDR 0x130000 696 #elif defined(CONFIG_SDCARD) 697 /* 698 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 699 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 700 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 701 */ 702 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 703 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 704 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 705 #elif defined(CONFIG_NAND) 706 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 707 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 708 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 709 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 710 /* 711 * Slave has no ucode locally, it can fetch this from remote. When implementing 712 * in two corenet boards, slave's ucode could be stored in master's memory 713 * space, the address can be mapped from slave TLB->slave LAW-> 714 * slave SRIO or PCIE outbound window->master inbound window-> 715 * master LAW->the ucode address in master's memory space. 716 */ 717 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 718 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 719 #else 720 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 721 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 722 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 723 #endif 724 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 725 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 726 #endif /* CONFIG_NOBQFMAN */ 727 728 #ifdef CONFIG_SYS_DPAA_FMAN 729 #define CONFIG_FMAN_ENET 730 #define CONFIG_PHYLIB_10G 731 #define CONFIG_PHY_VITESSE 732 #define CONFIG_PHY_REALTEK 733 #define CONFIG_PHY_TERANETICS 734 #define RGMII_PHY1_ADDR 0x1 735 #define RGMII_PHY2_ADDR 0x2 736 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 737 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 738 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 739 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 740 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 741 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 742 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 743 #endif 744 745 #ifdef CONFIG_FMAN_ENET 746 #define CONFIG_MII /* MII PHY management */ 747 #define CONFIG_ETHPRIME "FM1@DTSEC4" 748 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 749 #endif 750 751 /* 752 * Dynamic MTD Partition support with mtdparts 753 */ 754 #ifdef CONFIG_MTD_NOR_FLASH 755 #define CONFIG_MTD_DEVICE 756 #define CONFIG_MTD_PARTITIONS 757 #define CONFIG_FLASH_CFI_MTD 758 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 759 "spi0=spife110000.0" 760 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 761 "128k(dtb),96m(fs),-(user);"\ 762 "fff800000.flash:2m(uboot),9m(kernel),"\ 763 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 764 "2m(uboot),9m(kernel),128k(dtb),-(user)" 765 #endif 766 767 /* 768 * Environment 769 */ 770 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 771 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 772 773 /* 774 * Command line configuration. 775 */ 776 #define CONFIG_CMD_REGINFO 777 778 #ifdef CONFIG_PCI 779 #define CONFIG_CMD_PCI 780 #endif 781 782 /* 783 * Miscellaneous configurable options 784 */ 785 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 786 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 787 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 788 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 789 #ifdef CONFIG_CMD_KGDB 790 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 791 #else 792 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 793 #endif 794 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 795 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 796 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 797 798 /* 799 * For booting Linux, the board info and command line data 800 * have to be in the first 64 MB of memory, since this is 801 * the maximum mapped by the Linux kernel during initialization. 802 */ 803 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 804 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 805 806 #ifdef CONFIG_CMD_KGDB 807 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 808 #endif 809 810 /* 811 * Environment Configuration 812 */ 813 #define CONFIG_ROOTPATH "/opt/nfsroot" 814 #define CONFIG_BOOTFILE "uImage" 815 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 816 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 817 #define __USB_PHY_TYPE utmi 818 819 #define CONFIG_EXTRA_ENV_SETTINGS \ 820 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 821 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 822 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 823 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 824 "fdtfile=t1024qds/t1024qds.dtb\0" \ 825 "netdev=eth0\0" \ 826 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 827 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 828 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 829 "tftpflash=tftpboot $loadaddr $uboot && " \ 830 "protect off $ubootaddr +$filesize && " \ 831 "erase $ubootaddr +$filesize && " \ 832 "cp.b $loadaddr $ubootaddr $filesize && " \ 833 "protect on $ubootaddr +$filesize && " \ 834 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 835 "consoledev=ttyS0\0" \ 836 "ramdiskaddr=2000000\0" \ 837 "fdtaddr=d00000\0" \ 838 "bdev=sda3\0" 839 840 #define CONFIG_LINUX \ 841 "setenv bootargs root=/dev/ram rw " \ 842 "console=$consoledev,$baudrate $othbootargs;" \ 843 "setenv ramdiskaddr 0x02000000;" \ 844 "setenv fdtaddr 0x00c00000;" \ 845 "setenv loadaddr 0x1000000;" \ 846 "bootm $loadaddr $ramdiskaddr $fdtaddr" 847 848 #define CONFIG_NFSBOOTCOMMAND \ 849 "setenv bootargs root=/dev/nfs rw " \ 850 "nfsroot=$serverip:$rootpath " \ 851 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 852 "console=$consoledev,$baudrate $othbootargs;" \ 853 "tftp $loadaddr $bootfile;" \ 854 "tftp $fdtaddr $fdtfile;" \ 855 "bootm $loadaddr - $fdtaddr" 856 857 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 858 859 #include <asm/fsl_secure_boot.h> 860 861 #endif /* __T1024QDS_H */ 862