1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 26 #define CONFIG_FSL_IFC /* Enable IFC Support */ 27 28 #define CONFIG_ENV_OVERWRITE 29 30 #define CONFIG_DEEP_SLEEP 31 #if defined(CONFIG_DEEP_SLEEP) 32 #define CONFIG_BOARD_EARLY_INIT_F 33 #endif 34 35 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 36 37 #ifdef CONFIG_RAMBOOT_PBL 38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 39 #define CONFIG_SPL_FLUSH_IMAGE 40 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 41 #define CONFIG_SYS_TEXT_BASE 0x00201000 42 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 43 #define CONFIG_SPL_PAD_TO 0x40000 44 #define CONFIG_SPL_MAX_SIZE 0x28000 45 #define RESET_VECTOR_OFFSET 0x27FFC 46 #define BOOT_PAGE_OFFSET 0x27000 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SPL_SKIP_RELOCATE 49 #define CONFIG_SPL_COMMON_INIT_DDR 50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 51 #define CONFIG_SYS_NO_FLASH 52 #endif 53 54 #ifdef CONFIG_NAND 55 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 56 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 57 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 58 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 60 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 61 #define CONFIG_SPL_NAND_BOOT 62 #endif 63 64 #ifdef CONFIG_SPIFLASH 65 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 66 #define CONFIG_SPL_SPI_FLASH_MINIMAL 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 71 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 72 #ifndef CONFIG_SPL_BUILD 73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 74 #endif 75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 76 #define CONFIG_SPL_SPI_BOOT 77 #endif 78 79 #ifdef CONFIG_SDCARD 80 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 81 #define CONFIG_SPL_MMC_MINIMAL 82 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 83 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 84 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 85 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 86 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 87 #ifndef CONFIG_SPL_BUILD 88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 89 #endif 90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 91 #define CONFIG_SPL_MMC_BOOT 92 #endif 93 94 #endif /* CONFIG_RAMBOOT_PBL */ 95 96 #ifndef CONFIG_SYS_TEXT_BASE 97 #define CONFIG_SYS_TEXT_BASE 0xeff40000 98 #endif 99 100 #ifndef CONFIG_RESET_VECTOR_ADDRESS 101 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 102 #endif 103 104 #ifndef CONFIG_SYS_NO_FLASH 105 #define CONFIG_FLASH_CFI_DRIVER 106 #define CONFIG_SYS_FLASH_CFI 107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 108 #endif 109 110 /* PCIe Boot - Master */ 111 #define CONFIG_SRIO_PCIE_BOOT_MASTER 112 /* 113 * for slave u-boot IMAGE instored in master memory space, 114 * PHYS must be aligned based on the SIZE 115 */ 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 117 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 118 #ifdef CONFIG_PHYS_64BIT 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 120 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 121 #else 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 124 #endif 125 /* 126 * for slave UCODE and ENV instored in master memory space, 127 * PHYS must be aligned based on the SIZE 128 */ 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 131 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 132 #else 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 134 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 135 #endif 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 137 /* slave core release by master*/ 138 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 139 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 140 141 /* PCIe Boot - Slave */ 142 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 143 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 144 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 145 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 146 /* Set 1M boot space for PCIe boot */ 147 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 148 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 149 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 150 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 151 #define CONFIG_SYS_NO_FLASH 152 #endif 153 154 #if defined(CONFIG_SPIFLASH) 155 #define CONFIG_SYS_EXTRA_ENV_RELOC 156 #define CONFIG_ENV_IS_IN_SPI_FLASH 157 #define CONFIG_ENV_SPI_BUS 0 158 #define CONFIG_ENV_SPI_CS 0 159 #define CONFIG_ENV_SPI_MAX_HZ 10000000 160 #define CONFIG_ENV_SPI_MODE 0 161 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 162 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 163 #define CONFIG_ENV_SECT_SIZE 0x10000 164 #elif defined(CONFIG_SDCARD) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_MMC 167 #define CONFIG_SYS_MMC_ENV_DEV 0 168 #define CONFIG_ENV_SIZE 0x2000 169 #define CONFIG_ENV_OFFSET (512 * 0x800) 170 #elif defined(CONFIG_NAND) 171 #define CONFIG_SYS_EXTRA_ENV_RELOC 172 #define CONFIG_ENV_IS_IN_NAND 173 #define CONFIG_ENV_SIZE 0x2000 174 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 175 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 176 #define CONFIG_ENV_IS_IN_REMOTE 177 #define CONFIG_ENV_ADDR 0xffe20000 178 #define CONFIG_ENV_SIZE 0x2000 179 #elif defined(CONFIG_ENV_IS_NOWHERE) 180 #define CONFIG_ENV_SIZE 0x2000 181 #else 182 #define CONFIG_ENV_IS_IN_FLASH 183 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 184 #define CONFIG_ENV_SIZE 0x2000 185 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 186 #endif 187 188 #ifndef __ASSEMBLY__ 189 unsigned long get_board_sys_clk(void); 190 unsigned long get_board_ddr_clk(void); 191 #endif 192 193 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 194 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 195 196 /* 197 * These can be toggled for performance analysis, otherwise use default. 198 */ 199 #define CONFIG_SYS_CACHE_STASHING 200 #define CONFIG_BACKSIDE_L2_CACHE 201 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 202 #define CONFIG_BTB /* toggle branch predition */ 203 #define CONFIG_DDR_ECC 204 #ifdef CONFIG_DDR_ECC 205 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 206 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 207 #endif 208 209 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 210 #define CONFIG_SYS_MEMTEST_END 0x00400000 211 #define CONFIG_SYS_ALT_MEMTEST 212 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 213 214 /* 215 * Config the L3 Cache as L3 SRAM 216 */ 217 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 218 #define CONFIG_SYS_L3_SIZE (256 << 10) 219 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 220 #ifdef CONFIG_RAMBOOT_PBL 221 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 222 #endif 223 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 224 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 225 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 226 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 227 228 #ifdef CONFIG_PHYS_64BIT 229 #define CONFIG_SYS_DCSRBAR 0xf0000000 230 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 231 #endif 232 233 /* EEPROM */ 234 #define CONFIG_ID_EEPROM 235 #define CONFIG_SYS_I2C_EEPROM_NXID 236 #define CONFIG_SYS_EEPROM_BUS_NUM 0 237 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 238 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 241 242 /* 243 * DDR Setup 244 */ 245 #define CONFIG_VERY_BIG_RAM 246 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 247 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 248 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 249 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 250 #define CONFIG_DDR_SPD 251 #ifndef CONFIG_SYS_FSL_DDR4 252 #define CONFIG_SYS_FSL_DDR3 253 #endif 254 255 #define CONFIG_SYS_SPD_BUS_NUM 0 256 #define SPD_EEPROM_ADDRESS 0x51 257 258 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 259 260 /* 261 * IFC Definitions 262 */ 263 #define CONFIG_SYS_FLASH_BASE 0xe0000000 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 266 #else 267 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 268 #endif 269 270 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 271 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 272 + 0x8000000) | \ 273 CSPR_PORT_SIZE_16 | \ 274 CSPR_MSEL_NOR | \ 275 CSPR_V) 276 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 277 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 278 CSPR_PORT_SIZE_16 | \ 279 CSPR_MSEL_NOR | \ 280 CSPR_V) 281 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 282 /* NOR Flash Timing Params */ 283 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 284 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 285 FTIM0_NOR_TEADC(0x5) | \ 286 FTIM0_NOR_TEAHC(0x5)) 287 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 288 FTIM1_NOR_TRAD_NOR(0x1A) |\ 289 FTIM1_NOR_TSEQRAD_NOR(0x13)) 290 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 291 FTIM2_NOR_TCH(0x4) | \ 292 FTIM2_NOR_TWPH(0x0E) | \ 293 FTIM2_NOR_TWP(0x1c)) 294 #define CONFIG_SYS_NOR_FTIM3 0x0 295 296 #define CONFIG_SYS_FLASH_QUIET_TEST 297 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 298 299 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 300 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 301 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 302 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 303 304 #define CONFIG_SYS_FLASH_EMPTY_INFO 305 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 306 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 307 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 308 #define QIXIS_BASE 0xffdf0000 309 #ifdef CONFIG_PHYS_64BIT 310 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 311 #else 312 #define QIXIS_BASE_PHYS QIXIS_BASE 313 #endif 314 #define QIXIS_LBMAP_SWITCH 0x06 315 #define QIXIS_LBMAP_MASK 0x0f 316 #define QIXIS_LBMAP_SHIFT 0 317 #define QIXIS_LBMAP_DFLTBANK 0x00 318 #define QIXIS_LBMAP_ALTBANK 0x04 319 #define QIXIS_RST_CTL_RESET 0x31 320 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 321 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 322 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 323 #define QIXIS_RST_FORCE_MEM 0x01 324 325 #define CONFIG_SYS_CSPR3_EXT (0xf) 326 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 327 | CSPR_PORT_SIZE_8 \ 328 | CSPR_MSEL_GPCM \ 329 | CSPR_V) 330 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 331 #define CONFIG_SYS_CSOR3 0x0 332 /* QIXIS Timing parameters for IFC CS3 */ 333 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 334 FTIM0_GPCM_TEADC(0x0e) | \ 335 FTIM0_GPCM_TEAHC(0x0e)) 336 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 337 FTIM1_GPCM_TRAD(0x3f)) 338 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 339 FTIM2_GPCM_TCH(0x8) | \ 340 FTIM2_GPCM_TWP(0x1f)) 341 #define CONFIG_SYS_CS3_FTIM3 0x0 342 343 #define CONFIG_NAND_FSL_IFC 344 #define CONFIG_SYS_NAND_BASE 0xff800000 345 #ifdef CONFIG_PHYS_64BIT 346 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 347 #else 348 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 349 #endif 350 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 351 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 352 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 353 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 354 | CSPR_V) 355 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 356 357 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 358 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 359 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 360 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 361 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 362 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 363 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 364 365 #define CONFIG_SYS_NAND_ONFI_DETECTION 366 367 /* ONFI NAND Flash mode0 Timing Params */ 368 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 369 FTIM0_NAND_TWP(0x18) | \ 370 FTIM0_NAND_TWCHT(0x07) | \ 371 FTIM0_NAND_TWH(0x0a)) 372 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 373 FTIM1_NAND_TWBE(0x39) | \ 374 FTIM1_NAND_TRR(0x0e) | \ 375 FTIM1_NAND_TRP(0x18)) 376 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 377 FTIM2_NAND_TREH(0x0a) | \ 378 FTIM2_NAND_TWHRE(0x1e)) 379 #define CONFIG_SYS_NAND_FTIM3 0x0 380 381 #define CONFIG_SYS_NAND_DDR_LAW 11 382 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 383 #define CONFIG_SYS_MAX_NAND_DEVICE 1 384 #define CONFIG_CMD_NAND 385 386 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 387 388 #if defined(CONFIG_NAND) 389 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 390 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 391 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 392 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 393 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 394 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 395 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 396 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 397 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 398 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 399 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 400 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 401 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 402 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 403 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 404 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 405 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 406 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 407 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 408 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 409 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 410 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 411 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 412 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 413 #else 414 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 415 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 416 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 417 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 418 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 419 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 420 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 421 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 422 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 423 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 424 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 425 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 426 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 427 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 428 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 429 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 430 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 431 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 432 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 433 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 434 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 435 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 436 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 437 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 438 #endif 439 440 #ifdef CONFIG_SPL_BUILD 441 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 442 #else 443 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 444 #endif 445 446 #if defined(CONFIG_RAMBOOT_PBL) 447 #define CONFIG_SYS_RAMBOOT 448 #endif 449 450 #define CONFIG_BOARD_EARLY_INIT_R 451 #define CONFIG_MISC_INIT_R 452 453 #define CONFIG_HWCONFIG 454 455 /* define to use L1 as initial stack */ 456 #define CONFIG_L1_INIT_RAM 457 #define CONFIG_SYS_INIT_RAM_LOCK 458 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 462 /* The assembler doesn't like typecast */ 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 464 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 465 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 466 #else 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 470 #endif 471 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 472 473 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 474 GENERATED_GBL_DATA_SIZE) 475 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 476 477 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 478 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 479 480 /* Serial Port */ 481 #define CONFIG_CONS_INDEX 1 482 #define CONFIG_SYS_NS16550_SERIAL 483 #define CONFIG_SYS_NS16550_REG_SIZE 1 484 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 485 486 #define CONFIG_SYS_BAUDRATE_TABLE \ 487 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 488 489 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 490 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 491 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 492 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 493 494 /* Video */ 495 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 496 #define CONFIG_FSL_DIU_FB 497 #ifdef CONFIG_FSL_DIU_FB 498 #define CONFIG_FSL_DIU_CH7301 499 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 500 #define CONFIG_CMD_BMP 501 #define CONFIG_VIDEO_LOGO 502 #define CONFIG_VIDEO_BMP_LOGO 503 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 504 /* 505 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 506 * disable empty flash sector detection, which is I/O-intensive. 507 */ 508 #undef CONFIG_SYS_FLASH_EMPTY_INFO 509 #endif 510 #endif 511 512 /* I2C */ 513 #define CONFIG_SYS_I2C 514 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 515 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 516 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 517 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 518 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 519 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 520 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 521 522 #define I2C_MUX_PCA_ADDR 0x77 523 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 524 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 525 #define I2C_RETIMER_ADDR 0x18 526 527 /* I2C bus multiplexer */ 528 #define I2C_MUX_CH_DEFAULT 0x8 529 #define I2C_MUX_CH_DIU 0xC 530 #define I2C_MUX_CH5 0xD 531 #define I2C_MUX_CH7 0xF 532 533 /* LDI/DVI Encoder for display */ 534 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 535 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 536 537 /* 538 * RTC configuration 539 */ 540 #define RTC 541 #define CONFIG_RTC_DS3231 1 542 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 543 544 /* 545 * eSPI - Enhanced SPI 546 */ 547 #ifndef CONFIG_SPL_BUILD 548 #endif 549 #define CONFIG_SPI_FLASH_BAR 550 #define CONFIG_SF_DEFAULT_SPEED 10000000 551 #define CONFIG_SF_DEFAULT_MODE 0 552 553 /* 554 * General PCIe 555 * Memory space is mapped 1-1, but I/O space must start from 0. 556 */ 557 #define CONFIG_PCIE1 /* PCIE controller 1 */ 558 #define CONFIG_PCIE2 /* PCIE controller 2 */ 559 #define CONFIG_PCIE3 /* PCIE controller 3 */ 560 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 561 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 562 #define CONFIG_PCI_INDIRECT_BRIDGE 563 564 #ifdef CONFIG_PCI 565 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 566 #ifdef CONFIG_PCIE1 567 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 568 #ifdef CONFIG_PHYS_64BIT 569 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 570 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 571 #else 572 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 573 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 574 #endif 575 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 576 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 577 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 578 #ifdef CONFIG_PHYS_64BIT 579 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 580 #else 581 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 582 #endif 583 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 584 #endif 585 586 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 587 #ifdef CONFIG_PCIE2 588 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 589 #ifdef CONFIG_PHYS_64BIT 590 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 591 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 592 #else 593 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 594 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 595 #endif 596 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 597 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 598 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 601 #else 602 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 603 #endif 604 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 605 #endif 606 607 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 608 #ifdef CONFIG_PCIE3 609 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 610 #ifdef CONFIG_PHYS_64BIT 611 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 612 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 613 #else 614 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 615 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 616 #endif 617 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 618 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 619 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 620 #ifdef CONFIG_PHYS_64BIT 621 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 622 #else 623 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 624 #endif 625 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 626 #endif 627 628 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 629 #define CONFIG_DOS_PARTITION 630 #endif /* CONFIG_PCI */ 631 632 /* 633 *SATA 634 */ 635 #define CONFIG_FSL_SATA_V2 636 #ifdef CONFIG_FSL_SATA_V2 637 #define CONFIG_LIBATA 638 #define CONFIG_FSL_SATA 639 #define CONFIG_SYS_SATA_MAX_DEVICE 1 640 #define CONFIG_SATA1 641 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 642 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 643 #define CONFIG_LBA48 644 #define CONFIG_CMD_SATA 645 #define CONFIG_DOS_PARTITION 646 #endif 647 648 /* 649 * USB 650 */ 651 #define CONFIG_HAS_FSL_DR_USB 652 653 #ifdef CONFIG_HAS_FSL_DR_USB 654 #define CONFIG_USB_EHCI 655 #define CONFIG_USB_EHCI_FSL 656 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 657 #endif 658 659 /* 660 * SDHC 661 */ 662 #ifdef CONFIG_MMC 663 #define CONFIG_FSL_ESDHC 664 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 665 #define CONFIG_GENERIC_MMC 666 #define CONFIG_DOS_PARTITION 667 #endif 668 669 /* Qman/Bman */ 670 #ifndef CONFIG_NOBQFMAN 671 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 672 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 673 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 674 #ifdef CONFIG_PHYS_64BIT 675 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 676 #else 677 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 678 #endif 679 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 680 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 681 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 682 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 683 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 684 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 685 CONFIG_SYS_BMAN_CENA_SIZE) 686 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 687 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 688 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 689 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 690 #ifdef CONFIG_PHYS_64BIT 691 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 692 #else 693 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 694 #endif 695 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 696 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 697 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 698 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 699 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 700 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 701 CONFIG_SYS_QMAN_CENA_SIZE) 702 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 703 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 704 705 #define CONFIG_SYS_DPAA_FMAN 706 707 #define CONFIG_QE 708 #define CONFIG_U_QE 709 /* Default address of microcode for the Linux FMan driver */ 710 #if defined(CONFIG_SPIFLASH) 711 /* 712 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 713 * env, so we got 0x110000. 714 */ 715 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 716 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 717 #define CONFIG_SYS_QE_FW_ADDR 0x130000 718 #elif defined(CONFIG_SDCARD) 719 /* 720 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 721 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 722 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 723 */ 724 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 725 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 726 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 727 #elif defined(CONFIG_NAND) 728 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 729 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 730 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 731 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 732 /* 733 * Slave has no ucode locally, it can fetch this from remote. When implementing 734 * in two corenet boards, slave's ucode could be stored in master's memory 735 * space, the address can be mapped from slave TLB->slave LAW-> 736 * slave SRIO or PCIE outbound window->master inbound window-> 737 * master LAW->the ucode address in master's memory space. 738 */ 739 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 740 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 741 #else 742 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 743 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 744 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 745 #endif 746 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 747 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 748 #endif /* CONFIG_NOBQFMAN */ 749 750 #ifdef CONFIG_SYS_DPAA_FMAN 751 #define CONFIG_FMAN_ENET 752 #define CONFIG_PHYLIB_10G 753 #define CONFIG_PHY_VITESSE 754 #define CONFIG_PHY_REALTEK 755 #define CONFIG_PHY_TERANETICS 756 #define RGMII_PHY1_ADDR 0x1 757 #define RGMII_PHY2_ADDR 0x2 758 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 759 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 760 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 761 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 762 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 763 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 764 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 765 #endif 766 767 #ifdef CONFIG_FMAN_ENET 768 #define CONFIG_MII /* MII PHY management */ 769 #define CONFIG_ETHPRIME "FM1@DTSEC4" 770 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 771 #endif 772 773 /* 774 * Dynamic MTD Partition support with mtdparts 775 */ 776 #ifndef CONFIG_SYS_NO_FLASH 777 #define CONFIG_MTD_DEVICE 778 #define CONFIG_MTD_PARTITIONS 779 #define CONFIG_CMD_MTDPARTS 780 #define CONFIG_FLASH_CFI_MTD 781 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 782 "spi0=spife110000.0" 783 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 784 "128k(dtb),96m(fs),-(user);"\ 785 "fff800000.flash:2m(uboot),9m(kernel),"\ 786 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 787 "2m(uboot),9m(kernel),128k(dtb),-(user)" 788 #endif 789 790 /* 791 * Environment 792 */ 793 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 794 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 795 796 /* 797 * Command line configuration. 798 */ 799 #define CONFIG_CMD_DATE 800 #define CONFIG_CMD_EEPROM 801 #define CONFIG_CMD_ERRATA 802 #define CONFIG_CMD_IRQ 803 #define CONFIG_CMD_REGINFO 804 805 #ifdef CONFIG_PCI 806 #define CONFIG_CMD_PCI 807 #endif 808 809 /* 810 * Miscellaneous configurable options 811 */ 812 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 813 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 814 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 815 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 816 #ifdef CONFIG_CMD_KGDB 817 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 818 #else 819 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 820 #endif 821 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 822 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 823 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 824 825 /* 826 * For booting Linux, the board info and command line data 827 * have to be in the first 64 MB of memory, since this is 828 * the maximum mapped by the Linux kernel during initialization. 829 */ 830 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 831 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 832 833 #ifdef CONFIG_CMD_KGDB 834 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 835 #endif 836 837 /* 838 * Environment Configuration 839 */ 840 #define CONFIG_ROOTPATH "/opt/nfsroot" 841 #define CONFIG_BOOTFILE "uImage" 842 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 843 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 844 #define CONFIG_BAUDRATE 115200 845 #define __USB_PHY_TYPE utmi 846 847 #define CONFIG_EXTRA_ENV_SETTINGS \ 848 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 849 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 850 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 851 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 852 "fdtfile=t1024qds/t1024qds.dtb\0" \ 853 "netdev=eth0\0" \ 854 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 855 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 856 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 857 "tftpflash=tftpboot $loadaddr $uboot && " \ 858 "protect off $ubootaddr +$filesize && " \ 859 "erase $ubootaddr +$filesize && " \ 860 "cp.b $loadaddr $ubootaddr $filesize && " \ 861 "protect on $ubootaddr +$filesize && " \ 862 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 863 "consoledev=ttyS0\0" \ 864 "ramdiskaddr=2000000\0" \ 865 "fdtaddr=d00000\0" \ 866 "bdev=sda3\0" 867 868 #define CONFIG_LINUX \ 869 "setenv bootargs root=/dev/ram rw " \ 870 "console=$consoledev,$baudrate $othbootargs;" \ 871 "setenv ramdiskaddr 0x02000000;" \ 872 "setenv fdtaddr 0x00c00000;" \ 873 "setenv loadaddr 0x1000000;" \ 874 "bootm $loadaddr $ramdiskaddr $fdtaddr" 875 876 #define CONFIG_NFSBOOTCOMMAND \ 877 "setenv bootargs root=/dev/nfs rw " \ 878 "nfsroot=$serverip:$rootpath " \ 879 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 880 "console=$consoledev,$baudrate $othbootargs;" \ 881 "tftp $loadaddr $bootfile;" \ 882 "tftp $fdtaddr $fdtfile;" \ 883 "bootm $loadaddr - $fdtaddr" 884 885 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 886 887 /* Hash command with SHA acceleration supported in hardware */ 888 #ifdef CONFIG_FSL_CAAM 889 #define CONFIG_CMD_HASH 890 #define CONFIG_SHA_HW_ACCEL 891 #endif 892 893 #include <asm/fsl_secure_boot.h> 894 895 #endif /* __T1024QDS_H */ 896