xref: /rk3399_rockchip-uboot/include/configs/P3041DS.h (revision 1a4596601fd395f3afb8f82f3f840c5e00bdd57a)
1e02aea61SKumar Gala /*
2e02aea61SKumar Gala  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3e02aea61SKumar Gala  *
4*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
5e02aea61SKumar Gala  */
6e02aea61SKumar Gala 
7e02aea61SKumar Gala /*
8e02aea61SKumar Gala  * P3041 DS board configuration file
9e02aea61SKumar Gala  *
10e02aea61SKumar Gala  */
11e02aea61SKumar Gala #define CONFIG_P3041DS
12e02aea61SKumar Gala #define CONFIG_PHYS_64BIT
13e02aea61SKumar Gala #define CONFIG_PPC_P3041
14e02aea61SKumar Gala 
15c6d33901SKumar Gala #define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
16c6d33901SKumar Gala 
17c6d33901SKumar Gala #define CONFIG_MMC
18c6d33901SKumar Gala #define CONFIG_NAND_FSL_ELBC
199760b274SZang Roy-R61911 #define CONFIG_FSL_SATA_V2
20c6d33901SKumar Gala #define CONFIG_PCIE3
21e02aea61SKumar Gala #define CONFIG_PCIE4
224d28db8aSKumar Gala #define CONFIG_SYS_DPAA_RMAN
23e02aea61SKumar Gala 
2411860d88STimur Tabi #define CONFIG_SYS_SRIO
2511860d88STimur Tabi #define CONFIG_SRIO1			/* SRIO port 1 */
2611860d88STimur Tabi #define CONFIG_SRIO2			/* SRIO port 2 */
27c8b28152SLiu Gang #define CONFIG_SRIO_PCIE_BOOT_MASTER
28e02aea61SKumar Gala #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
29e02aea61SKumar Gala 
30e02aea61SKumar Gala #include "corenet_ds.h"
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