xref: /rk3399_rockchip-uboot/include/configs/P3041DS.h (revision c27269953b94d19b3fc7a21a1c3e19985507b94d)
1e02aea61SKumar Gala /*
2e02aea61SKumar Gala  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3e02aea61SKumar Gala  *
4*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
5e02aea61SKumar Gala  */
6e02aea61SKumar Gala 
7e02aea61SKumar Gala /*
8e02aea61SKumar Gala  * P3041 DS board configuration file
9e02aea61SKumar Gala  *
10e02aea61SKumar Gala  */
11c6d33901SKumar Gala #define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
12c6d33901SKumar Gala 
13c6d33901SKumar Gala #define CONFIG_NAND_FSL_ELBC
149760b274SZang Roy-R61911 #define CONFIG_FSL_SATA_V2
15c6d33901SKumar Gala #define CONFIG_PCIE3
16e02aea61SKumar Gala #define CONFIG_PCIE4
174d28db8aSKumar Gala #define CONFIG_SYS_DPAA_RMAN
18e02aea61SKumar Gala 
1911860d88STimur Tabi #define CONFIG_SYS_SRIO
2011860d88STimur Tabi #define CONFIG_SRIO1			/* SRIO port 1 */
2111860d88STimur Tabi #define CONFIG_SRIO2			/* SRIO port 2 */
22c8b28152SLiu Gang #define CONFIG_SRIO_PCIE_BOOT_MASTER
23e02aea61SKumar Gala #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
24e02aea61SKumar Gala 
25e02aea61SKumar Gala #include "corenet_ds.h"
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