1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 19 #endif 20 21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 22 /* Set 1M boot space */ 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #endif 28 29 /* High Level Configuration Options */ 30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 31 #define CONFIG_MP /* support multiple processors */ 32 33 #ifndef CONFIG_SYS_TEXT_BASE 34 #define CONFIG_SYS_TEXT_BASE 0xeff40000 35 #endif 36 37 #ifndef CONFIG_RESET_VECTOR_ADDRESS 38 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 43 #define CONFIG_PCIE1 /* PCIE controller 1 */ 44 #define CONFIG_PCIE2 /* PCIE controller 2 */ 45 #define CONFIG_PCIE3 /* PCIE controller 3 */ 46 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 47 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 48 49 #define CONFIG_SYS_SRIO 50 #define CONFIG_SRIO1 /* SRIO port 1 */ 51 #define CONFIG_SRIO2 /* SRIO port 2 */ 52 #define CONFIG_SRIO_PCIE_BOOT_MASTER 53 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 54 55 #define CONFIG_ENV_OVERWRITE 56 57 #ifndef CONFIG_MTD_NOR_FLASH 58 #else 59 #define CONFIG_FLASH_CFI_DRIVER 60 #define CONFIG_SYS_FLASH_CFI 61 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 62 #endif 63 64 #if defined(CONFIG_SPIFLASH) 65 #define CONFIG_SYS_EXTRA_ENV_RELOC 66 #define CONFIG_ENV_SPI_BUS 0 67 #define CONFIG_ENV_SPI_CS 0 68 #define CONFIG_ENV_SPI_MAX_HZ 10000000 69 #define CONFIG_ENV_SPI_MODE 0 70 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 71 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 72 #define CONFIG_ENV_SECT_SIZE 0x10000 73 #elif defined(CONFIG_SDCARD) 74 #define CONFIG_SYS_EXTRA_ENV_RELOC 75 #define CONFIG_FSL_FIXED_MMC_LOCATION 76 #define CONFIG_SYS_MMC_ENV_DEV 0 77 #define CONFIG_ENV_SIZE 0x2000 78 #define CONFIG_ENV_OFFSET (512 * 1658) 79 #elif defined(CONFIG_NAND) 80 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 82 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 83 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 84 #define CONFIG_ENV_IS_IN_REMOTE 85 #define CONFIG_ENV_ADDR 0xffe20000 86 #define CONFIG_ENV_SIZE 0x2000 87 #elif defined(CONFIG_ENV_IS_NOWHERE) 88 #define CONFIG_ENV_SIZE 0x2000 89 #else 90 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 91 - CONFIG_ENV_SECT_SIZE) 92 #define CONFIG_ENV_SIZE 0x2000 93 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 94 #endif 95 96 #ifndef __ASSEMBLY__ 97 unsigned long get_board_sys_clk(unsigned long dummy); 98 #endif 99 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 100 101 /* 102 * These can be toggled for performance analysis, otherwise use default. 103 */ 104 #define CONFIG_SYS_CACHE_STASHING 105 #define CONFIG_BACKSIDE_L2_CACHE 106 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 107 #define CONFIG_BTB /* toggle branch predition */ 108 109 #define CONFIG_ENABLE_36BIT_PHYS 110 111 #ifdef CONFIG_PHYS_64BIT 112 #define CONFIG_ADDR_MAP 113 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 114 #endif 115 116 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 117 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 118 #define CONFIG_SYS_MEMTEST_END 0x00400000 119 #define CONFIG_SYS_ALT_MEMTEST 120 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 121 122 /* 123 * Config the L3 Cache as L3 SRAM 124 */ 125 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 126 #ifdef CONFIG_PHYS_64BIT 127 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 128 CONFIG_RAMBOOT_TEXT_BASE) 129 #else 130 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 131 #endif 132 #define CONFIG_SYS_L3_SIZE (1024 << 10) 133 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 134 135 #ifdef CONFIG_PHYS_64BIT 136 #define CONFIG_SYS_DCSRBAR 0xf0000000 137 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 138 #endif 139 140 /* EEPROM */ 141 #define CONFIG_ID_EEPROM 142 #define CONFIG_SYS_I2C_EEPROM_NXID 143 #define CONFIG_SYS_EEPROM_BUS_NUM 0 144 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 145 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 146 147 /* 148 * DDR Setup 149 */ 150 #define CONFIG_VERY_BIG_RAM 151 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 152 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 153 154 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 155 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 156 157 #define CONFIG_DDR_SPD 158 159 #define CONFIG_SYS_SPD_BUS_NUM 0 160 #define SPD_EEPROM_ADDRESS 0x52 161 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 162 163 /* 164 * Local Bus Definitions 165 */ 166 167 /* Set the local bus clock 1/8 of platform clock */ 168 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 169 170 /* 171 * This board doesn't have a promjet connector. 172 * However, it uses commone corenet board LAW and TLB. 173 * It is necessary to use the same start address with proper offset. 174 */ 175 #define CONFIG_SYS_FLASH_BASE 0xe0000000 176 #ifdef CONFIG_PHYS_64BIT 177 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 178 #else 179 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 180 #endif 181 182 #define CONFIG_SYS_FLASH_BR_PRELIM \ 183 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 184 BR_PS_16 | BR_V) 185 #define CONFIG_SYS_FLASH_OR_PRELIM \ 186 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 187 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 188 189 #define CONFIG_FSL_CPLD 190 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 191 #ifdef CONFIG_PHYS_64BIT 192 #define CPLD_BASE_PHYS 0xfffdf0000ull 193 #else 194 #define CPLD_BASE_PHYS CPLD_BASE 195 #endif 196 197 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 198 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 199 200 #define PIXIS_LBMAP_SWITCH 7 201 #define PIXIS_LBMAP_MASK 0xf0 202 #define PIXIS_LBMAP_SHIFT 4 203 #define PIXIS_LBMAP_ALTBANK 0x40 204 205 #define CONFIG_SYS_FLASH_QUIET_TEST 206 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 207 208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 212 213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 214 215 #if defined(CONFIG_RAMBOOT_PBL) 216 #define CONFIG_SYS_RAMBOOT 217 #endif 218 219 #define CONFIG_NAND_FSL_ELBC 220 /* Nand Flash */ 221 #ifdef CONFIG_NAND_FSL_ELBC 222 #define CONFIG_SYS_NAND_BASE 0xffa00000 223 #ifdef CONFIG_PHYS_64BIT 224 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 225 #else 226 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 227 #endif 228 229 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 230 #define CONFIG_SYS_MAX_NAND_DEVICE 1 231 #define CONFIG_CMD_NAND 232 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 233 234 /* NAND flash config */ 235 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 236 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 237 | BR_PS_8 /* Port Size = 8 bit */ \ 238 | BR_MS_FCM /* MSEL = FCM */ \ 239 | BR_V) /* valid */ 240 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 241 | OR_FCM_PGS /* Large Page*/ \ 242 | OR_FCM_CSCT \ 243 | OR_FCM_CST \ 244 | OR_FCM_CHT \ 245 | OR_FCM_SCY_1 \ 246 | OR_FCM_TRLX \ 247 | OR_FCM_EHTR) 248 249 #ifdef CONFIG_NAND 250 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 251 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 252 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 253 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 254 #else 255 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 256 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 257 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 258 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 259 #endif 260 #else 261 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 262 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 263 #endif /* CONFIG_NAND_FSL_ELBC */ 264 265 #define CONFIG_SYS_FLASH_EMPTY_INFO 266 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 268 269 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 270 #define CONFIG_MISC_INIT_R 271 272 #define CONFIG_HWCONFIG 273 274 /* define to use L1 as initial stack */ 275 #define CONFIG_L1_INIT_RAM 276 #define CONFIG_SYS_INIT_RAM_LOCK 277 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 281 /* The assembler doesn't like typecast */ 282 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 283 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 284 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 285 #else 286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 289 #endif 290 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 291 292 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 293 GENERATED_GBL_DATA_SIZE) 294 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 295 296 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 297 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 298 299 /* Serial Port - controlled on board with jumper J8 300 * open - index 2 301 * shorted - index 1 302 */ 303 #define CONFIG_CONS_INDEX 1 304 #define CONFIG_SYS_NS16550_SERIAL 305 #define CONFIG_SYS_NS16550_REG_SIZE 1 306 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 307 308 #define CONFIG_SYS_BAUDRATE_TABLE \ 309 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 310 311 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 312 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 313 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 314 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 315 316 /* I2C */ 317 #define CONFIG_SYS_I2C 318 #define CONFIG_SYS_I2C_FSL 319 #define CONFIG_SYS_FSL_I2C_SPEED 400000 320 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 321 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 322 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 323 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 324 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 325 326 /* 327 * RapidIO 328 */ 329 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 330 #ifdef CONFIG_PHYS_64BIT 331 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 332 #else 333 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 334 #endif 335 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 336 337 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 338 #ifdef CONFIG_PHYS_64BIT 339 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 340 #else 341 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 342 #endif 343 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 344 345 /* 346 * for slave u-boot IMAGE instored in master memory space, 347 * PHYS must be aligned based on the SIZE 348 */ 349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 353 /* 354 * for slave UCODE and ENV instored in master memory space, 355 * PHYS must be aligned based on the SIZE 356 */ 357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 360 361 /* slave core release by master*/ 362 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 363 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 364 365 /* 366 * SRIO_PCIE_BOOT - SLAVE 367 */ 368 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 369 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 370 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 371 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 372 #endif 373 374 /* 375 * eSPI - Enhanced SPI 376 */ 377 #define CONFIG_SF_DEFAULT_SPEED 10000000 378 #define CONFIG_SF_DEFAULT_MODE 0 379 380 /* 381 * General PCI 382 * Memory space is mapped 1-1, but I/O space must start from 0. 383 */ 384 385 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 386 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 387 #ifdef CONFIG_PHYS_64BIT 388 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 389 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 390 #else 391 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 392 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 393 #endif 394 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 395 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 396 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 397 #ifdef CONFIG_PHYS_64BIT 398 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 399 #else 400 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 401 #endif 402 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 403 404 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 405 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 406 #ifdef CONFIG_PHYS_64BIT 407 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 408 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 409 #else 410 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 411 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 412 #endif 413 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 414 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 415 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 418 #else 419 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 420 #endif 421 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 422 423 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 424 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 425 #ifdef CONFIG_PHYS_64BIT 426 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 427 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 428 #else 429 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 430 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 431 #endif 432 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 433 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 434 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 435 #ifdef CONFIG_PHYS_64BIT 436 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 437 #else 438 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 439 #endif 440 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 441 442 /* Qman/Bman */ 443 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 444 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 445 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 448 #else 449 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 450 #endif 451 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 452 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 453 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 454 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 455 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 456 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 457 CONFIG_SYS_BMAN_CENA_SIZE) 458 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 459 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 460 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 461 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 464 #else 465 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 466 #endif 467 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 468 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 469 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 470 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 471 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 472 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 473 CONFIG_SYS_QMAN_CENA_SIZE) 474 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 475 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 476 477 #define CONFIG_SYS_DPAA_FMAN 478 #define CONFIG_SYS_DPAA_PME 479 /* Default address of microcode for the Linux Fman driver */ 480 #if defined(CONFIG_SPIFLASH) 481 /* 482 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 483 * env, so we got 0x110000. 484 */ 485 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 486 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 487 #elif defined(CONFIG_SDCARD) 488 /* 489 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 490 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 491 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 492 */ 493 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 494 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 495 #elif defined(CONFIG_NAND) 496 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 497 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 498 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 499 /* 500 * Slave has no ucode locally, it can fetch this from remote. When implementing 501 * in two corenet boards, slave's ucode could be stored in master's memory 502 * space, the address can be mapped from slave TLB->slave LAW-> 503 * slave SRIO or PCIE outbound window->master inbound window-> 504 * master LAW->the ucode address in master's memory space. 505 */ 506 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 507 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 508 #else 509 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 510 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 511 #endif 512 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 513 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 514 515 #ifdef CONFIG_SYS_DPAA_FMAN 516 #define CONFIG_FMAN_ENET 517 #define CONFIG_PHYLIB_10G 518 #define CONFIG_PHY_VITESSE 519 #define CONFIG_PHY_TERANETICS 520 #endif 521 522 #ifdef CONFIG_PCI 523 #define CONFIG_PCI_INDIRECT_BRIDGE 524 525 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 526 #endif /* CONFIG_PCI */ 527 528 /* SATA */ 529 #define CONFIG_FSL_SATA_V2 530 531 #ifdef CONFIG_FSL_SATA_V2 532 #define CONFIG_FSL_SATA 533 #define CONFIG_LIBATA 534 535 #define CONFIG_SYS_SATA_MAX_DEVICE 2 536 #define CONFIG_SATA1 537 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 538 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 539 #define CONFIG_SATA2 540 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 541 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 542 543 #define CONFIG_LBA48 544 #endif 545 546 #ifdef CONFIG_FMAN_ENET 547 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 548 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 549 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 550 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 551 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 552 553 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 554 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 555 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 556 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 557 558 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 559 560 #define CONFIG_SYS_TBIPA_VALUE 8 561 #define CONFIG_MII /* MII PHY management */ 562 #define CONFIG_ETHPRIME "FM1@DTSEC1" 563 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 564 #endif 565 566 /* 567 * Environment 568 */ 569 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 570 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 571 572 /* 573 * Command line configuration. 574 */ 575 576 #ifdef CONFIG_PCI 577 #define CONFIG_CMD_PCI 578 #endif 579 580 /* 581 * USB 582 */ 583 #define CONFIG_HAS_FSL_DR_USB 584 #define CONFIG_HAS_FSL_MPH_USB 585 586 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 587 #define CONFIG_USB_EHCI_FSL 588 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 589 #endif 590 591 #ifdef CONFIG_MMC 592 #define CONFIG_FSL_ESDHC 593 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 594 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 595 #endif 596 597 /* 598 * Miscellaneous configurable options 599 */ 600 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 601 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 602 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 603 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 604 #ifdef CONFIG_CMD_KGDB 605 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 606 #else 607 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 608 #endif 609 /* Print Buffer Size */ 610 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 611 sizeof(CONFIG_SYS_PROMPT)+16) 612 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 613 /* Boot Argument Buffer Size */ 614 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 615 616 /* 617 * For booting Linux, the board info and command line data 618 * have to be in the first 64 MB of memory, since this is 619 * the maximum mapped by the Linux kernel during initialization. 620 */ 621 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 622 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 623 624 #ifdef CONFIG_CMD_KGDB 625 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 626 #endif 627 628 /* 629 * Environment Configuration 630 */ 631 #define CONFIG_ROOTPATH "/opt/nfsroot" 632 #define CONFIG_BOOTFILE "uImage" 633 #define CONFIG_UBOOTPATH u-boot.bin 634 635 /* default location for tftp and bootm */ 636 #define CONFIG_LOADADDR 1000000 637 638 #define __USB_PHY_TYPE utmi 639 640 #define CONFIG_EXTRA_ENV_SETTINGS \ 641 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 642 "bank_intlv=cs0_cs1\0" \ 643 "netdev=eth0\0" \ 644 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 645 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 646 "tftpflash=tftpboot $loadaddr $uboot && " \ 647 "protect off $ubootaddr +$filesize && " \ 648 "erase $ubootaddr +$filesize && " \ 649 "cp.b $loadaddr $ubootaddr $filesize && " \ 650 "protect on $ubootaddr +$filesize && " \ 651 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 652 "consoledev=ttyS0\0" \ 653 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 654 "usb_dr_mode=host\0" \ 655 "ramdiskaddr=2000000\0" \ 656 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 657 "fdtaddr=1e00000\0" \ 658 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 659 "bdev=sda3\0" 660 661 #define CONFIG_HDBOOT \ 662 "setenv bootargs root=/dev/$bdev rw " \ 663 "console=$consoledev,$baudrate $othbootargs;" \ 664 "tftp $loadaddr $bootfile;" \ 665 "tftp $fdtaddr $fdtfile;" \ 666 "bootm $loadaddr - $fdtaddr" 667 668 #define CONFIG_NFSBOOTCOMMAND \ 669 "setenv bootargs root=/dev/nfs rw " \ 670 "nfsroot=$serverip:$rootpath " \ 671 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 672 "console=$consoledev,$baudrate $othbootargs;" \ 673 "tftp $loadaddr $bootfile;" \ 674 "tftp $fdtaddr $fdtfile;" \ 675 "bootm $loadaddr - $fdtaddr" 676 677 #define CONFIG_RAMBOOTCOMMAND \ 678 "setenv bootargs root=/dev/ram rw " \ 679 "console=$consoledev,$baudrate $othbootargs;" \ 680 "tftp $ramdiskaddr $ramdiskfile;" \ 681 "tftp $loadaddr $bootfile;" \ 682 "tftp $fdtaddr $fdtfile;" \ 683 "bootm $loadaddr $ramdiskaddr $fdtaddr" 684 685 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 686 687 #include <asm/fsl_secure_boot.h> 688 689 #endif /* __CONFIG_H */ 690