1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 19 #endif 20 21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 22 /* Set 1M boot space */ 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #define CONFIG_SYS_NO_FLASH 28 #endif 29 30 /* High Level Configuration Options */ 31 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 32 #define CONFIG_MP /* support multiple processors */ 33 34 #ifndef CONFIG_SYS_TEXT_BASE 35 #define CONFIG_SYS_TEXT_BASE 0xeff40000 36 #endif 37 38 #ifndef CONFIG_RESET_VECTOR_ADDRESS 39 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 40 #endif 41 42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 43 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 44 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 45 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 46 #define CONFIG_PCIE1 /* PCIE controller 1 */ 47 #define CONFIG_PCIE2 /* PCIE controller 2 */ 48 #define CONFIG_PCIE3 /* PCIE controller 3 */ 49 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 50 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 51 52 #define CONFIG_SYS_SRIO 53 #define CONFIG_SRIO1 /* SRIO port 1 */ 54 #define CONFIG_SRIO2 /* SRIO port 2 */ 55 #define CONFIG_SRIO_PCIE_BOOT_MASTER 56 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 57 58 #define CONFIG_ENV_OVERWRITE 59 60 #ifdef CONFIG_SYS_NO_FLASH 61 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 62 #define CONFIG_ENV_IS_NOWHERE 63 #endif 64 #else 65 #define CONFIG_FLASH_CFI_DRIVER 66 #define CONFIG_SYS_FLASH_CFI 67 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 68 #endif 69 70 #if defined(CONFIG_SPIFLASH) 71 #define CONFIG_SYS_EXTRA_ENV_RELOC 72 #define CONFIG_ENV_IS_IN_SPI_FLASH 73 #define CONFIG_ENV_SPI_BUS 0 74 #define CONFIG_ENV_SPI_CS 0 75 #define CONFIG_ENV_SPI_MAX_HZ 10000000 76 #define CONFIG_ENV_SPI_MODE 0 77 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 78 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 79 #define CONFIG_ENV_SECT_SIZE 0x10000 80 #elif defined(CONFIG_SDCARD) 81 #define CONFIG_SYS_EXTRA_ENV_RELOC 82 #define CONFIG_ENV_IS_IN_MMC 83 #define CONFIG_FSL_FIXED_MMC_LOCATION 84 #define CONFIG_SYS_MMC_ENV_DEV 0 85 #define CONFIG_ENV_SIZE 0x2000 86 #define CONFIG_ENV_OFFSET (512 * 1658) 87 #elif defined(CONFIG_NAND) 88 #define CONFIG_SYS_EXTRA_ENV_RELOC 89 #define CONFIG_ENV_IS_IN_NAND 90 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 91 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 92 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 93 #define CONFIG_ENV_IS_IN_REMOTE 94 #define CONFIG_ENV_ADDR 0xffe20000 95 #define CONFIG_ENV_SIZE 0x2000 96 #elif defined(CONFIG_ENV_IS_NOWHERE) 97 #define CONFIG_ENV_SIZE 0x2000 98 #else 99 #define CONFIG_ENV_IS_IN_FLASH 100 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 101 - CONFIG_ENV_SECT_SIZE) 102 #define CONFIG_ENV_SIZE 0x2000 103 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 104 #endif 105 106 #ifndef __ASSEMBLY__ 107 unsigned long get_board_sys_clk(unsigned long dummy); 108 #endif 109 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 110 111 /* 112 * These can be toggled for performance analysis, otherwise use default. 113 */ 114 #define CONFIG_SYS_CACHE_STASHING 115 #define CONFIG_BACKSIDE_L2_CACHE 116 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 117 #define CONFIG_BTB /* toggle branch predition */ 118 119 #define CONFIG_ENABLE_36BIT_PHYS 120 121 #ifdef CONFIG_PHYS_64BIT 122 #define CONFIG_ADDR_MAP 123 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 124 #endif 125 126 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 127 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 128 #define CONFIG_SYS_MEMTEST_END 0x00400000 129 #define CONFIG_SYS_ALT_MEMTEST 130 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 131 132 /* 133 * Config the L3 Cache as L3 SRAM 134 */ 135 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 136 #ifdef CONFIG_PHYS_64BIT 137 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 138 CONFIG_RAMBOOT_TEXT_BASE) 139 #else 140 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 141 #endif 142 #define CONFIG_SYS_L3_SIZE (1024 << 10) 143 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 144 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_SYS_DCSRBAR 0xf0000000 147 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 148 #endif 149 150 /* EEPROM */ 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 157 /* 158 * DDR Setup 159 */ 160 #define CONFIG_VERY_BIG_RAM 161 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 162 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 163 164 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 165 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 166 167 #define CONFIG_DDR_SPD 168 #define CONFIG_SYS_FSL_DDR3 169 170 #define CONFIG_SYS_SPD_BUS_NUM 0 171 #define SPD_EEPROM_ADDRESS 0x52 172 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 173 174 /* 175 * Local Bus Definitions 176 */ 177 178 /* Set the local bus clock 1/8 of platform clock */ 179 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 180 181 /* 182 * This board doesn't have a promjet connector. 183 * However, it uses commone corenet board LAW and TLB. 184 * It is necessary to use the same start address with proper offset. 185 */ 186 #define CONFIG_SYS_FLASH_BASE 0xe0000000 187 #ifdef CONFIG_PHYS_64BIT 188 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 189 #else 190 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 191 #endif 192 193 #define CONFIG_SYS_FLASH_BR_PRELIM \ 194 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 195 BR_PS_16 | BR_V) 196 #define CONFIG_SYS_FLASH_OR_PRELIM \ 197 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 198 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 199 200 #define CONFIG_FSL_CPLD 201 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 202 #ifdef CONFIG_PHYS_64BIT 203 #define CPLD_BASE_PHYS 0xfffdf0000ull 204 #else 205 #define CPLD_BASE_PHYS CPLD_BASE 206 #endif 207 208 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 209 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 210 211 #define PIXIS_LBMAP_SWITCH 7 212 #define PIXIS_LBMAP_MASK 0xf0 213 #define PIXIS_LBMAP_SHIFT 4 214 #define PIXIS_LBMAP_ALTBANK 0x40 215 216 #define CONFIG_SYS_FLASH_QUIET_TEST 217 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 218 219 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 220 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 223 224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 225 226 #if defined(CONFIG_RAMBOOT_PBL) 227 #define CONFIG_SYS_RAMBOOT 228 #endif 229 230 #define CONFIG_NAND_FSL_ELBC 231 /* Nand Flash */ 232 #ifdef CONFIG_NAND_FSL_ELBC 233 #define CONFIG_SYS_NAND_BASE 0xffa00000 234 #ifdef CONFIG_PHYS_64BIT 235 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 236 #else 237 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 238 #endif 239 240 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 241 #define CONFIG_SYS_MAX_NAND_DEVICE 1 242 #define CONFIG_CMD_NAND 243 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 244 245 /* NAND flash config */ 246 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 247 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 248 | BR_PS_8 /* Port Size = 8 bit */ \ 249 | BR_MS_FCM /* MSEL = FCM */ \ 250 | BR_V) /* valid */ 251 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 252 | OR_FCM_PGS /* Large Page*/ \ 253 | OR_FCM_CSCT \ 254 | OR_FCM_CST \ 255 | OR_FCM_CHT \ 256 | OR_FCM_SCY_1 \ 257 | OR_FCM_TRLX \ 258 | OR_FCM_EHTR) 259 260 #ifdef CONFIG_NAND 261 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 262 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 263 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 264 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 265 #else 266 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 267 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 268 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 269 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 270 #endif 271 #else 272 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 273 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 274 #endif /* CONFIG_NAND_FSL_ELBC */ 275 276 #define CONFIG_SYS_FLASH_EMPTY_INFO 277 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 278 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 279 280 #define CONFIG_BOARD_EARLY_INIT_F 281 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 282 #define CONFIG_MISC_INIT_R 283 284 #define CONFIG_HWCONFIG 285 286 /* define to use L1 as initial stack */ 287 #define CONFIG_L1_INIT_RAM 288 #define CONFIG_SYS_INIT_RAM_LOCK 289 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 290 #ifdef CONFIG_PHYS_64BIT 291 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 292 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 293 /* The assembler doesn't like typecast */ 294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 295 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 296 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 297 #else 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 301 #endif 302 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 303 304 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 305 GENERATED_GBL_DATA_SIZE) 306 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 307 308 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 309 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 310 311 /* Serial Port - controlled on board with jumper J8 312 * open - index 2 313 * shorted - index 1 314 */ 315 #define CONFIG_CONS_INDEX 1 316 #define CONFIG_SYS_NS16550_SERIAL 317 #define CONFIG_SYS_NS16550_REG_SIZE 1 318 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 319 320 #define CONFIG_SYS_BAUDRATE_TABLE \ 321 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 322 323 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 324 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 325 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 326 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 327 328 /* I2C */ 329 #define CONFIG_SYS_I2C 330 #define CONFIG_SYS_I2C_FSL 331 #define CONFIG_SYS_FSL_I2C_SPEED 400000 332 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 333 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 334 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 335 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 336 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 337 338 /* 339 * RapidIO 340 */ 341 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 342 #ifdef CONFIG_PHYS_64BIT 343 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 344 #else 345 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 346 #endif 347 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 348 349 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 350 #ifdef CONFIG_PHYS_64BIT 351 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 352 #else 353 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 354 #endif 355 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 356 357 /* 358 * for slave u-boot IMAGE instored in master memory space, 359 * PHYS must be aligned based on the SIZE 360 */ 361 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 362 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 363 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 364 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 365 /* 366 * for slave UCODE and ENV instored in master memory space, 367 * PHYS must be aligned based on the SIZE 368 */ 369 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 370 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 371 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 372 373 /* slave core release by master*/ 374 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 375 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 376 377 /* 378 * SRIO_PCIE_BOOT - SLAVE 379 */ 380 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 381 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 382 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 383 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 384 #endif 385 386 /* 387 * eSPI - Enhanced SPI 388 */ 389 #define CONFIG_SF_DEFAULT_SPEED 10000000 390 #define CONFIG_SF_DEFAULT_MODE 0 391 392 /* 393 * General PCI 394 * Memory space is mapped 1-1, but I/O space must start from 0. 395 */ 396 397 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 398 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 399 #ifdef CONFIG_PHYS_64BIT 400 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 401 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 402 #else 403 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 404 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 405 #endif 406 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 407 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 408 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 409 #ifdef CONFIG_PHYS_64BIT 410 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 411 #else 412 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 413 #endif 414 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 415 416 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 417 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 420 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 421 #else 422 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 423 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 424 #endif 425 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 426 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 427 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 428 #ifdef CONFIG_PHYS_64BIT 429 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 430 #else 431 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 432 #endif 433 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 434 435 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 436 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 439 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 440 #else 441 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 442 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 443 #endif 444 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 445 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 446 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 449 #else 450 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 451 #endif 452 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 453 454 /* Qman/Bman */ 455 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 456 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 457 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 460 #else 461 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 462 #endif 463 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 464 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 465 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 466 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 467 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 468 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 469 CONFIG_SYS_BMAN_CENA_SIZE) 470 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 471 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 472 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 473 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 476 #else 477 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 478 #endif 479 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 480 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 481 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 482 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 483 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 484 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 485 CONFIG_SYS_QMAN_CENA_SIZE) 486 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 487 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 488 489 #define CONFIG_SYS_DPAA_FMAN 490 #define CONFIG_SYS_DPAA_PME 491 /* Default address of microcode for the Linux Fman driver */ 492 #if defined(CONFIG_SPIFLASH) 493 /* 494 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 495 * env, so we got 0x110000. 496 */ 497 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 498 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 499 #elif defined(CONFIG_SDCARD) 500 /* 501 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 502 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 503 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 504 */ 505 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 506 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 507 #elif defined(CONFIG_NAND) 508 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 509 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 510 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 511 /* 512 * Slave has no ucode locally, it can fetch this from remote. When implementing 513 * in two corenet boards, slave's ucode could be stored in master's memory 514 * space, the address can be mapped from slave TLB->slave LAW-> 515 * slave SRIO or PCIE outbound window->master inbound window-> 516 * master LAW->the ucode address in master's memory space. 517 */ 518 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 519 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 520 #else 521 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 522 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 523 #endif 524 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 525 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 526 527 #ifdef CONFIG_SYS_DPAA_FMAN 528 #define CONFIG_FMAN_ENET 529 #define CONFIG_PHYLIB_10G 530 #define CONFIG_PHY_VITESSE 531 #define CONFIG_PHY_TERANETICS 532 #endif 533 534 #ifdef CONFIG_PCI 535 #define CONFIG_PCI_INDIRECT_BRIDGE 536 537 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 538 #define CONFIG_DOS_PARTITION 539 #endif /* CONFIG_PCI */ 540 541 /* SATA */ 542 #define CONFIG_FSL_SATA_V2 543 544 #ifdef CONFIG_FSL_SATA_V2 545 #define CONFIG_FSL_SATA 546 #define CONFIG_LIBATA 547 548 #define CONFIG_SYS_SATA_MAX_DEVICE 2 549 #define CONFIG_SATA1 550 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 551 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 552 #define CONFIG_SATA2 553 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 554 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 555 556 #define CONFIG_LBA48 557 #define CONFIG_CMD_SATA 558 #define CONFIG_DOS_PARTITION 559 #endif 560 561 #ifdef CONFIG_FMAN_ENET 562 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 563 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 564 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 565 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 566 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 567 568 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 569 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 570 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 571 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 572 573 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 574 575 #define CONFIG_SYS_TBIPA_VALUE 8 576 #define CONFIG_MII /* MII PHY management */ 577 #define CONFIG_ETHPRIME "FM1@DTSEC1" 578 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 579 #endif 580 581 /* 582 * Environment 583 */ 584 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 585 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 586 587 /* 588 * Command line configuration. 589 */ 590 #define CONFIG_CMD_ERRATA 591 #define CONFIG_CMD_IRQ 592 593 #ifdef CONFIG_PCI 594 #define CONFIG_CMD_PCI 595 #endif 596 597 /* 598 * USB 599 */ 600 #define CONFIG_HAS_FSL_DR_USB 601 #define CONFIG_HAS_FSL_MPH_USB 602 603 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 604 #define CONFIG_USB_EHCI 605 #define CONFIG_USB_EHCI_FSL 606 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 607 #endif 608 609 #ifdef CONFIG_MMC 610 #define CONFIG_FSL_ESDHC 611 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 612 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 613 #define CONFIG_GENERIC_MMC 614 #define CONFIG_DOS_PARTITION 615 #endif 616 617 /* Hash command with SHA acceleration supported in hardware */ 618 #ifdef CONFIG_FSL_CAAM 619 #define CONFIG_CMD_HASH 620 #define CONFIG_SHA_HW_ACCEL 621 #endif 622 623 /* 624 * Miscellaneous configurable options 625 */ 626 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 627 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 628 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 629 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 630 #ifdef CONFIG_CMD_KGDB 631 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 632 #else 633 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 634 #endif 635 /* Print Buffer Size */ 636 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 637 sizeof(CONFIG_SYS_PROMPT)+16) 638 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 639 /* Boot Argument Buffer Size */ 640 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 641 642 /* 643 * For booting Linux, the board info and command line data 644 * have to be in the first 64 MB of memory, since this is 645 * the maximum mapped by the Linux kernel during initialization. 646 */ 647 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 648 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 649 650 #ifdef CONFIG_CMD_KGDB 651 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 652 #endif 653 654 /* 655 * Environment Configuration 656 */ 657 #define CONFIG_ROOTPATH "/opt/nfsroot" 658 #define CONFIG_BOOTFILE "uImage" 659 #define CONFIG_UBOOTPATH u-boot.bin 660 661 /* default location for tftp and bootm */ 662 #define CONFIG_LOADADDR 1000000 663 664 665 #define CONFIG_BAUDRATE 115200 666 667 #define __USB_PHY_TYPE utmi 668 669 #define CONFIG_EXTRA_ENV_SETTINGS \ 670 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 671 "bank_intlv=cs0_cs1\0" \ 672 "netdev=eth0\0" \ 673 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 674 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 675 "tftpflash=tftpboot $loadaddr $uboot && " \ 676 "protect off $ubootaddr +$filesize && " \ 677 "erase $ubootaddr +$filesize && " \ 678 "cp.b $loadaddr $ubootaddr $filesize && " \ 679 "protect on $ubootaddr +$filesize && " \ 680 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 681 "consoledev=ttyS0\0" \ 682 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 683 "usb_dr_mode=host\0" \ 684 "ramdiskaddr=2000000\0" \ 685 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 686 "fdtaddr=1e00000\0" \ 687 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 688 "bdev=sda3\0" 689 690 #define CONFIG_HDBOOT \ 691 "setenv bootargs root=/dev/$bdev rw " \ 692 "console=$consoledev,$baudrate $othbootargs;" \ 693 "tftp $loadaddr $bootfile;" \ 694 "tftp $fdtaddr $fdtfile;" \ 695 "bootm $loadaddr - $fdtaddr" 696 697 #define CONFIG_NFSBOOTCOMMAND \ 698 "setenv bootargs root=/dev/nfs rw " \ 699 "nfsroot=$serverip:$rootpath " \ 700 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 701 "console=$consoledev,$baudrate $othbootargs;" \ 702 "tftp $loadaddr $bootfile;" \ 703 "tftp $fdtaddr $fdtfile;" \ 704 "bootm $loadaddr - $fdtaddr" 705 706 #define CONFIG_RAMBOOTCOMMAND \ 707 "setenv bootargs root=/dev/ram rw " \ 708 "console=$consoledev,$baudrate $othbootargs;" \ 709 "tftp $ramdiskaddr $ramdiskfile;" \ 710 "tftp $loadaddr $bootfile;" \ 711 "tftp $fdtaddr $fdtfile;" \ 712 "bootm $loadaddr $ramdiskaddr $fdtaddr" 713 714 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 715 716 #include <asm/fsl_secure_boot.h> 717 718 #endif /* __CONFIG_H */ 719