1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * P2041 RDB board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #define CONFIG_P2041RDB 31 #define CONFIG_PHYS_64BIT 32 #define CONFIG_PPC_P2041 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_BOOKE 41 #define CONFIG_E500 /* BOOKE e500 family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 45 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 46 #define CONFIG_MP /* support multiple processors */ 47 48 #ifndef CONFIG_SYS_TEXT_BASE 49 #define CONFIG_SYS_TEXT_BASE 0xeff80000 50 #endif 51 52 #ifndef CONFIG_RESET_VECTOR_ADDRESS 53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 54 #endif 55 56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 57 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 58 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 59 #define CONFIG_PCI /* Enable PCI/PCIE */ 60 #define CONFIG_PCIE1 /* PCIE controler 1 */ 61 #define CONFIG_PCIE2 /* PCIE controler 2 */ 62 #define CONFIG_PCIE3 /* PCIE controler 3 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_SYS_SRIO 67 #define CONFIG_SRIO1 /* SRIO port 1 */ 68 #define CONFIG_SRIO2 /* SRIO port 2 */ 69 70 #define CONFIG_FSL_LAW /* Use common FSL init code */ 71 72 #define CONFIG_ENV_OVERWRITE 73 74 #ifdef CONFIG_SYS_NO_FLASH 75 #define CONFIG_ENV_IS_NOWHERE 76 #else 77 #define CONFIG_FLASH_CFI_DRIVER 78 #define CONFIG_SYS_FLASH_CFI 79 #endif 80 81 #if defined(CONFIG_SPIFLASH) 82 #define CONFIG_SYS_EXTRA_ENV_RELOC 83 #define CONFIG_ENV_IS_IN_SPI_FLASH 84 #define CONFIG_ENV_SPI_BUS 0 85 #define CONFIG_ENV_SPI_CS 0 86 #define CONFIG_ENV_SPI_MAX_HZ 10000000 87 #define CONFIG_ENV_SPI_MODE 0 88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 90 #define CONFIG_ENV_SECT_SIZE 0x10000 91 #elif defined(CONFIG_SDCARD) 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_ENV_IS_IN_MMC 94 #define CONFIG_SYS_MMC_ENV_DEV 0 95 #define CONFIG_ENV_SIZE 0x2000 96 #define CONFIG_ENV_OFFSET (512 * 1097) 97 #else 98 #define CONFIG_ENV_IS_IN_FLASH 99 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 100 - CONFIG_ENV_SECT_SIZE) 101 #define CONFIG_ENV_SIZE 0x2000 102 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 103 #endif 104 105 #define CONFIG_SYS_CLK_FREQ 66666666 106 107 /* 108 * These can be toggled for performance analysis, otherwise use default. 109 */ 110 #define CONFIG_SYS_CACHE_STASHING 111 #define CONFIG_BACKSIDE_L2_CACHE 112 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 113 #define CONFIG_BTB /* toggle branch predition */ 114 115 #define CONFIG_ENABLE_36BIT_PHYS 116 117 #ifdef CONFIG_PHYS_64BIT 118 #define CONFIG_ADDR_MAP 119 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 120 #endif 121 122 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 123 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 124 #define CONFIG_SYS_MEMTEST_END 0x00400000 125 #define CONFIG_SYS_ALT_MEMTEST 126 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 127 128 /* 129 * Config the L3 Cache as L3 SRAM 130 */ 131 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 132 #ifdef CONFIG_PHYS_64BIT 133 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 134 CONFIG_RAMBOOT_TEXT_BASE) 135 #else 136 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 137 #endif 138 #define CONFIG_SYS_L3_SIZE (1024 << 10) 139 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 140 141 #ifdef CONFIG_PHYS_64BIT 142 #define CONFIG_SYS_DCSRBAR 0xf0000000 143 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 144 #endif 145 146 /* EEPROM */ 147 #define CONFIG_ID_EEPROM 148 #define CONFIG_SYS_I2C_EEPROM_NXID 149 #define CONFIG_SYS_EEPROM_BUS_NUM 0 150 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 151 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 152 153 /* 154 * DDR Setup 155 */ 156 #define CONFIG_VERY_BIG_RAM 157 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 158 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 159 160 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 161 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 162 163 #define CONFIG_DDR_SPD 164 #define CONFIG_FSL_DDR3 165 166 #define CONFIG_SYS_SPD_BUS_NUM 0 167 #define SPD_EEPROM_ADDRESS 0x52 168 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 169 170 /* 171 * Local Bus Definitions 172 */ 173 174 /* Set the local bus clock 1/8 of platform clock */ 175 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 176 177 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ 178 #ifdef CONFIG_PHYS_64BIT 179 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 180 #else 181 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 182 #endif 183 184 #define CONFIG_SYS_BR0_PRELIM \ 185 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 186 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 187 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 188 189 #define CONFIG_FSL_CPLD 190 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 191 #ifdef CONFIG_PHYS_64BIT 192 #define CPLD_BASE_PHYS 0xfffdf0000ull 193 #else 194 #define CPLD_BASE_PHYS CPLD_BASE 195 #endif 196 197 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 198 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 199 200 #define PIXIS_LBMAP_SWITCH 7 201 #define PIXIS_LBMAP_MASK 0xf0 202 #define PIXIS_LBMAP_SHIFT 4 203 #define PIXIS_LBMAP_ALTBANK 0x40 204 205 #define CONFIG_SYS_FLASH_QUIET_TEST 206 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 207 208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 212 213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 214 215 #if defined(CONFIG_RAMBOOT_PBL) 216 #define CONFIG_SYS_RAMBOOT 217 #endif 218 219 #define CONFIG_SYS_FLASH_EMPTY_INFO 220 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 222 223 #define CONFIG_BOARD_EARLY_INIT_F 224 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 225 #define CONFIG_MISC_INIT_R 226 227 #define CONFIG_HWCONFIG 228 229 /* define to use L1 as initial stack */ 230 #define CONFIG_L1_INIT_RAM 231 #define CONFIG_SYS_INIT_RAM_LOCK 232 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 233 #ifdef CONFIG_PHYS_64BIT 234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 235 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 236 /* The assembler doesn't like typecast */ 237 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 238 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 239 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 240 #else 241 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 243 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 244 #endif 245 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 246 247 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 248 GENERATED_GBL_DATA_SIZE) 249 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 250 251 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 252 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 253 254 /* Serial Port - controlled on board with jumper J8 255 * open - index 2 256 * shorted - index 1 257 */ 258 #define CONFIG_CONS_INDEX 1 259 #define CONFIG_SYS_NS16550 260 #define CONFIG_SYS_NS16550_SERIAL 261 #define CONFIG_SYS_NS16550_REG_SIZE 1 262 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 263 264 #define CONFIG_SYS_BAUDRATE_TABLE \ 265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 266 267 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 268 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 269 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 270 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 271 272 /* Use the HUSH parser */ 273 #define CONFIG_SYS_HUSH_PARSER 274 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 275 276 /* pass open firmware flat tree */ 277 #define CONFIG_OF_LIBFDT 278 #define CONFIG_OF_BOARD_SETUP 279 #define CONFIG_OF_STDOUT_VIA_ALIAS 280 281 /* new uImage format support */ 282 #define CONFIG_FIT 283 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 284 285 /* I2C */ 286 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 287 #define CONFIG_HARD_I2C /* I2C with hardware support */ 288 #define CONFIG_I2C_MULTI_BUS 289 #define CONFIG_I2C_CMD_TREE 290 #define CONFIG_SYS_I2C_SPEED 400000 291 #define CONFIG_SYS_I2C_SLAVE 0x7F 292 #define CONFIG_SYS_I2C_OFFSET 0x118000 293 #define CONFIG_SYS_I2C2_OFFSET 0x118100 294 295 /* 296 * RapidIO 297 */ 298 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 299 #ifdef CONFIG_PHYS_64BIT 300 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 301 #else 302 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 303 #endif 304 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 305 306 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 307 #ifdef CONFIG_PHYS_64BIT 308 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 309 #else 310 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 311 #endif 312 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 313 314 /* 315 * eSPI - Enhanced SPI 316 */ 317 #define CONFIG_FSL_ESPI 318 #define CONFIG_SPI_FLASH 319 #define CONFIG_SPI_FLASH_SPANSION 320 #define CONFIG_CMD_SF 321 #define CONFIG_SF_DEFAULT_SPEED 10000000 322 #define CONFIG_SF_DEFAULT_MODE 0 323 324 /* 325 * General PCI 326 * Memory space is mapped 1-1, but I/O space must start from 0. 327 */ 328 329 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 330 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 331 #ifdef CONFIG_PHYS_64BIT 332 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 333 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 334 #else 335 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 336 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 337 #endif 338 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 339 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 340 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 341 #ifdef CONFIG_PHYS_64BIT 342 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 343 #else 344 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 345 #endif 346 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 347 348 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 349 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 350 #ifdef CONFIG_PHYS_64BIT 351 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 352 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 353 #else 354 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 355 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 356 #endif 357 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 358 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 359 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 360 #ifdef CONFIG_PHYS_64BIT 361 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 362 #else 363 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 364 #endif 365 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 366 367 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 368 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 369 #ifdef CONFIG_PHYS_64BIT 370 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 371 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 372 #else 373 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 374 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 375 #endif 376 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 377 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 378 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 379 #ifdef CONFIG_PHYS_64BIT 380 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 381 #else 382 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 383 #endif 384 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 385 386 /* Qman/Bman */ 387 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 388 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 389 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 390 #ifdef CONFIG_PHYS_64BIT 391 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 392 #else 393 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 394 #endif 395 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 396 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 397 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 398 #ifdef CONFIG_PHYS_64BIT 399 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 400 #else 401 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 402 #endif 403 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 404 405 #define CONFIG_SYS_DPAA_FMAN 406 #define CONFIG_SYS_DPAA_PME 407 /* Default address of microcode for the Linux Fman driver */ 408 #define CONFIG_SYS_FMAN_FW 409 #if defined(CONFIG_SPIFLASH) 410 /* 411 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 412 * env, so we got 0x110000. 413 */ 414 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 415 #elif defined(CONFIG_SDCARD) 416 /* 417 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 418 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 419 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 420 */ 421 #define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) 422 #elif defined(CONFIG_NAND) 423 #define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 424 #else 425 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 426 #endif 427 #define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 428 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) 429 430 #ifdef CONFIG_SYS_DPAA_FMAN 431 #define CONFIG_FMAN_ENET 432 #endif 433 434 #ifdef CONFIG_PCI 435 #define CONFIG_NET_MULTI 436 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 437 #define CONFIG_E1000 438 439 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 440 #define CONFIG_DOS_PARTITION 441 #endif /* CONFIG_PCI */ 442 443 /* SATA */ 444 #define CONFIG_FSL_SATA_V2 445 #ifdef CONFIG_FSL_SATA_V2 446 #define CONFIG_LIBATA 447 #define CONFIG_FSL_SATA 448 449 #define CONFIG_SYS_SATA_MAX_DEVICE 2 450 #define CONFIG_SATA1 451 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 452 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 453 #define CONFIG_SATA2 454 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 455 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 456 457 #define CONFIG_LBA48 458 #define CONFIG_CMD_SATA 459 #define CONFIG_DOS_PARTITION 460 #define CONFIG_CMD_EXT2 461 #endif 462 463 #ifdef CONFIG_FMAN_ENET 464 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 465 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 466 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 467 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 468 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 469 470 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 471 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 472 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 473 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 474 475 #define CONFIG_SYS_TBIPA_VALUE 8 476 #define CONFIG_MII /* MII PHY management */ 477 #define CONFIG_ETHPRIME "FM1@DTSEC1" 478 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 479 #endif 480 481 /* 482 * Environment 483 */ 484 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 485 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 486 487 /* 488 * Command line configuration. 489 */ 490 #include <config_cmd_default.h> 491 492 #define CONFIG_CMD_DHCP 493 #define CONFIG_CMD_ELF 494 #define CONFIG_CMD_ERRATA 495 #define CONFIG_CMD_GREPENV 496 #define CONFIG_CMD_IRQ 497 #define CONFIG_CMD_I2C 498 #define CONFIG_CMD_MII 499 #define CONFIG_CMD_PING 500 #define CONFIG_CMD_SETEXPR 501 502 #ifdef CONFIG_PCI 503 #define CONFIG_CMD_PCI 504 #define CONFIG_CMD_NET 505 #endif 506 507 /* 508 * USB 509 */ 510 #define CONFIG_CMD_USB 511 #define CONFIG_USB_STORAGE 512 #define CONFIG_USB_EHCI 513 #define CONFIG_USB_EHCI_FSL 514 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 515 #define CONFIG_CMD_EXT2 516 517 #define CONFIG_MMC 518 519 #ifdef CONFIG_MMC 520 #define CONFIG_FSL_ESDHC 521 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 522 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 523 #define CONFIG_CMD_MMC 524 #define CONFIG_GENERIC_MMC 525 #define CONFIG_CMD_EXT2 526 #define CONFIG_CMD_FAT 527 #define CONFIG_DOS_PARTITION 528 #endif 529 530 /* 531 * Miscellaneous configurable options 532 */ 533 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 534 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 535 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 536 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 537 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 538 #ifdef CONFIG_CMD_KGDB 539 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 540 #else 541 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 542 #endif 543 /* Print Buffer Size */ 544 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 545 sizeof(CONFIG_SYS_PROMPT)+16) 546 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 547 /* Boot Argument Buffer Size */ 548 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 549 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ 550 551 /* 552 * For booting Linux, the board info and command line data 553 * have to be in the first 64 MB of memory, since this is 554 * the maximum mapped by the Linux kernel during initialization. 555 */ 556 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 557 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 558 559 #ifdef CONFIG_CMD_KGDB 560 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 561 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 562 #endif 563 564 /* 565 * Environment Configuration 566 */ 567 #define CONFIG_ROOTPATH /opt/nfsroot 568 #define CONFIG_BOOTFILE uImage 569 #define CONFIG_UBOOTPATH u-boot.bin 570 571 /* default location for tftp and bootm */ 572 #define CONFIG_LOADADDR 1000000 573 574 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 575 576 #define CONFIG_BAUDRATE 115200 577 578 #define __USB_PHY_TYPE utmi 579 580 #define CONFIG_EXTRA_ENV_SETTINGS \ 581 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 582 "bank_intlv=cs0_cs1\0" \ 583 "netdev=eth0\0" \ 584 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 585 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 586 "tftpflash=tftpboot $loadaddr $uboot && " \ 587 "protect off $ubootaddr +$filesize && " \ 588 "erase $ubootaddr +$filesize && " \ 589 "cp.b $loadaddr $ubootaddr $filesize && " \ 590 "protect on $ubootaddr +$filesize && " \ 591 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 592 "consoledev=ttyS0\0" \ 593 "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \ 594 "usb_dr_mode=host\0" \ 595 "ramdiskaddr=2000000\0" \ 596 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 597 "fdtaddr=c00000\0" \ 598 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 599 "bdev=sda3\0" \ 600 "c=ffe\0" 601 602 #define CONFIG_HDBOOT \ 603 "setenv bootargs root=/dev/$bdev rw " \ 604 "console=$consoledev,$baudrate $othbootargs;" \ 605 "tftp $loadaddr $bootfile;" \ 606 "tftp $fdtaddr $fdtfile;" \ 607 "bootm $loadaddr - $fdtaddr" 608 609 #define CONFIG_NFSBOOTCOMMAND \ 610 "setenv bootargs root=/dev/nfs rw " \ 611 "nfsroot=$serverip:$rootpath " \ 612 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 613 "console=$consoledev,$baudrate $othbootargs;" \ 614 "tftp $loadaddr $bootfile;" \ 615 "tftp $fdtaddr $fdtfile;" \ 616 "bootm $loadaddr - $fdtaddr" 617 618 #define CONFIG_RAMBOOTCOMMAND \ 619 "setenv bootargs root=/dev/ram rw " \ 620 "console=$consoledev,$baudrate $othbootargs;" \ 621 "tftp $ramdiskaddr $ramdiskfile;" \ 622 "tftp $loadaddr $bootfile;" \ 623 "tftp $fdtaddr $fdtfile;" \ 624 "bootm $loadaddr $ramdiskaddr $fdtaddr" 625 626 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 627 628 #ifdef CONFIG_SECURE_BOOT 629 #include <asm/fsl_secure_boot.h> 630 #endif 631 632 #endif /* __CONFIG_H */ 633