1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * Authors: Roy Zang <tie-fei.zang@freescale.com> 5 * Chunhe Lan <Chunhe.Lan@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifndef CONFIG_SYS_TEXT_BASE 14 #define CONFIG_SYS_TEXT_BASE 0xeff40000 15 #endif 16 17 #ifndef CONFIG_SYS_MONITOR_BASE 18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 19 #endif 20 21 #ifndef CONFIG_RESET_VECTOR_ADDRESS 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 23 #endif 24 25 /* High Level Configuration Options */ 26 #define CONFIG_MP /* support multiple processors */ 27 28 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 29 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 30 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 31 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 32 #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ 33 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 34 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 35 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 36 37 #ifndef __ASSEMBLY__ 38 extern unsigned long get_clock_freq(void); 39 #endif 40 41 #define CONFIG_SYS_CLK_FREQ 66666666 42 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 43 44 /* 45 * These can be toggled for performance analysis, otherwise use default. 46 */ 47 #define CONFIG_L2_CACHE /* toggle L2 cache */ 48 #define CONFIG_BTB /* toggle branch predition */ 49 #define CONFIG_HWCONFIG 50 51 #define CONFIG_ENABLE_36BIT_PHYS 52 53 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 54 #define CONFIG_SYS_MEMTEST_END 0x02000000 55 56 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 57 58 /* Implement conversion of addresses in the LBC */ 59 #define CONFIG_SYS_LBC_LBCR 0x00000000 60 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 61 62 /* DDR Setup */ 63 #define CONFIG_VERY_BIG_RAM 64 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 65 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 66 67 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 68 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 69 70 #define CONFIG_DDR_SPD 71 #define CONFIG_SYS_FSL_DDR3 72 #define CONFIG_FSL_DDR_INTERACTIVE 73 #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ 74 #define CONFIG_SYS_SPD_BUS_NUM 0 75 #define SPD_EEPROM_ADDRESS 0x50 76 #define CONFIG_SYS_DDR_RAW_TIMING 77 78 /* 79 * Memory map 80 * 81 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable 82 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 83 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 84 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 85 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable 86 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable 87 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 88 * 89 * Localbus non-cacheable 90 * 91 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable 92 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 93 */ 94 95 /* 96 * Local Bus Definitions 97 */ 98 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ 99 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 100 101 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 102 | BR_PS_16 | BR_V) 103 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 104 105 #define CONFIG_FLASH_CFI_DRIVER 106 #define CONFIG_SYS_FLASH_CFI 107 #define CONFIG_SYS_FLASH_EMPTY_INFO 108 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 109 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 113 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ 114 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 115 116 #define CONFIG_SYS_INIT_RAM_LOCK 117 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 118 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ 119 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 120 GENERATED_GBL_DATA_SIZE) 121 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 122 123 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */ 124 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 125 126 #define CONFIG_SYS_NAND_BASE 0xffa00000 127 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 128 129 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 130 #define CONFIG_SYS_MAX_NAND_DEVICE 1 131 #define CONFIG_CMD_NAND 132 #define CONFIG_NAND_FSL_ELBC 133 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 134 135 /* NAND flash config */ 136 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 137 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 138 | BR_PS_8 /* Port Size = 8bit */ \ 139 | BR_MS_FCM /* MSEL = FCM */ \ 140 | BR_V) /* valid */ 141 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 142 | OR_FCM_PGS \ 143 | OR_FCM_CSCT \ 144 | OR_FCM_CST \ 145 | OR_FCM_CHT \ 146 | OR_FCM_SCY_1 \ 147 | OR_FCM_TRLX \ 148 | OR_FCM_EHTR) 149 150 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 151 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 152 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 153 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 154 155 /* Serial Port */ 156 #define CONFIG_CONS_INDEX 1 157 #undef CONFIG_SERIAL_SOFTWARE_FIFO 158 #define CONFIG_SYS_NS16550_SERIAL 159 #define CONFIG_SYS_NS16550_REG_SIZE 1 160 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 161 162 #define CONFIG_SYS_BAUDRATE_TABLE \ 163 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 164 165 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 166 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 167 168 /* I2C */ 169 #define CONFIG_SYS_I2C 170 #define CONFIG_SYS_I2C_FSL 171 #define CONFIG_SYS_FSL_I2C_SPEED 400000 172 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 173 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 174 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 175 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 176 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 177 178 /* 179 * I2C2 EEPROM 180 */ 181 #define CONFIG_ID_EEPROM 182 #ifdef CONFIG_ID_EEPROM 183 #define CONFIG_SYS_I2C_EEPROM_NXID 184 #endif 185 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 186 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 187 #define CONFIG_SYS_EEPROM_BUS_NUM 0 188 189 /* 190 * General PCI 191 * Memory space is mapped 1-1, but I/O space must start from 0. 192 */ 193 194 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 195 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 196 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 197 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 198 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 199 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 200 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 201 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 202 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 203 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 204 205 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 206 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 207 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 208 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 209 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 210 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 211 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 212 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 213 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 214 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 215 216 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 217 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 218 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 219 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 220 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 221 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 222 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 223 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 224 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 225 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 226 227 #if defined(CONFIG_PCI) 228 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 229 #endif /* CONFIG_PCI */ 230 231 /* 232 * Environment 233 */ 234 #define CONFIG_ENV_OVERWRITE 235 236 #define CONFIG_ENV_IS_IN_FLASH 237 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 238 #define CONFIG_ENV_SIZE 0x2000 239 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 240 241 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 242 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 243 244 /* 245 * Command line configuration. 246 */ 247 #define CONFIG_CMD_IRQ 248 #define CONFIG_CMD_REGINFO 249 250 #if defined(CONFIG_PCI) 251 #define CONFIG_CMD_PCI 252 #endif 253 254 /* 255 * USB 256 */ 257 #define CONFIG_HAS_FSL_DR_USB 258 #ifdef CONFIG_HAS_FSL_DR_USB 259 #define CONFIG_USB_EHCI 260 261 #ifdef CONFIG_USB_EHCI 262 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 263 #define CONFIG_USB_EHCI_FSL 264 #define CONFIG_DOS_PARTITION 265 #endif 266 #endif 267 268 /* 269 * Miscellaneous configurable options 270 */ 271 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 272 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 273 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 274 #if defined(CONFIG_CMD_KGDB) 275 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 276 #else 277 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 278 #endif 279 /* Print Buffer Size */ 280 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) 281 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 282 /* Boot Argument Buffer Size */ 283 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 284 285 /* 286 * For booting Linux, the board info and command line data 287 * have to be in the first 64 MB of memory, since this is 288 * the maximum mapped by the Linux kernel during initialization. 289 */ 290 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 291 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 292 293 /* 294 * Environment Configuration 295 */ 296 #define CONFIG_BOOTFILE "uImage" 297 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ 298 299 /* default location for tftp and bootm */ 300 #define CONFIG_LOADADDR 1000000 301 302 303 #define CONFIG_BAUDRATE 115200 304 305 /* Qman/Bman */ 306 #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ 307 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 308 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 309 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 310 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 311 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 312 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 313 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 314 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 315 CONFIG_SYS_QMAN_CENA_SIZE) 316 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 317 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 318 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 319 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 320 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 321 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 322 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 323 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 324 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 325 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 326 CONFIG_SYS_BMAN_CENA_SIZE) 327 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 328 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 329 330 /* For FM */ 331 #define CONFIG_SYS_DPAA_FMAN 332 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 333 334 #ifdef CONFIG_SYS_DPAA_FMAN 335 #define CONFIG_FMAN_ENET 336 #define CONFIG_PHY_ATHEROS 337 #endif 338 339 /* Default address of microcode for the Linux Fman driver */ 340 /* QE microcode/firmware address */ 341 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 342 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 343 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 344 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 345 346 #ifdef CONFIG_FMAN_ENET 347 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 348 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 349 350 #define CONFIG_SYS_TBIPA_VALUE 8 351 #define CONFIG_MII /* MII PHY management */ 352 #define CONFIG_ETHPRIME "FM1@DTSEC1" 353 #endif 354 355 #define CONFIG_EXTRA_ENV_SETTINGS \ 356 "netdev=eth0\0" \ 357 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 358 "loadaddr=1000000\0" \ 359 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 360 "tftpflash=tftpboot $loadaddr $uboot; " \ 361 "protect off $ubootaddr +$filesize; " \ 362 "erase $ubootaddr +$filesize; " \ 363 "cp.b $loadaddr $ubootaddr $filesize; " \ 364 "protect on $ubootaddr +$filesize; " \ 365 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 366 "consoledev=ttyS0\0" \ 367 "ramdiskaddr=2000000\0" \ 368 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 369 "fdtaddr=1e00000\0" \ 370 "fdtfile=p1023rdb.dtb\0" \ 371 "othbootargs=ramdisk_size=600000\0" \ 372 "bdev=sda1\0" \ 373 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 374 375 #define CONFIG_HDBOOT \ 376 "setenv bootargs root=/dev/$bdev rw " \ 377 "console=$consoledev,$baudrate $othbootargs;" \ 378 "tftp $loadaddr $bootfile;" \ 379 "tftp $fdtaddr $fdtfile;" \ 380 "bootm $loadaddr - $fdtaddr" 381 382 #define CONFIG_NFSBOOTCOMMAND \ 383 "setenv bootargs root=/dev/nfs rw " \ 384 "nfsroot=$serverip:$rootpath " \ 385 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 386 "console=$consoledev,$baudrate $othbootargs;" \ 387 "tftp $loadaddr $bootfile;" \ 388 "tftp $fdtaddr $fdtfile;" \ 389 "bootm $loadaddr - $fdtaddr" 390 391 #define CONFIG_RAMBOOTCOMMAND \ 392 "setenv bootargs root=/dev/ram rw " \ 393 "console=$consoledev,$baudrate $othbootargs;" \ 394 "tftp $ramdiskaddr $ramdiskfile;" \ 395 "tftp $loadaddr $bootfile;" \ 396 "tftp $fdtaddr $fdtfile;" \ 397 "bootm $loadaddr $ramdiskaddr $fdtaddr" 398 399 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 400 401 #endif /* __CONFIG_H */ 402