1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include "../board/freescale/common/ics307_clk.h" 16 17 #ifdef CONFIG_36BIT 18 #define CONFIG_PHYS_64BIT 19 #endif 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE /* BOOKE */ 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ 25 #define CONFIG_P1022 26 #define CONFIG_P1022DS 27 #define CONFIG_MP /* support multiple processors */ 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff80000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 38 #define CONFIG_PCI /* Enable PCI/PCIE */ 39 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 44 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 45 46 #ifdef CONFIG_PHYS_64BIT 47 #define CONFIG_ENABLE_36BIT_PHYS 48 #define CONFIG_ADDR_MAP 49 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 50 #endif 51 52 #define CONFIG_FSL_LAW /* Use common FSL init code */ 53 54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 56 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 57 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_L2_CACHE 62 #define CONFIG_BTB 63 64 #define CONFIG_SYS_MEMTEST_START 0x00000000 65 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 66 67 /* 68 * Base addresses -- Note these are effective addresses where the 69 * actual resources get mapped (not physical addresses) 70 */ 71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 72 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 73 #ifdef CONFIG_PHYS_64BIT 74 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull 75 #else 76 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 77 #endif 78 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 79 80 /* DDR Setup */ 81 #define CONFIG_DDR_SPD 82 #define CONFIG_VERY_BIG_RAM 83 #define CONFIG_FSL_DDR3 84 85 #ifdef CONFIG_DDR_ECC 86 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 87 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 88 #endif 89 90 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 91 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 92 93 #define CONFIG_NUM_DDR_CONTROLLERS 1 94 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 95 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 96 97 /* I2C addresses of SPD EEPROMs */ 98 #define CONFIG_SYS_SPD_BUS_NUM 1 99 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 100 101 /* 102 * Memory map 103 * 104 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 105 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 106 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 107 * 108 * Localbus cacheable (TBD) 109 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 110 * 111 * Localbus non-cacheable 112 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 113 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 114 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 115 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 116 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 117 */ 118 119 /* 120 * Local Bus Definitions 121 */ 122 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 123 #ifdef CONFIG_PHYS_64BIT 124 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 125 #else 126 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 127 #endif 128 129 #define CONFIG_FLASH_BR_PRELIM \ 130 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 131 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 132 133 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 134 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 135 136 #define CONFIG_SYS_BR1_PRELIM \ 137 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 138 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM 139 140 #define CONFIG_SYS_FLASH_BANKS_LIST \ 141 {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 142 #define CONFIG_SYS_FLASH_QUIET_TEST 143 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 144 145 #define CONFIG_SYS_MAX_FLASH_BANKS 2 146 #define CONFIG_SYS_MAX_FLASH_SECT 1024 147 148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 149 150 #define CONFIG_FLASH_CFI_DRIVER 151 #define CONFIG_SYS_FLASH_CFI 152 #define CONFIG_SYS_FLASH_EMPTY_INFO 153 154 #define CONFIG_BOARD_EARLY_INIT_F 155 #define CONFIG_BOARD_EARLY_INIT_R 156 #define CONFIG_MISC_INIT_R 157 #define CONFIG_HWCONFIG 158 159 #define CONFIG_FSL_NGPIXIS 160 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 161 #ifdef CONFIG_PHYS_64BIT 162 #define PIXIS_BASE_PHYS 0xfffdf0000ull 163 #else 164 #define PIXIS_BASE_PHYS PIXIS_BASE 165 #endif 166 167 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 168 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 169 170 #define PIXIS_LBMAP_SWITCH 7 171 #define PIXIS_LBMAP_MASK 0xF0 172 #define PIXIS_LBMAP_ALTBANK 0x20 173 174 #define CONFIG_SYS_INIT_RAM_LOCK 175 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 176 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 177 178 #define CONFIG_SYS_GBL_DATA_OFFSET \ 179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 181 182 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 183 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) 184 185 /* 186 * Serial Port 187 */ 188 #define CONFIG_CONS_INDEX 1 189 #define CONFIG_SYS_NS16550 190 #define CONFIG_SYS_NS16550_SERIAL 191 #define CONFIG_SYS_NS16550_REG_SIZE 1 192 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 193 194 #define CONFIG_SYS_BAUDRATE_TABLE \ 195 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 196 197 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 198 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 199 200 /* Use the HUSH parser */ 201 #define CONFIG_SYS_HUSH_PARSER 202 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 203 204 /* Video */ 205 #define CONFIG_FSL_DIU_FB 206 207 #ifdef CONFIG_FSL_DIU_FB 208 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 209 #define CONFIG_VIDEO 210 #define CONFIG_CMD_BMP 211 #define CONFIG_CFB_CONSOLE 212 #define CONFIG_VIDEO_SW_CURSOR 213 #define CONFIG_VGA_AS_SINGLE_DEVICE 214 #define CONFIG_VIDEO_LOGO 215 #define CONFIG_VIDEO_BMP_LOGO 216 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 217 /* 218 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 219 * disable empty flash sector detection, which is I/O-intensive. 220 */ 221 #undef CONFIG_SYS_FLASH_EMPTY_INFO 222 #endif 223 224 #ifndef CONFIG_FSL_DIU_FB 225 #define CONFIG_ATI 226 #endif 227 228 #ifdef CONFIG_ATI 229 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 230 #define CONFIG_VIDEO 231 #define CONFIG_BIOSEMU 232 #define CONFIG_VIDEO_SW_CURSOR 233 #define CONFIG_ATI_RADEON_FB 234 #define CONFIG_VIDEO_LOGO 235 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 236 #define CONFIG_CFB_CONSOLE 237 #define CONFIG_VGA_AS_SINGLE_DEVICE 238 #endif 239 240 /* 241 * Pass open firmware flat tree 242 */ 243 #define CONFIG_OF_LIBFDT 244 #define CONFIG_OF_BOARD_SETUP 245 #define CONFIG_OF_STDOUT_VIA_ALIAS 246 247 /* new uImage format support */ 248 #define CONFIG_FIT 249 #define CONFIG_FIT_VERBOSE 250 251 /* I2C */ 252 #define CONFIG_FSL_I2C 253 #define CONFIG_HARD_I2C 254 #define CONFIG_I2C_MULTI_BUS 255 #define CONFIG_SYS_I2C_SPEED 400000 256 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 257 #define CONFIG_SYS_I2C_SLAVE 0x7F 258 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 259 #define CONFIG_SYS_I2C_OFFSET 0x3000 260 #define CONFIG_SYS_I2C2_OFFSET 0x3100 261 262 /* 263 * I2C2 EEPROM 264 */ 265 #define CONFIG_ID_EEPROM 266 #define CONFIG_SYS_I2C_EEPROM_NXID 267 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 268 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 269 #define CONFIG_SYS_EEPROM_BUS_NUM 1 270 271 /* 272 * General PCI 273 * Memory space is mapped 1-1, but I/O space must start from 0. 274 */ 275 276 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 277 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 280 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 281 #else 282 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 283 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 284 #endif 285 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 286 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 287 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 288 #ifdef CONFIG_PHYS_64BIT 289 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 290 #else 291 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 292 #endif 293 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 294 295 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 296 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 297 #ifdef CONFIG_PHYS_64BIT 298 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 299 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 300 #else 301 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 302 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 303 #endif 304 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 305 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 306 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 307 #ifdef CONFIG_PHYS_64BIT 308 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 309 #else 310 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 311 #endif 312 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 313 314 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 315 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 316 #ifdef CONFIG_PHYS_64BIT 317 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 318 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 319 #else 320 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 321 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 322 #endif 323 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 324 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 325 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 326 #ifdef CONFIG_PHYS_64BIT 327 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 328 #else 329 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 330 #endif 331 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 332 333 #ifdef CONFIG_PCI 334 #define CONFIG_NET_MULTI 335 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 336 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 337 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 338 #endif 339 340 /* SATA */ 341 #define CONFIG_LIBATA 342 #define CONFIG_FSL_SATA 343 #define CONFIG_FSL_SATA_V2 344 345 #define CONFIG_SYS_SATA_MAX_DEVICE 2 346 #define CONFIG_SATA1 347 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 348 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 349 #define CONFIG_SATA2 350 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 351 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 352 353 #ifdef CONFIG_FSL_SATA 354 #define CONFIG_LBA48 355 #define CONFIG_CMD_SATA 356 #define CONFIG_DOS_PARTITION 357 #define CONFIG_CMD_EXT2 358 #endif 359 360 #define CONFIG_MMC 361 #ifdef CONFIG_MMC 362 #define CONFIG_CMD_MMC 363 #define CONFIG_FSL_ESDHC 364 #define CONFIG_GENERIC_MMC 365 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 366 #endif 367 368 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 369 #define CONFIG_CMD_EXT2 370 #define CONFIG_CMD_FAT 371 #define CONFIG_DOS_PARTITION 372 #endif 373 374 #define CONFIG_TSEC_ENET 375 #ifdef CONFIG_TSEC_ENET 376 377 #define CONFIG_TSECV2 378 #define CONFIG_NET_MULTI 379 380 #define CONFIG_MII /* MII PHY management */ 381 #define CONFIG_TSEC1 1 382 #define CONFIG_TSEC1_NAME "eTSEC1" 383 #define CONFIG_TSEC2 1 384 #define CONFIG_TSEC2_NAME "eTSEC2" 385 386 #define TSEC1_PHY_ADDR 1 387 #define TSEC2_PHY_ADDR 2 388 389 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 390 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 391 392 #define TSEC1_PHYIDX 0 393 #define TSEC2_PHYIDX 0 394 395 #define CONFIG_ETHPRIME "eTSEC1" 396 397 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 398 #endif 399 400 /* 401 * Environment 402 */ 403 #define CONFIG_ENV_IS_IN_FLASH 404 #define CONFIG_ENV_OVERWRITE 405 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 406 #define CONFIG_ENV_SIZE 0x2000 407 #define CONFIG_ENV_SECT_SIZE 0x20000 408 409 #define CONFIG_LOADS_ECHO 410 #define CONFIG_SYS_LOADS_BAUD_CHANGE 411 412 /* 413 * Command line configuration. 414 */ 415 #include <config_cmd_default.h> 416 417 #define CONFIG_CMD_ELF 418 #define CONFIG_CMD_ERRATA 419 #define CONFIG_CMD_IRQ 420 #define CONFIG_CMD_I2C 421 #define CONFIG_CMD_MII 422 #define CONFIG_CMD_PING 423 #define CONFIG_CMD_SETEXPR 424 #define CONFIG_CMD_REGINFO 425 426 #ifdef CONFIG_PCI 427 #define CONFIG_CMD_PCI 428 #define CONFIG_CMD_NET 429 #endif 430 431 /* 432 * USB 433 */ 434 #define CONFIG_USB_EHCI 435 436 #ifdef CONFIG_USB_EHCI 437 #define CONFIG_CMD_USB 438 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 439 #define CONFIG_USB_EHCI_FSL 440 #define CONFIG_USB_STORAGE 441 #define CONFIG_CMD_FAT 442 #endif 443 444 /* 445 * Miscellaneous configurable options 446 */ 447 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 448 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 449 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 450 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 451 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 452 #ifdef CONFIG_CMD_KGDB 453 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 454 #else 455 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 456 #endif 457 /* Print Buffer Size */ 458 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 459 #define CONFIG_SYS_MAXARGS 16 460 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 461 #define CONFIG_SYS_HZ 1000 462 463 /* 464 * For booting Linux, the board info and command line data 465 * have to be in the first 16 MB of memory, since this is 466 * the maximum mapped by the Linux kernel during initialization. 467 */ 468 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 469 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 470 471 #ifdef CONFIG_CMD_KGDB 472 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 473 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 474 #endif 475 476 /* 477 * Environment Configuration 478 */ 479 480 #define CONFIG_HOSTNAME p1022ds 481 #define CONFIG_ROOTPATH /opt/nfsroot 482 #define CONFIG_BOOTFILE uImage 483 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 484 485 #define CONFIG_LOADADDR 1000000 486 487 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 488 #define CONFIG_BOOTARGS 489 490 #define CONFIG_BAUDRATE 115200 491 492 #define CONFIG_EXTRA_ENV_SETTINGS \ 493 "perf_mode=stable\0" \ 494 "memctl_intlv_ctl=2\0" \ 495 "netdev=eth0\0" \ 496 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 497 "tftpflash=tftpboot $loadaddr $uboot; " \ 498 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 499 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 500 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 501 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 502 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 503 "consoledev=ttyS0\0" \ 504 "ramdiskaddr=2000000\0" \ 505 "ramdiskfile=uramdisk\0" \ 506 "fdtaddr=c00000\0" \ 507 "fdtfile=p1022ds.dtb\0" \ 508 "bdev=sda3\0" \ 509 "diuregs=md e002c000 1d\0" \ 510 "dium=mw e002c01c\0" \ 511 "diuerr=md e002c014 1\0" \ 512 "hwconfig=esdhc;audclk:12\0" 513 514 #define CONFIG_HDBOOT \ 515 "setenv bootargs root=/dev/$bdev rw " \ 516 "console=$consoledev,$baudrate $othbootargs;" \ 517 "tftp $loadaddr $bootfile;" \ 518 "tftp $fdtaddr $fdtfile;" \ 519 "bootm $loadaddr - $fdtaddr" 520 521 #define CONFIG_NFSBOOTCOMMAND \ 522 "setenv bootargs root=/dev/nfs rw " \ 523 "nfsroot=$serverip:$rootpath " \ 524 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 525 "console=$consoledev,$baudrate $othbootargs;" \ 526 "tftp $loadaddr $bootfile;" \ 527 "tftp $fdtaddr $fdtfile;" \ 528 "bootm $loadaddr - $fdtaddr" 529 530 #define CONFIG_RAMBOOTCOMMAND \ 531 "setenv bootargs root=/dev/ram rw " \ 532 "console=$consoledev,$baudrate $othbootargs;" \ 533 "tftp $ramdiskaddr $ramdiskfile;" \ 534 "tftp $loadaddr $bootfile;" \ 535 "tftp $fdtaddr $fdtfile;" \ 536 "bootm $loadaddr $ramdiskaddr $fdtaddr" 537 538 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 539 540 #endif 541