1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 18 #define CONFIG_SPL_SERIAL_SUPPORT 19 #define CONFIG_SPL_MMC_SUPPORT 20 #define CONFIG_SPL_MMC_MINIMAL 21 #define CONFIG_SPL_FLUSH_IMAGE 22 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 23 #define CONFIG_SPL_LIBGENERIC_SUPPORT 24 #define CONFIG_SPL_LIBCOMMON_SUPPORT 25 #define CONFIG_SPL_I2C_SUPPORT 26 #define CONFIG_FSL_LAW /* Use common FSL init code */ 27 #define CONFIG_SYS_TEXT_BASE 0x11001000 28 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 29 #define CONFIG_SPL_PAD_TO 0x20000 30 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 31 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 32 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 33 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 34 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 35 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 36 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 37 #define CONFIG_SPL_MMC_BOOT 38 #ifdef CONFIG_SPL_BUILD 39 #define CONFIG_SPL_COMMON_INIT_DDR 40 #endif 41 #endif 42 43 #ifdef CONFIG_SPIFLASH 44 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 45 #define CONFIG_SPL_SERIAL_SUPPORT 46 #define CONFIG_SPL_SPI_SUPPORT 47 #define CONFIG_SPL_SPI_FLASH_SUPPORT 48 #define CONFIG_SPL_SPI_FLASH_MINIMAL 49 #define CONFIG_SPL_FLUSH_IMAGE 50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 51 #define CONFIG_SPL_LIBGENERIC_SUPPORT 52 #define CONFIG_SPL_LIBCOMMON_SUPPORT 53 #define CONFIG_SPL_I2C_SUPPORT 54 #define CONFIG_FSL_LAW /* Use common FSL init code */ 55 #define CONFIG_SYS_TEXT_BASE 0x11001000 56 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 57 #define CONFIG_SPL_PAD_TO 0x20000 58 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 65 #define CONFIG_SPL_SPI_BOOT 66 #ifdef CONFIG_SPL_BUILD 67 #define CONFIG_SPL_COMMON_INIT_DDR 68 #endif 69 #endif 70 71 #define CONFIG_NAND_FSL_ELBC 72 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 73 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 74 75 #ifdef CONFIG_NAND 76 #ifdef CONFIG_TPL_BUILD 77 #define CONFIG_SPL_NAND_BOOT 78 #define CONFIG_SPL_FLUSH_IMAGE 79 #define CONFIG_SPL_NAND_INIT 80 #define CONFIG_TPL_SERIAL_SUPPORT 81 #define CONFIG_TPL_LIBGENERIC_SUPPORT 82 #define CONFIG_TPL_LIBCOMMON_SUPPORT 83 #define CONFIG_TPL_I2C_SUPPORT 84 #define CONFIG_TPL_NAND_SUPPORT 85 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 86 #define CONFIG_SPL_COMMON_INIT_DDR 87 #define CONFIG_SPL_MAX_SIZE (128 << 10) 88 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 89 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 90 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 91 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 92 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 93 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 94 #elif defined(CONFIG_SPL_BUILD) 95 #define CONFIG_SPL_INIT_MINIMAL 96 #define CONFIG_SPL_SERIAL_SUPPORT 97 #define CONFIG_SPL_NAND_SUPPORT 98 #define CONFIG_SPL_FLUSH_IMAGE 99 #define CONFIG_SPL_TEXT_BASE 0xff800000 100 #define CONFIG_SPL_MAX_SIZE 4096 101 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 102 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 103 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 104 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 105 #endif 106 #define CONFIG_SPL_PAD_TO 0x20000 107 #define CONFIG_TPL_PAD_TO 0x20000 108 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 109 #define CONFIG_SYS_TEXT_BASE 0x11001000 110 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 111 #endif 112 113 /* High Level Configuration Options */ 114 #define CONFIG_BOOKE /* BOOKE */ 115 #define CONFIG_E500 /* BOOKE e500 family */ 116 #define CONFIG_P1022 117 #define CONFIG_P1022DS 118 #define CONFIG_MP /* support multiple processors */ 119 120 #ifndef CONFIG_SYS_TEXT_BASE 121 #define CONFIG_SYS_TEXT_BASE 0xeff40000 122 #endif 123 124 #ifndef CONFIG_RESET_VECTOR_ADDRESS 125 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 126 #endif 127 128 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 129 #define CONFIG_PCI /* Enable PCI/PCIE */ 130 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 131 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 132 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 133 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 134 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 135 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 136 137 #define CONFIG_ENABLE_36BIT_PHYS 138 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_ADDR_MAP 141 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 142 #endif 143 144 #define CONFIG_FSL_LAW /* Use common FSL init code */ 145 146 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 147 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 148 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 149 150 /* 151 * These can be toggled for performance analysis, otherwise use default. 152 */ 153 #define CONFIG_L2_CACHE 154 #define CONFIG_BTB 155 156 #define CONFIG_SYS_MEMTEST_START 0x00000000 157 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 158 159 #define CONFIG_SYS_CCSRBAR 0xffe00000 160 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 161 162 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 163 SPL code*/ 164 #ifdef CONFIG_SPL_BUILD 165 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 166 #endif 167 168 /* DDR Setup */ 169 #define CONFIG_DDR_SPD 170 #define CONFIG_VERY_BIG_RAM 171 #define CONFIG_SYS_FSL_DDR3 172 173 #ifdef CONFIG_DDR_ECC 174 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 175 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 176 #endif 177 178 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 179 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 180 181 #define CONFIG_NUM_DDR_CONTROLLERS 1 182 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 183 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 184 185 /* I2C addresses of SPD EEPROMs */ 186 #define CONFIG_SYS_SPD_BUS_NUM 1 187 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 188 189 /* These are used when DDR doesn't use SPD. */ 190 #define CONFIG_SYS_SDRAM_SIZE 2048 191 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 192 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 193 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 194 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 195 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 196 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 197 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 198 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 199 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 200 #define CONFIG_SYS_DDR_MODE_1 0x00441221 201 #define CONFIG_SYS_DDR_MODE_2 0x00000000 202 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 203 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 204 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 205 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 206 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 207 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 208 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 209 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 210 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 211 212 /* 213 * Memory map 214 * 215 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 216 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 217 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 218 * 219 * Localbus cacheable (TBD) 220 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 221 * 222 * Localbus non-cacheable 223 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 224 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 225 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 226 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 227 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 228 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 229 */ 230 231 /* 232 * Local Bus Definitions 233 */ 234 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 235 #ifdef CONFIG_PHYS_64BIT 236 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 237 #else 238 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 239 #endif 240 241 #define CONFIG_FLASH_BR_PRELIM \ 242 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 243 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 244 245 #ifdef CONFIG_NAND 246 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 247 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 248 #else 249 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 250 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 251 #endif 252 253 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 254 #define CONFIG_SYS_FLASH_QUIET_TEST 255 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 256 257 #define CONFIG_SYS_MAX_FLASH_BANKS 1 258 #define CONFIG_SYS_MAX_FLASH_SECT 1024 259 260 #ifndef CONFIG_SYS_MONITOR_BASE 261 #ifdef CONFIG_SPL_BUILD 262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 263 #else 264 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 265 #endif 266 #endif 267 268 #define CONFIG_FLASH_CFI_DRIVER 269 #define CONFIG_SYS_FLASH_CFI 270 #define CONFIG_SYS_FLASH_EMPTY_INFO 271 272 /* Nand Flash */ 273 #if defined(CONFIG_NAND_FSL_ELBC) 274 #define CONFIG_SYS_NAND_BASE 0xff800000 275 #ifdef CONFIG_PHYS_64BIT 276 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 277 #else 278 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 279 #endif 280 281 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 282 #define CONFIG_SYS_MAX_NAND_DEVICE 1 283 #define CONFIG_CMD_NAND 1 284 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 285 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 286 287 /* NAND flash config */ 288 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 289 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 290 | BR_PS_8 /* Port Size = 8 bit */ \ 291 | BR_MS_FCM /* MSEL = FCM */ \ 292 | BR_V) /* valid */ 293 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 294 | OR_FCM_PGS /* Large Page*/ \ 295 | OR_FCM_CSCT \ 296 | OR_FCM_CST \ 297 | OR_FCM_CHT \ 298 | OR_FCM_SCY_1 \ 299 | OR_FCM_TRLX \ 300 | OR_FCM_EHTR) 301 #ifdef CONFIG_NAND 302 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 303 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 304 #else 305 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 306 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 307 #endif 308 309 #endif /* CONFIG_NAND_FSL_ELBC */ 310 311 #define CONFIG_BOARD_EARLY_INIT_F 312 #define CONFIG_BOARD_EARLY_INIT_R 313 #define CONFIG_MISC_INIT_R 314 #define CONFIG_HWCONFIG 315 316 #define CONFIG_FSL_NGPIXIS 317 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 318 #ifdef CONFIG_PHYS_64BIT 319 #define PIXIS_BASE_PHYS 0xfffdf0000ull 320 #else 321 #define PIXIS_BASE_PHYS PIXIS_BASE 322 #endif 323 324 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 325 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 326 327 #define PIXIS_LBMAP_SWITCH 7 328 #define PIXIS_LBMAP_MASK 0xF0 329 #define PIXIS_LBMAP_ALTBANK 0x20 330 #define PIXIS_SPD 0x07 331 #define PIXIS_SPD_SYSCLK_MASK 0x07 332 #define PIXIS_ELBC_SPI_MASK 0xc0 333 #define PIXIS_SPI 0x80 334 335 #define CONFIG_SYS_INIT_RAM_LOCK 336 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 337 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 338 339 #define CONFIG_SYS_GBL_DATA_OFFSET \ 340 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 341 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 342 343 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 344 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 345 346 /* 347 * Config the L2 Cache as L2 SRAM 348 */ 349 #if defined(CONFIG_SPL_BUILD) 350 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 351 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 352 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 353 #define CONFIG_SYS_L2_SIZE (256 << 10) 354 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 355 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 356 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 357 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 358 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 359 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 360 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 361 #elif defined(CONFIG_NAND) 362 #ifdef CONFIG_TPL_BUILD 363 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 364 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 365 #define CONFIG_SYS_L2_SIZE (256 << 10) 366 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 367 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 368 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 369 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 370 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 371 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 372 #else 373 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 374 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 375 #define CONFIG_SYS_L2_SIZE (256 << 10) 376 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 377 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 378 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 379 #endif 380 #endif 381 #endif 382 383 /* 384 * Serial Port 385 */ 386 #define CONFIG_CONS_INDEX 1 387 #define CONFIG_SYS_NS16550_SERIAL 388 #define CONFIG_SYS_NS16550_REG_SIZE 1 389 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 390 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 391 #define CONFIG_NS16550_MIN_FUNCTIONS 392 #endif 393 394 #define CONFIG_SYS_BAUDRATE_TABLE \ 395 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 396 397 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 398 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 399 400 /* Video */ 401 402 #ifdef CONFIG_FSL_DIU_FB 403 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 404 #define CONFIG_VIDEO 405 #define CONFIG_CMD_BMP 406 #define CONFIG_CFB_CONSOLE 407 #define CONFIG_VIDEO_SW_CURSOR 408 #define CONFIG_VGA_AS_SINGLE_DEVICE 409 #define CONFIG_VIDEO_LOGO 410 #define CONFIG_VIDEO_BMP_LOGO 411 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 412 /* 413 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 414 * disable empty flash sector detection, which is I/O-intensive. 415 */ 416 #undef CONFIG_SYS_FLASH_EMPTY_INFO 417 #endif 418 419 #ifndef CONFIG_FSL_DIU_FB 420 #endif 421 422 #ifdef CONFIG_ATI 423 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 424 #define CONFIG_VIDEO 425 #define CONFIG_BIOSEMU 426 #define CONFIG_VIDEO_SW_CURSOR 427 #define CONFIG_ATI_RADEON_FB 428 #define CONFIG_VIDEO_LOGO 429 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 430 #define CONFIG_CFB_CONSOLE 431 #define CONFIG_VGA_AS_SINGLE_DEVICE 432 #endif 433 434 /* I2C */ 435 #define CONFIG_SYS_I2C 436 #define CONFIG_SYS_I2C_FSL 437 #define CONFIG_SYS_FSL_I2C_SPEED 400000 438 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 439 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 440 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 441 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 442 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 443 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 444 445 /* 446 * I2C2 EEPROM 447 */ 448 #define CONFIG_ID_EEPROM 449 #define CONFIG_SYS_I2C_EEPROM_NXID 450 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 451 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 452 #define CONFIG_SYS_EEPROM_BUS_NUM 1 453 454 /* 455 * eSPI - Enhanced SPI 456 */ 457 458 #define CONFIG_HARD_SPI 459 460 #define CONFIG_SF_DEFAULT_SPEED 10000000 461 #define CONFIG_SF_DEFAULT_MODE 0 462 463 /* 464 * General PCI 465 * Memory space is mapped 1-1, but I/O space must start from 0. 466 */ 467 468 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 469 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 472 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 473 #else 474 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 475 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 476 #endif 477 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 478 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 479 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 482 #else 483 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 484 #endif 485 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 486 487 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 488 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 491 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 492 #else 493 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 494 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 495 #endif 496 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 497 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 498 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 499 #ifdef CONFIG_PHYS_64BIT 500 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 501 #else 502 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 503 #endif 504 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 505 506 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 507 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 508 #ifdef CONFIG_PHYS_64BIT 509 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 510 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 511 #else 512 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 513 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 514 #endif 515 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 516 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 517 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 518 #ifdef CONFIG_PHYS_64BIT 519 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 520 #else 521 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 522 #endif 523 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 524 525 #ifdef CONFIG_PCI 526 #define CONFIG_PCI_INDIRECT_BRIDGE 527 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 528 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 529 #endif 530 531 /* SATA */ 532 #define CONFIG_LIBATA 533 #define CONFIG_FSL_SATA 534 #define CONFIG_FSL_SATA_V2 535 536 #define CONFIG_SYS_SATA_MAX_DEVICE 2 537 #define CONFIG_SATA1 538 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 539 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 540 #define CONFIG_SATA2 541 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 542 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 543 544 #ifdef CONFIG_FSL_SATA 545 #define CONFIG_LBA48 546 #define CONFIG_CMD_SATA 547 #define CONFIG_DOS_PARTITION 548 #endif 549 550 #define CONFIG_MMC 551 #ifdef CONFIG_MMC 552 #define CONFIG_FSL_ESDHC 553 #define CONFIG_GENERIC_MMC 554 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 555 #endif 556 557 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 558 #define CONFIG_DOS_PARTITION 559 #endif 560 561 #define CONFIG_TSEC_ENET 562 #ifdef CONFIG_TSEC_ENET 563 564 #define CONFIG_TSECV2 565 566 #define CONFIG_MII /* MII PHY management */ 567 #define CONFIG_TSEC1 1 568 #define CONFIG_TSEC1_NAME "eTSEC1" 569 #define CONFIG_TSEC2 1 570 #define CONFIG_TSEC2_NAME "eTSEC2" 571 572 #define TSEC1_PHY_ADDR 1 573 #define TSEC2_PHY_ADDR 2 574 575 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 576 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 577 578 #define TSEC1_PHYIDX 0 579 #define TSEC2_PHYIDX 0 580 581 #define CONFIG_ETHPRIME "eTSEC1" 582 583 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 584 #endif 585 586 /* 587 * Dynamic MTD Partition support with mtdparts 588 */ 589 #define CONFIG_MTD_DEVICE 590 #define CONFIG_MTD_PARTITIONS 591 #define CONFIG_CMD_MTDPARTS 592 #define CONFIG_FLASH_CFI_MTD 593 #ifdef CONFIG_PHYS_64BIT 594 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 595 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 596 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 597 "512k(dtb),768k(u-boot)" 598 #else 599 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 600 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 601 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 602 "512k(dtb),768k(u-boot)" 603 #endif 604 605 /* 606 * Environment 607 */ 608 #ifdef CONFIG_SPIFLASH 609 #define CONFIG_ENV_IS_IN_SPI_FLASH 610 #define CONFIG_ENV_SPI_BUS 0 611 #define CONFIG_ENV_SPI_CS 0 612 #define CONFIG_ENV_SPI_MAX_HZ 10000000 613 #define CONFIG_ENV_SPI_MODE 0 614 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 615 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 616 #define CONFIG_ENV_SECT_SIZE 0x10000 617 #elif defined(CONFIG_SDCARD) 618 #define CONFIG_ENV_IS_IN_MMC 619 #define CONFIG_FSL_FIXED_MMC_LOCATION 620 #define CONFIG_ENV_SIZE 0x2000 621 #define CONFIG_SYS_MMC_ENV_DEV 0 622 #elif defined(CONFIG_NAND) 623 #ifdef CONFIG_TPL_BUILD 624 #define CONFIG_ENV_SIZE 0x2000 625 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 626 #else 627 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 628 #endif 629 #define CONFIG_ENV_IS_IN_NAND 630 #define CONFIG_ENV_OFFSET (1024 * 1024) 631 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 632 #elif defined(CONFIG_SYS_RAMBOOT) 633 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 634 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 635 #define CONFIG_ENV_SIZE 0x2000 636 #else 637 #define CONFIG_ENV_IS_IN_FLASH 638 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 639 #define CONFIG_ENV_SIZE 0x2000 640 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 641 #endif 642 643 #define CONFIG_LOADS_ECHO 644 #define CONFIG_SYS_LOADS_BAUD_CHANGE 645 646 /* 647 * Command line configuration. 648 */ 649 #define CONFIG_CMD_ERRATA 650 #define CONFIG_CMD_IRQ 651 #define CONFIG_CMD_REGINFO 652 653 #ifdef CONFIG_PCI 654 #define CONFIG_CMD_PCI 655 #endif 656 657 /* 658 * USB 659 */ 660 #define CONFIG_HAS_FSL_DR_USB 661 #ifdef CONFIG_HAS_FSL_DR_USB 662 #define CONFIG_USB_EHCI 663 664 #ifdef CONFIG_USB_EHCI 665 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 666 #define CONFIG_USB_EHCI_FSL 667 #endif 668 #endif 669 670 /* 671 * Miscellaneous configurable options 672 */ 673 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 674 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 675 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 676 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 677 #ifdef CONFIG_CMD_KGDB 678 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 679 #else 680 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 681 #endif 682 /* Print Buffer Size */ 683 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 684 #define CONFIG_SYS_MAXARGS 16 685 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 686 687 /* 688 * For booting Linux, the board info and command line data 689 * have to be in the first 64 MB of memory, since this is 690 * the maximum mapped by the Linux kernel during initialization. 691 */ 692 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 693 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 694 695 #ifdef CONFIG_CMD_KGDB 696 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 697 #endif 698 699 /* 700 * Environment Configuration 701 */ 702 703 #define CONFIG_HOSTNAME p1022ds 704 #define CONFIG_ROOTPATH "/opt/nfsroot" 705 #define CONFIG_BOOTFILE "uImage" 706 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 707 708 #define CONFIG_LOADADDR 1000000 709 710 711 #define CONFIG_BAUDRATE 115200 712 713 #define CONFIG_EXTRA_ENV_SETTINGS \ 714 "netdev=eth0\0" \ 715 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 716 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 717 "tftpflash=tftpboot $loadaddr $uboot && " \ 718 "protect off $ubootaddr +$filesize && " \ 719 "erase $ubootaddr +$filesize && " \ 720 "cp.b $loadaddr $ubootaddr $filesize && " \ 721 "protect on $ubootaddr +$filesize && " \ 722 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 723 "consoledev=ttyS0\0" \ 724 "ramdiskaddr=2000000\0" \ 725 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 726 "fdtaddr=1e00000\0" \ 727 "fdtfile=p1022ds.dtb\0" \ 728 "bdev=sda3\0" \ 729 "hwconfig=esdhc;audclk:12\0" 730 731 #define CONFIG_HDBOOT \ 732 "setenv bootargs root=/dev/$bdev rw " \ 733 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 734 "tftp $loadaddr $bootfile;" \ 735 "tftp $fdtaddr $fdtfile;" \ 736 "bootm $loadaddr - $fdtaddr" 737 738 #define CONFIG_NFSBOOTCOMMAND \ 739 "setenv bootargs root=/dev/nfs rw " \ 740 "nfsroot=$serverip:$rootpath " \ 741 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 742 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 743 "tftp $loadaddr $bootfile;" \ 744 "tftp $fdtaddr $fdtfile;" \ 745 "bootm $loadaddr - $fdtaddr" 746 747 #define CONFIG_RAMBOOTCOMMAND \ 748 "setenv bootargs root=/dev/ram rw " \ 749 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 750 "tftp $ramdiskaddr $ramdiskfile;" \ 751 "tftp $loadaddr $bootfile;" \ 752 "tftp $fdtaddr $fdtfile;" \ 753 "bootm $loadaddr $ramdiskaddr $fdtaddr" 754 755 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 756 757 #endif 758