1 /* 2 * Copyright 2010 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include "../board/freescale/common/ics307_clk.h" 16 17 /* High Level Configuration Options */ 18 #define CONFIG_BOOKE /* BOOKE */ 19 #define CONFIG_E500 /* BOOKE e500 family */ 20 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ 21 #define CONFIG_P1022 22 #define CONFIG_P1022DS 23 #define CONFIG_MP /* support multiple processors */ 24 25 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 26 #define CONFIG_PCI /* Enable PCI/PCIE */ 27 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 28 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 29 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 30 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 31 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 32 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 33 34 #define CONFIG_PHYS_64BIT 35 #define CONFIG_ENABLE_36BIT_PHYS 36 #define CONFIG_ADDR_MAP 37 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 38 39 #define CONFIG_FSL_LAW /* Use common FSL init code */ 40 41 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 42 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 43 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 44 45 /* 46 * These can be toggled for performance analysis, otherwise use default. 47 */ 48 #define CONFIG_L2_CACHE 49 #define CONFIG_BTB 50 51 #define CONFIG_SYS_MEMTEST_START 0x00000000 52 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 53 54 /* 55 * Base addresses -- Note these are effective addresses where the 56 * actual resources get mapped (not physical addresses) 57 */ 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 59 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 60 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull 61 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 62 63 /* DDR Setup */ 64 #define CONFIG_DDR_SPD 65 #define CONFIG_VERY_BIG_RAM 66 #define CONFIG_FSL_DDR3 67 68 #ifdef CONFIG_DDR_ECC 69 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 70 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 71 #endif 72 73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 75 76 #define CONFIG_NUM_DDR_CONTROLLERS 1 77 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 78 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 79 80 /* I2C addresses of SPD EEPROMs */ 81 #define CONFIG_SYS_SPD_BUS_NUM 1 82 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 83 84 /* 85 * Memory map 86 * 87 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 88 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 89 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 90 * 91 * Localbus cacheable (TBD) 92 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 93 * 94 * Localbus non-cacheable 95 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 96 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 97 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 98 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 99 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 100 */ 101 102 /* 103 * Local Bus Definitions 104 */ 105 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 106 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 107 108 #define CONFIG_FLASH_BR_PRELIM \ 109 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 110 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 111 112 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 113 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 114 115 #define CONFIG_SYS_BR1_PRELIM \ 116 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 117 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM 118 119 #define CONFIG_SYS_FLASH_BANKS_LIST \ 120 {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 121 #define CONFIG_SYS_FLASH_QUIET_TEST 122 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 123 124 #define CONFIG_SYS_MAX_FLASH_BANKS 2 125 #define CONFIG_SYS_MAX_FLASH_SECT 1024 126 127 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 128 129 #define CONFIG_FLASH_CFI_DRIVER 130 #define CONFIG_SYS_FLASH_CFI 131 #define CONFIG_SYS_FLASH_EMPTY_INFO 132 133 #define CONFIG_BOARD_EARLY_INIT_F 134 #define CONFIG_BOARD_EARLY_INIT_R 135 #define CONFIG_MISC_INIT_R 136 137 #define CONFIG_FSL_NGPIXIS 138 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 139 #define PIXIS_BASE_PHYS 0xfffdf0000ull 140 141 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 142 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 143 144 #define PIXIS_LBMAP_SWITCH 7 145 #define PIXIS_LBMAP_MASK 0xE0 146 #define PIXIS_LBMAP_ALTBANK 0x20 147 148 #define CONFIG_SYS_INIT_RAM_LOCK 149 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 150 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 151 152 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 153 #define CONFIG_SYS_GBL_DATA_OFFSET \ 154 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 155 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 156 157 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 158 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) 159 160 /* 161 * Serial Port 162 */ 163 #define CONFIG_CONS_INDEX 1 164 #define CONFIG_SYS_NS16550 165 #define CONFIG_SYS_NS16550_SERIAL 166 #define CONFIG_SYS_NS16550_REG_SIZE 1 167 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 168 169 #define CONFIG_SYS_BAUDRATE_TABLE \ 170 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 171 172 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 173 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 174 175 /* Use the HUSH parser */ 176 #define CONFIG_SYS_HUSH_PARSER 177 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 178 179 #define CONFIG_FSL_DIU_FB 180 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 181 182 /* Video */ 183 /* #define CONFIG_VIDEO */ 184 #ifdef CONFIG_VIDEO 185 #define CONFIG_CFB_CONSOLE 186 #define CONFIG_VGA_AS_SINGLE_DEVICE 187 #endif 188 189 /* 190 * Pass open firmware flat tree 191 */ 192 #define CONFIG_OF_LIBFDT 193 #define CONFIG_OF_BOARD_SETUP 194 #define CONFIG_OF_STDOUT_VIA_ALIAS 195 196 /* new uImage format support */ 197 #define CONFIG_FIT 198 #define CONFIG_FIT_VERBOSE 199 200 /* I2C */ 201 #define CONFIG_FSL_I2C 202 #define CONFIG_HARD_I2C 203 #define CONFIG_I2C_MULTI_BUS 204 #define CONFIG_SYS_I2C_SPEED 400000 205 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 206 #define CONFIG_SYS_I2C_SLAVE 0x7F 207 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 208 #define CONFIG_SYS_I2C_OFFSET 0x3000 209 #define CONFIG_SYS_I2C2_OFFSET 0x3100 210 211 /* 212 * I2C2 EEPROM 213 */ 214 #define CONFIG_ID_EEPROM 215 #define CONFIG_SYS_I2C_EEPROM_NXID 216 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 218 #define CONFIG_SYS_EEPROM_BUS_NUM 1 219 220 /* 221 * General PCI 222 * Memory space is mapped 1-1, but I/O space must start from 0. 223 */ 224 225 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 226 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 227 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 228 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 229 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 230 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 231 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 232 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 233 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 234 235 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 236 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 237 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 238 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 239 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 240 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 241 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 242 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 243 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 244 245 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 246 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 247 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 248 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 249 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 250 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 251 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 252 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 253 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 254 255 #ifdef CONFIG_PCI 256 #define CONFIG_NET_MULTI 257 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 258 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 259 #endif 260 261 /* SATA */ 262 #define CONFIG_LIBATA 263 #define CONFIG_FSL_SATA 264 265 #define CONFIG_SYS_SATA_MAX_DEVICE 2 266 #define CONFIG_SATA1 267 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 268 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 269 #define CONFIG_SATA2 270 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 271 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 272 273 #ifdef CONFIG_FSL_SATA 274 #define CONFIG_LBA48 275 #define CONFIG_CMD_SATA 276 #define CONFIG_DOS_PARTITION 277 #define CONFIG_CMD_EXT2 278 #endif 279 280 #define CONFIG_MMC 281 #ifdef CONFIG_MMC 282 #define CONFIG_CMD_MMC 283 #define CONFIG_FSL_ESDHC 284 #define CONFIG_GENERIC_MMC 285 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 286 #endif 287 288 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 289 #define CONFIG_CMD_EXT2 290 #define CONFIG_CMD_FAT 291 #define CONFIG_DOS_PARTITION 292 #endif 293 294 #define CONFIG_TSEC_ENET 295 #ifdef CONFIG_TSEC_ENET 296 297 #define CONFIG_TSECV2 298 #define CONFIG_NET_MULTI 299 300 #define CONFIG_MII /* MII PHY management */ 301 #define CONFIG_TSEC1 1 302 #define CONFIG_TSEC1_NAME "eTSEC1" 303 #define CONFIG_TSEC2 1 304 #define CONFIG_TSEC2_NAME "eTSEC2" 305 306 #define TSEC1_PHY_ADDR 1 307 #define TSEC2_PHY_ADDR 2 308 309 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 310 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 311 312 #define TSEC1_PHYIDX 0 313 #define TSEC2_PHYIDX 0 314 315 #define CONFIG_ETHPRIME "eTSEC1" 316 317 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 318 #endif 319 320 /* 321 * Environment 322 */ 323 #define CONFIG_ENV_IS_IN_FLASH 324 #define CONFIG_ENV_OVERWRITE 325 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 326 #define CONFIG_ENV_SIZE 0x2000 327 #define CONFIG_ENV_SECT_SIZE 0x20000 328 329 #define CONFIG_LOADS_ECHO 330 #define CONFIG_SYS_LOADS_BAUD_CHANGE 331 332 /* 333 * Command line configuration. 334 */ 335 #include <config_cmd_default.h> 336 337 #define CONFIG_CMD_ELF 338 #define CONFIG_CMD_ERRATA 339 #define CONFIG_CMD_IRQ 340 #define CONFIG_CMD_I2C 341 #define CONFIG_CMD_MII 342 #define CONFIG_CMD_PING 343 #define CONFIG_CMD_SETEXPR 344 345 #ifdef CONFIG_PCI 346 #define CONFIG_CMD_PCI 347 #define CONFIG_CMD_NET 348 #endif 349 350 /* 351 * USB 352 */ 353 #define CONFIG_USB_EHCI 354 355 #ifdef CONFIG_USB_EHCI 356 #define CONFIG_CMD_USB 357 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 358 #define CONFIG_USB_EHCI_FSL 359 #define CONFIG_USB_STORAGE 360 #define CONFIG_CMD_FAT 361 #endif 362 363 /* 364 * Miscellaneous configurable options 365 */ 366 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 367 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 368 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 369 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 370 #ifdef CONFIG_CMD_KGDB 371 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 372 #else 373 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 374 #endif 375 /* Print Buffer Size */ 376 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 377 #define CONFIG_SYS_MAXARGS 16 378 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 379 #define CONFIG_SYS_HZ 1000 380 381 /* 382 * For booting Linux, the board info and command line data 383 * have to be in the first 16 MB of memory, since this is 384 * the maximum mapped by the Linux kernel during initialization. 385 */ 386 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 387 388 /* 389 * Internal Definitions 390 * 391 * Boot Flags 392 */ 393 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 394 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 395 396 #ifdef CONFIG_CMD_KGDB 397 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 398 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 399 #endif 400 401 /* 402 * Environment Configuration 403 */ 404 405 #define CONFIG_HOSTNAME p1022ds 406 #define CONFIG_ROOTPATH /opt/nfsroot 407 #define CONFIG_BOOTFILE uImage 408 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 409 410 #define CONFIG_LOADADDR 1000000 411 412 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 413 #define CONFIG_BOOTARGS 414 415 #define CONFIG_BAUDRATE 115200 416 417 #define CONFIG_EXTRA_ENV_SETTINGS \ 418 "perf_mode=stable\0" \ 419 "memctl_intlv_ctl=2\0" \ 420 "netdev=eth0\0" \ 421 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 422 "tftpflash=tftpboot $loadaddr $uboot; " \ 423 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 424 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 425 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 426 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 427 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 428 "consoledev=ttyS0\0" \ 429 "ramdiskaddr=2000000\0" \ 430 "ramdiskfile=uramdisk\0" \ 431 "fdtaddr=c00000\0" \ 432 "fdtfile=p1022ds.dtb\0" \ 433 "bdev=sda3\0" \ 434 "diuregs=md e002c000 1d\0" \ 435 "dium=mw e002c01c\0" \ 436 "diuerr=md e002c014 1\0" \ 437 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \ 438 "monitor=0-DVI\0" 439 440 #define CONFIG_HDBOOT \ 441 "setenv bootargs root=/dev/$bdev rw " \ 442 "console=$consoledev,$baudrate $othbootargs;" \ 443 "tftp $loadaddr $bootfile;" \ 444 "tftp $fdtaddr $fdtfile;" \ 445 "bootm $loadaddr - $fdtaddr" 446 447 #define CONFIG_NFSBOOTCOMMAND \ 448 "setenv bootargs root=/dev/nfs rw " \ 449 "nfsroot=$serverip:$rootpath " \ 450 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 451 "console=$consoledev,$baudrate $othbootargs;" \ 452 "tftp $loadaddr $bootfile;" \ 453 "tftp $fdtaddr $fdtfile;" \ 454 "bootm $loadaddr - $fdtaddr" 455 456 #define CONFIG_RAMBOOTCOMMAND \ 457 "setenv bootargs root=/dev/ram rw " \ 458 "console=$consoledev,$baudrate $othbootargs;" \ 459 "tftp $ramdiskaddr $ramdiskfile;" \ 460 "tftp $loadaddr $bootfile;" \ 461 "tftp $fdtaddr $fdtfile;" \ 462 "bootm $loadaddr $ramdiskaddr $fdtaddr" 463 464 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 465 466 #endif 467