1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 18 #define CONFIG_SPL_SERIAL_SUPPORT 19 #define CONFIG_SPL_MMC_SUPPORT 20 #define CONFIG_SPL_MMC_MINIMAL 21 #define CONFIG_SPL_FLUSH_IMAGE 22 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 23 #define CONFIG_SPL_LIBGENERIC_SUPPORT 24 #define CONFIG_SPL_LIBCOMMON_SUPPORT 25 #define CONFIG_FSL_LAW /* Use common FSL init code */ 26 #define CONFIG_SYS_TEXT_BASE 0x11001000 27 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 28 #define CONFIG_SPL_PAD_TO 0x20000 29 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 30 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 31 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 32 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 33 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 34 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 35 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 36 #define CONFIG_SPL_MMC_BOOT 37 #ifdef CONFIG_SPL_BUILD 38 #define CONFIG_SPL_COMMON_INIT_DDR 39 #endif 40 #endif 41 42 #ifdef CONFIG_SPIFLASH 43 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 44 #define CONFIG_SPL_SERIAL_SUPPORT 45 #define CONFIG_SPL_SPI_SUPPORT 46 #define CONFIG_SPL_SPI_FLASH_SUPPORT 47 #define CONFIG_SPL_SPI_FLASH_MINIMAL 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_SPL_LIBGENERIC_SUPPORT 51 #define CONFIG_SPL_LIBCOMMON_SUPPORT 52 #define CONFIG_FSL_LAW /* Use common FSL init code */ 53 #define CONFIG_SYS_TEXT_BASE 0x11001000 54 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 55 #define CONFIG_SPL_PAD_TO 0x20000 56 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 63 #define CONFIG_SPL_SPI_BOOT 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SPL_COMMON_INIT_DDR 66 #endif 67 #endif 68 69 #define CONFIG_NAND_FSL_ELBC 70 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 71 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 72 73 #ifdef CONFIG_NAND 74 #ifdef CONFIG_TPL_BUILD 75 #define CONFIG_SPL_NAND_BOOT 76 #define CONFIG_SPL_FLUSH_IMAGE 77 #define CONFIG_SPL_NAND_INIT 78 #define CONFIG_TPL_SERIAL_SUPPORT 79 #define CONFIG_TPL_LIBGENERIC_SUPPORT 80 #define CONFIG_TPL_LIBCOMMON_SUPPORT 81 #define CONFIG_TPL_NAND_SUPPORT 82 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 83 #define CONFIG_SPL_COMMON_INIT_DDR 84 #define CONFIG_SPL_MAX_SIZE (128 << 10) 85 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 87 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 88 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 89 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 90 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 91 #elif defined(CONFIG_SPL_BUILD) 92 #define CONFIG_SPL_INIT_MINIMAL 93 #define CONFIG_SPL_SERIAL_SUPPORT 94 #define CONFIG_SPL_NAND_SUPPORT 95 #define CONFIG_SPL_FLUSH_IMAGE 96 #define CONFIG_SPL_TEXT_BASE 0xff800000 97 #define CONFIG_SPL_MAX_SIZE 4096 98 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 99 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 100 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 101 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 102 #endif 103 #define CONFIG_SPL_PAD_TO 0x20000 104 #define CONFIG_TPL_PAD_TO 0x20000 105 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 106 #define CONFIG_SYS_TEXT_BASE 0x11001000 107 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 108 #endif 109 110 /* High Level Configuration Options */ 111 #define CONFIG_BOOKE /* BOOKE */ 112 #define CONFIG_E500 /* BOOKE e500 family */ 113 #define CONFIG_P1022 114 #define CONFIG_P1022DS 115 #define CONFIG_MP /* support multiple processors */ 116 117 #ifndef CONFIG_SYS_TEXT_BASE 118 #define CONFIG_SYS_TEXT_BASE 0xeff40000 119 #endif 120 121 #ifndef CONFIG_RESET_VECTOR_ADDRESS 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 123 #endif 124 125 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 126 #define CONFIG_PCI /* Enable PCI/PCIE */ 127 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 128 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 129 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 130 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 131 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 132 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 133 134 #define CONFIG_ENABLE_36BIT_PHYS 135 136 #ifdef CONFIG_PHYS_64BIT 137 #define CONFIG_ADDR_MAP 138 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 139 #endif 140 141 #define CONFIG_FSL_LAW /* Use common FSL init code */ 142 143 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 144 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 145 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 146 147 /* 148 * These can be toggled for performance analysis, otherwise use default. 149 */ 150 #define CONFIG_L2_CACHE 151 #define CONFIG_BTB 152 153 #define CONFIG_SYS_MEMTEST_START 0x00000000 154 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 155 156 #define CONFIG_SYS_CCSRBAR 0xffe00000 157 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 158 159 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 160 SPL code*/ 161 #ifdef CONFIG_SPL_BUILD 162 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 163 #endif 164 165 /* DDR Setup */ 166 #define CONFIG_DDR_SPD 167 #define CONFIG_VERY_BIG_RAM 168 #define CONFIG_SYS_FSL_DDR3 169 170 #ifdef CONFIG_DDR_ECC 171 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 172 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 173 #endif 174 175 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 176 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 177 178 #define CONFIG_NUM_DDR_CONTROLLERS 1 179 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 180 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 181 182 /* I2C addresses of SPD EEPROMs */ 183 #define CONFIG_SYS_SPD_BUS_NUM 1 184 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 185 186 /* These are used when DDR doesn't use SPD. */ 187 #define CONFIG_SYS_SDRAM_SIZE 2048 188 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 189 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 190 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 191 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 192 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 193 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 194 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 195 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 196 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 197 #define CONFIG_SYS_DDR_MODE_1 0x00441221 198 #define CONFIG_SYS_DDR_MODE_2 0x00000000 199 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 200 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 201 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 202 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 203 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 204 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 205 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 206 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 207 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 208 209 /* 210 * Memory map 211 * 212 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 213 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 214 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 215 * 216 * Localbus cacheable (TBD) 217 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 218 * 219 * Localbus non-cacheable 220 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 221 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 222 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 223 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 224 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 225 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 226 */ 227 228 /* 229 * Local Bus Definitions 230 */ 231 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 232 #ifdef CONFIG_PHYS_64BIT 233 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 234 #else 235 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 236 #endif 237 238 #define CONFIG_FLASH_BR_PRELIM \ 239 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 240 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 241 242 #ifdef CONFIG_NAND 243 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 244 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 245 #else 246 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 247 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 248 #endif 249 250 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 251 #define CONFIG_SYS_FLASH_QUIET_TEST 252 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 253 254 #define CONFIG_SYS_MAX_FLASH_BANKS 1 255 #define CONFIG_SYS_MAX_FLASH_SECT 1024 256 257 #ifndef CONFIG_SYS_MONITOR_BASE 258 #ifdef CONFIG_SPL_BUILD 259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 260 #else 261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 262 #endif 263 #endif 264 265 #define CONFIG_FLASH_CFI_DRIVER 266 #define CONFIG_SYS_FLASH_CFI 267 #define CONFIG_SYS_FLASH_EMPTY_INFO 268 269 /* Nand Flash */ 270 #if defined(CONFIG_NAND_FSL_ELBC) 271 #define CONFIG_SYS_NAND_BASE 0xff800000 272 #ifdef CONFIG_PHYS_64BIT 273 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 274 #else 275 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 276 #endif 277 278 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 279 #define CONFIG_SYS_MAX_NAND_DEVICE 1 280 #define CONFIG_CMD_NAND 1 281 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 282 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 283 284 /* NAND flash config */ 285 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 286 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 287 | BR_PS_8 /* Port Size = 8 bit */ \ 288 | BR_MS_FCM /* MSEL = FCM */ \ 289 | BR_V) /* valid */ 290 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 291 | OR_FCM_PGS /* Large Page*/ \ 292 | OR_FCM_CSCT \ 293 | OR_FCM_CST \ 294 | OR_FCM_CHT \ 295 | OR_FCM_SCY_1 \ 296 | OR_FCM_TRLX \ 297 | OR_FCM_EHTR) 298 #ifdef CONFIG_NAND 299 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 300 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 301 #else 302 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 303 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 304 #endif 305 306 #endif /* CONFIG_NAND_FSL_ELBC */ 307 308 #define CONFIG_BOARD_EARLY_INIT_F 309 #define CONFIG_BOARD_EARLY_INIT_R 310 #define CONFIG_MISC_INIT_R 311 #define CONFIG_HWCONFIG 312 313 #define CONFIG_FSL_NGPIXIS 314 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 315 #ifdef CONFIG_PHYS_64BIT 316 #define PIXIS_BASE_PHYS 0xfffdf0000ull 317 #else 318 #define PIXIS_BASE_PHYS PIXIS_BASE 319 #endif 320 321 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 322 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 323 324 #define PIXIS_LBMAP_SWITCH 7 325 #define PIXIS_LBMAP_MASK 0xF0 326 #define PIXIS_LBMAP_ALTBANK 0x20 327 #define PIXIS_SPD 0x07 328 #define PIXIS_SPD_SYSCLK_MASK 0x07 329 #define PIXIS_ELBC_SPI_MASK 0xc0 330 #define PIXIS_SPI 0x80 331 332 #define CONFIG_SYS_INIT_RAM_LOCK 333 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 334 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 335 336 #define CONFIG_SYS_GBL_DATA_OFFSET \ 337 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 338 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 339 340 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 341 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 342 343 /* 344 * Config the L2 Cache as L2 SRAM 345 */ 346 #if defined(CONFIG_SPL_BUILD) 347 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 348 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 349 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 350 #define CONFIG_SYS_L2_SIZE (256 << 10) 351 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 352 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 353 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 354 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 355 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 356 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 357 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 358 #elif defined(CONFIG_NAND) 359 #ifdef CONFIG_TPL_BUILD 360 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 361 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 362 #define CONFIG_SYS_L2_SIZE (256 << 10) 363 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 364 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 365 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 366 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 367 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 368 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 369 #else 370 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 371 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 372 #define CONFIG_SYS_L2_SIZE (256 << 10) 373 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 374 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 375 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 376 #endif 377 #endif 378 #endif 379 380 /* 381 * Serial Port 382 */ 383 #define CONFIG_CONS_INDEX 1 384 #define CONFIG_SYS_NS16550_SERIAL 385 #define CONFIG_SYS_NS16550_REG_SIZE 1 386 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 387 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 388 #define CONFIG_NS16550_MIN_FUNCTIONS 389 #endif 390 391 #define CONFIG_SYS_BAUDRATE_TABLE \ 392 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 393 394 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 395 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 396 397 /* Video */ 398 399 #ifdef CONFIG_FSL_DIU_FB 400 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 401 #define CONFIG_VIDEO 402 #define CONFIG_CMD_BMP 403 #define CONFIG_CFB_CONSOLE 404 #define CONFIG_VIDEO_SW_CURSOR 405 #define CONFIG_VGA_AS_SINGLE_DEVICE 406 #define CONFIG_VIDEO_LOGO 407 #define CONFIG_VIDEO_BMP_LOGO 408 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 409 /* 410 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 411 * disable empty flash sector detection, which is I/O-intensive. 412 */ 413 #undef CONFIG_SYS_FLASH_EMPTY_INFO 414 #endif 415 416 #ifndef CONFIG_FSL_DIU_FB 417 #endif 418 419 #ifdef CONFIG_ATI 420 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 421 #define CONFIG_VIDEO 422 #define CONFIG_BIOSEMU 423 #define CONFIG_VIDEO_SW_CURSOR 424 #define CONFIG_ATI_RADEON_FB 425 #define CONFIG_VIDEO_LOGO 426 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 427 #define CONFIG_CFB_CONSOLE 428 #define CONFIG_VGA_AS_SINGLE_DEVICE 429 #endif 430 431 /* I2C */ 432 #define CONFIG_SYS_I2C 433 #define CONFIG_SYS_I2C_FSL 434 #define CONFIG_SYS_FSL_I2C_SPEED 400000 435 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 437 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 438 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 439 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 440 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 441 442 /* 443 * I2C2 EEPROM 444 */ 445 #define CONFIG_ID_EEPROM 446 #define CONFIG_SYS_I2C_EEPROM_NXID 447 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 448 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 449 #define CONFIG_SYS_EEPROM_BUS_NUM 1 450 451 /* 452 * eSPI - Enhanced SPI 453 */ 454 455 #define CONFIG_HARD_SPI 456 457 #define CONFIG_SF_DEFAULT_SPEED 10000000 458 #define CONFIG_SF_DEFAULT_MODE 0 459 460 /* 461 * General PCI 462 * Memory space is mapped 1-1, but I/O space must start from 0. 463 */ 464 465 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 466 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 469 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 470 #else 471 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 472 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 473 #endif 474 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 475 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 476 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 479 #else 480 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 481 #endif 482 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 483 484 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 485 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 486 #ifdef CONFIG_PHYS_64BIT 487 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 488 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 489 #else 490 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 491 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 492 #endif 493 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 494 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 495 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 496 #ifdef CONFIG_PHYS_64BIT 497 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 498 #else 499 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 500 #endif 501 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 502 503 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 504 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 505 #ifdef CONFIG_PHYS_64BIT 506 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 507 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 508 #else 509 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 510 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 511 #endif 512 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 513 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 514 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 515 #ifdef CONFIG_PHYS_64BIT 516 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 517 #else 518 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 519 #endif 520 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 521 522 #ifdef CONFIG_PCI 523 #define CONFIG_PCI_INDIRECT_BRIDGE 524 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 525 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 526 #endif 527 528 /* SATA */ 529 #define CONFIG_LIBATA 530 #define CONFIG_FSL_SATA 531 #define CONFIG_FSL_SATA_V2 532 533 #define CONFIG_SYS_SATA_MAX_DEVICE 2 534 #define CONFIG_SATA1 535 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 536 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 537 #define CONFIG_SATA2 538 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 539 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 540 541 #ifdef CONFIG_FSL_SATA 542 #define CONFIG_LBA48 543 #define CONFIG_CMD_SATA 544 #define CONFIG_DOS_PARTITION 545 #endif 546 547 #define CONFIG_MMC 548 #ifdef CONFIG_MMC 549 #define CONFIG_FSL_ESDHC 550 #define CONFIG_GENERIC_MMC 551 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 552 #endif 553 554 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 555 #define CONFIG_DOS_PARTITION 556 #endif 557 558 #define CONFIG_TSEC_ENET 559 #ifdef CONFIG_TSEC_ENET 560 561 #define CONFIG_TSECV2 562 563 #define CONFIG_MII /* MII PHY management */ 564 #define CONFIG_TSEC1 1 565 #define CONFIG_TSEC1_NAME "eTSEC1" 566 #define CONFIG_TSEC2 1 567 #define CONFIG_TSEC2_NAME "eTSEC2" 568 569 #define TSEC1_PHY_ADDR 1 570 #define TSEC2_PHY_ADDR 2 571 572 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 573 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 574 575 #define TSEC1_PHYIDX 0 576 #define TSEC2_PHYIDX 0 577 578 #define CONFIG_ETHPRIME "eTSEC1" 579 580 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 581 #endif 582 583 /* 584 * Dynamic MTD Partition support with mtdparts 585 */ 586 #define CONFIG_MTD_DEVICE 587 #define CONFIG_MTD_PARTITIONS 588 #define CONFIG_CMD_MTDPARTS 589 #define CONFIG_FLASH_CFI_MTD 590 #ifdef CONFIG_PHYS_64BIT 591 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 592 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 593 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 594 "512k(dtb),768k(u-boot)" 595 #else 596 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 597 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 598 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 599 "512k(dtb),768k(u-boot)" 600 #endif 601 602 /* 603 * Environment 604 */ 605 #ifdef CONFIG_SPIFLASH 606 #define CONFIG_ENV_IS_IN_SPI_FLASH 607 #define CONFIG_ENV_SPI_BUS 0 608 #define CONFIG_ENV_SPI_CS 0 609 #define CONFIG_ENV_SPI_MAX_HZ 10000000 610 #define CONFIG_ENV_SPI_MODE 0 611 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 612 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 613 #define CONFIG_ENV_SECT_SIZE 0x10000 614 #elif defined(CONFIG_SDCARD) 615 #define CONFIG_ENV_IS_IN_MMC 616 #define CONFIG_FSL_FIXED_MMC_LOCATION 617 #define CONFIG_ENV_SIZE 0x2000 618 #define CONFIG_SYS_MMC_ENV_DEV 0 619 #elif defined(CONFIG_NAND) 620 #ifdef CONFIG_TPL_BUILD 621 #define CONFIG_ENV_SIZE 0x2000 622 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 623 #else 624 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 625 #endif 626 #define CONFIG_ENV_IS_IN_NAND 627 #define CONFIG_ENV_OFFSET (1024 * 1024) 628 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 629 #elif defined(CONFIG_SYS_RAMBOOT) 630 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 631 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 632 #define CONFIG_ENV_SIZE 0x2000 633 #else 634 #define CONFIG_ENV_IS_IN_FLASH 635 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 636 #define CONFIG_ENV_SIZE 0x2000 637 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 638 #endif 639 640 #define CONFIG_LOADS_ECHO 641 #define CONFIG_SYS_LOADS_BAUD_CHANGE 642 643 /* 644 * Command line configuration. 645 */ 646 #define CONFIG_CMD_ERRATA 647 #define CONFIG_CMD_IRQ 648 #define CONFIG_CMD_REGINFO 649 650 #ifdef CONFIG_PCI 651 #define CONFIG_CMD_PCI 652 #endif 653 654 /* 655 * USB 656 */ 657 #define CONFIG_HAS_FSL_DR_USB 658 #ifdef CONFIG_HAS_FSL_DR_USB 659 #define CONFIG_USB_EHCI 660 661 #ifdef CONFIG_USB_EHCI 662 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 663 #define CONFIG_USB_EHCI_FSL 664 #endif 665 #endif 666 667 /* 668 * Miscellaneous configurable options 669 */ 670 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 671 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 672 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 673 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 674 #ifdef CONFIG_CMD_KGDB 675 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 676 #else 677 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 678 #endif 679 /* Print Buffer Size */ 680 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 681 #define CONFIG_SYS_MAXARGS 16 682 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 683 684 /* 685 * For booting Linux, the board info and command line data 686 * have to be in the first 64 MB of memory, since this is 687 * the maximum mapped by the Linux kernel during initialization. 688 */ 689 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 690 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 691 692 #ifdef CONFIG_CMD_KGDB 693 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 694 #endif 695 696 /* 697 * Environment Configuration 698 */ 699 700 #define CONFIG_HOSTNAME p1022ds 701 #define CONFIG_ROOTPATH "/opt/nfsroot" 702 #define CONFIG_BOOTFILE "uImage" 703 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 704 705 #define CONFIG_LOADADDR 1000000 706 707 708 #define CONFIG_BAUDRATE 115200 709 710 #define CONFIG_EXTRA_ENV_SETTINGS \ 711 "netdev=eth0\0" \ 712 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 713 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 714 "tftpflash=tftpboot $loadaddr $uboot && " \ 715 "protect off $ubootaddr +$filesize && " \ 716 "erase $ubootaddr +$filesize && " \ 717 "cp.b $loadaddr $ubootaddr $filesize && " \ 718 "protect on $ubootaddr +$filesize && " \ 719 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 720 "consoledev=ttyS0\0" \ 721 "ramdiskaddr=2000000\0" \ 722 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 723 "fdtaddr=1e00000\0" \ 724 "fdtfile=p1022ds.dtb\0" \ 725 "bdev=sda3\0" \ 726 "hwconfig=esdhc;audclk:12\0" 727 728 #define CONFIG_HDBOOT \ 729 "setenv bootargs root=/dev/$bdev rw " \ 730 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 731 "tftp $loadaddr $bootfile;" \ 732 "tftp $fdtaddr $fdtfile;" \ 733 "bootm $loadaddr - $fdtaddr" 734 735 #define CONFIG_NFSBOOTCOMMAND \ 736 "setenv bootargs root=/dev/nfs rw " \ 737 "nfsroot=$serverip:$rootpath " \ 738 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 739 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 740 "tftp $loadaddr $bootfile;" \ 741 "tftp $fdtaddr $fdtfile;" \ 742 "bootm $loadaddr - $fdtaddr" 743 744 #define CONFIG_RAMBOOTCOMMAND \ 745 "setenv bootargs root=/dev/ram rw " \ 746 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 747 "tftp $ramdiskaddr $ramdiskfile;" \ 748 "tftp $loadaddr $bootfile;" \ 749 "tftp $fdtaddr $fdtfile;" \ 750 "bootm $loadaddr $ramdiskaddr $fdtaddr" 751 752 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 753 754 #endif 755