1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_SPL_SERIAL_SUPPORT 18 #define CONFIG_SPL_MMC_MINIMAL 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 21 #define CONFIG_FSL_LAW /* Use common FSL init code */ 22 #define CONFIG_SYS_TEXT_BASE 0x11001000 23 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 24 #define CONFIG_SPL_PAD_TO 0x20000 25 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 26 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 27 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 28 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 29 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 30 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 31 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 32 #define CONFIG_SPL_MMC_BOOT 33 #ifdef CONFIG_SPL_BUILD 34 #define CONFIG_SPL_COMMON_INIT_DDR 35 #endif 36 #endif 37 38 #ifdef CONFIG_SPIFLASH 39 #define CONFIG_SPL_SERIAL_SUPPORT 40 #define CONFIG_SPL_SPI_SUPPORT 41 #define CONFIG_SPL_SPI_FLASH_SUPPORT 42 #define CONFIG_SPL_SPI_FLASH_MINIMAL 43 #define CONFIG_SPL_FLUSH_IMAGE 44 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_SYS_TEXT_BASE 0x11001000 47 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 48 #define CONFIG_SPL_PAD_TO 0x20000 49 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 56 #define CONFIG_SPL_SPI_BOOT 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #endif 60 #endif 61 62 #define CONFIG_NAND_FSL_ELBC 63 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 64 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 65 66 #ifdef CONFIG_NAND 67 #ifdef CONFIG_TPL_BUILD 68 #define CONFIG_SPL_NAND_BOOT 69 #define CONFIG_SPL_FLUSH_IMAGE 70 #define CONFIG_SPL_NAND_INIT 71 #define CONFIG_TPL_SERIAL_SUPPORT 72 #define CONFIG_TPL_NAND_SUPPORT 73 #define CONFIG_SPL_COMMON_INIT_DDR 74 #define CONFIG_SPL_MAX_SIZE (128 << 10) 75 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 76 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 77 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 78 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 79 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 80 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 81 #elif defined(CONFIG_SPL_BUILD) 82 #define CONFIG_SPL_INIT_MINIMAL 83 #define CONFIG_SPL_SERIAL_SUPPORT 84 #define CONFIG_SPL_NAND_SUPPORT 85 #define CONFIG_SPL_FLUSH_IMAGE 86 #define CONFIG_SPL_TEXT_BASE 0xff800000 87 #define CONFIG_SPL_MAX_SIZE 4096 88 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 89 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 90 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 91 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 92 #endif 93 #define CONFIG_SPL_PAD_TO 0x20000 94 #define CONFIG_TPL_PAD_TO 0x20000 95 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 96 #define CONFIG_SYS_TEXT_BASE 0x11001000 97 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 98 #endif 99 100 /* High Level Configuration Options */ 101 #define CONFIG_BOOKE /* BOOKE */ 102 #define CONFIG_E500 /* BOOKE e500 family */ 103 #define CONFIG_P1022 104 #define CONFIG_P1022DS 105 #define CONFIG_MP /* support multiple processors */ 106 107 #ifndef CONFIG_SYS_TEXT_BASE 108 #define CONFIG_SYS_TEXT_BASE 0xeff40000 109 #endif 110 111 #ifndef CONFIG_RESET_VECTOR_ADDRESS 112 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 113 #endif 114 115 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 116 #define CONFIG_PCI /* Enable PCI/PCIE */ 117 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 118 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 119 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 120 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 121 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 122 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 123 124 #define CONFIG_ENABLE_36BIT_PHYS 125 126 #ifdef CONFIG_PHYS_64BIT 127 #define CONFIG_ADDR_MAP 128 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 129 #endif 130 131 #define CONFIG_FSL_LAW /* Use common FSL init code */ 132 133 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 134 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 135 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 136 137 /* 138 * These can be toggled for performance analysis, otherwise use default. 139 */ 140 #define CONFIG_L2_CACHE 141 #define CONFIG_BTB 142 143 #define CONFIG_SYS_MEMTEST_START 0x00000000 144 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 145 146 #define CONFIG_SYS_CCSRBAR 0xffe00000 147 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 148 149 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 150 SPL code*/ 151 #ifdef CONFIG_SPL_BUILD 152 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 153 #endif 154 155 /* DDR Setup */ 156 #define CONFIG_DDR_SPD 157 #define CONFIG_VERY_BIG_RAM 158 #define CONFIG_SYS_FSL_DDR3 159 160 #ifdef CONFIG_DDR_ECC 161 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 162 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 163 #endif 164 165 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 166 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 167 168 #define CONFIG_NUM_DDR_CONTROLLERS 1 169 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 170 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 171 172 /* I2C addresses of SPD EEPROMs */ 173 #define CONFIG_SYS_SPD_BUS_NUM 1 174 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 175 176 /* These are used when DDR doesn't use SPD. */ 177 #define CONFIG_SYS_SDRAM_SIZE 2048 178 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 179 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 180 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 181 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 182 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 183 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 184 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 185 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 186 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 187 #define CONFIG_SYS_DDR_MODE_1 0x00441221 188 #define CONFIG_SYS_DDR_MODE_2 0x00000000 189 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 190 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 191 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 192 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 193 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 194 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 195 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 196 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 197 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 198 199 /* 200 * Memory map 201 * 202 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 203 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 204 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 205 * 206 * Localbus cacheable (TBD) 207 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 208 * 209 * Localbus non-cacheable 210 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 211 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 212 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 213 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 214 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 215 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 216 */ 217 218 /* 219 * Local Bus Definitions 220 */ 221 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 222 #ifdef CONFIG_PHYS_64BIT 223 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 224 #else 225 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 226 #endif 227 228 #define CONFIG_FLASH_BR_PRELIM \ 229 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 230 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 231 232 #ifdef CONFIG_NAND 233 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 234 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 235 #else 236 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 237 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 238 #endif 239 240 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 241 #define CONFIG_SYS_FLASH_QUIET_TEST 242 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 243 244 #define CONFIG_SYS_MAX_FLASH_BANKS 1 245 #define CONFIG_SYS_MAX_FLASH_SECT 1024 246 247 #ifndef CONFIG_SYS_MONITOR_BASE 248 #ifdef CONFIG_SPL_BUILD 249 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 250 #else 251 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 252 #endif 253 #endif 254 255 #define CONFIG_FLASH_CFI_DRIVER 256 #define CONFIG_SYS_FLASH_CFI 257 #define CONFIG_SYS_FLASH_EMPTY_INFO 258 259 /* Nand Flash */ 260 #if defined(CONFIG_NAND_FSL_ELBC) 261 #define CONFIG_SYS_NAND_BASE 0xff800000 262 #ifdef CONFIG_PHYS_64BIT 263 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 264 #else 265 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 266 #endif 267 268 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 269 #define CONFIG_SYS_MAX_NAND_DEVICE 1 270 #define CONFIG_CMD_NAND 1 271 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 272 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 273 274 /* NAND flash config */ 275 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 276 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 277 | BR_PS_8 /* Port Size = 8 bit */ \ 278 | BR_MS_FCM /* MSEL = FCM */ \ 279 | BR_V) /* valid */ 280 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 281 | OR_FCM_PGS /* Large Page*/ \ 282 | OR_FCM_CSCT \ 283 | OR_FCM_CST \ 284 | OR_FCM_CHT \ 285 | OR_FCM_SCY_1 \ 286 | OR_FCM_TRLX \ 287 | OR_FCM_EHTR) 288 #ifdef CONFIG_NAND 289 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 290 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 291 #else 292 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 293 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 294 #endif 295 296 #endif /* CONFIG_NAND_FSL_ELBC */ 297 298 #define CONFIG_BOARD_EARLY_INIT_F 299 #define CONFIG_BOARD_EARLY_INIT_R 300 #define CONFIG_MISC_INIT_R 301 #define CONFIG_HWCONFIG 302 303 #define CONFIG_FSL_NGPIXIS 304 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 305 #ifdef CONFIG_PHYS_64BIT 306 #define PIXIS_BASE_PHYS 0xfffdf0000ull 307 #else 308 #define PIXIS_BASE_PHYS PIXIS_BASE 309 #endif 310 311 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 312 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 313 314 #define PIXIS_LBMAP_SWITCH 7 315 #define PIXIS_LBMAP_MASK 0xF0 316 #define PIXIS_LBMAP_ALTBANK 0x20 317 #define PIXIS_SPD 0x07 318 #define PIXIS_SPD_SYSCLK_MASK 0x07 319 #define PIXIS_ELBC_SPI_MASK 0xc0 320 #define PIXIS_SPI 0x80 321 322 #define CONFIG_SYS_INIT_RAM_LOCK 323 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 324 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 325 326 #define CONFIG_SYS_GBL_DATA_OFFSET \ 327 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 328 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 329 330 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 331 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 332 333 /* 334 * Config the L2 Cache as L2 SRAM 335 */ 336 #if defined(CONFIG_SPL_BUILD) 337 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 338 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 339 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 340 #define CONFIG_SYS_L2_SIZE (256 << 10) 341 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 342 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 343 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 344 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 345 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 346 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 347 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 348 #elif defined(CONFIG_NAND) 349 #ifdef CONFIG_TPL_BUILD 350 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 351 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 352 #define CONFIG_SYS_L2_SIZE (256 << 10) 353 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 354 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 355 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 356 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 357 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 358 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 359 #else 360 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 361 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 362 #define CONFIG_SYS_L2_SIZE (256 << 10) 363 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 364 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 365 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 366 #endif 367 #endif 368 #endif 369 370 /* 371 * Serial Port 372 */ 373 #define CONFIG_CONS_INDEX 1 374 #define CONFIG_SYS_NS16550_SERIAL 375 #define CONFIG_SYS_NS16550_REG_SIZE 1 376 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 377 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 378 #define CONFIG_NS16550_MIN_FUNCTIONS 379 #endif 380 381 #define CONFIG_SYS_BAUDRATE_TABLE \ 382 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 383 384 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 385 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 386 387 /* Video */ 388 389 #ifdef CONFIG_FSL_DIU_FB 390 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 391 #define CONFIG_VIDEO 392 #define CONFIG_CMD_BMP 393 #define CONFIG_CFB_CONSOLE 394 #define CONFIG_VIDEO_SW_CURSOR 395 #define CONFIG_VGA_AS_SINGLE_DEVICE 396 #define CONFIG_VIDEO_LOGO 397 #define CONFIG_VIDEO_BMP_LOGO 398 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 399 /* 400 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 401 * disable empty flash sector detection, which is I/O-intensive. 402 */ 403 #undef CONFIG_SYS_FLASH_EMPTY_INFO 404 #endif 405 406 #ifndef CONFIG_FSL_DIU_FB 407 #endif 408 409 #ifdef CONFIG_ATI 410 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 411 #define CONFIG_VIDEO 412 #define CONFIG_BIOSEMU 413 #define CONFIG_VIDEO_SW_CURSOR 414 #define CONFIG_ATI_RADEON_FB 415 #define CONFIG_VIDEO_LOGO 416 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 417 #define CONFIG_CFB_CONSOLE 418 #define CONFIG_VGA_AS_SINGLE_DEVICE 419 #endif 420 421 /* I2C */ 422 #define CONFIG_SYS_I2C 423 #define CONFIG_SYS_I2C_FSL 424 #define CONFIG_SYS_FSL_I2C_SPEED 400000 425 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 426 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 427 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 428 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 429 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 430 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 431 432 /* 433 * I2C2 EEPROM 434 */ 435 #define CONFIG_ID_EEPROM 436 #define CONFIG_SYS_I2C_EEPROM_NXID 437 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 438 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 439 #define CONFIG_SYS_EEPROM_BUS_NUM 1 440 441 /* 442 * eSPI - Enhanced SPI 443 */ 444 445 #define CONFIG_HARD_SPI 446 447 #define CONFIG_SF_DEFAULT_SPEED 10000000 448 #define CONFIG_SF_DEFAULT_MODE 0 449 450 /* 451 * General PCI 452 * Memory space is mapped 1-1, but I/O space must start from 0. 453 */ 454 455 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 456 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 457 #ifdef CONFIG_PHYS_64BIT 458 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 459 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 460 #else 461 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 462 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 463 #endif 464 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 465 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 466 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 469 #else 470 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 471 #endif 472 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 473 474 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 475 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 478 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 479 #else 480 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 481 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 482 #endif 483 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 484 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 485 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 486 #ifdef CONFIG_PHYS_64BIT 487 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 488 #else 489 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 490 #endif 491 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 492 493 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 494 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 495 #ifdef CONFIG_PHYS_64BIT 496 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 497 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 498 #else 499 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 500 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 501 #endif 502 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 503 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 504 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 505 #ifdef CONFIG_PHYS_64BIT 506 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 507 #else 508 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 509 #endif 510 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 511 512 #ifdef CONFIG_PCI 513 #define CONFIG_PCI_INDIRECT_BRIDGE 514 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 515 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 516 #endif 517 518 /* SATA */ 519 #define CONFIG_LIBATA 520 #define CONFIG_FSL_SATA 521 #define CONFIG_FSL_SATA_V2 522 523 #define CONFIG_SYS_SATA_MAX_DEVICE 2 524 #define CONFIG_SATA1 525 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 526 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 527 #define CONFIG_SATA2 528 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 529 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 530 531 #ifdef CONFIG_FSL_SATA 532 #define CONFIG_LBA48 533 #define CONFIG_CMD_SATA 534 #define CONFIG_DOS_PARTITION 535 #endif 536 537 #define CONFIG_MMC 538 #ifdef CONFIG_MMC 539 #define CONFIG_FSL_ESDHC 540 #define CONFIG_GENERIC_MMC 541 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 542 #endif 543 544 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 545 #define CONFIG_DOS_PARTITION 546 #endif 547 548 #define CONFIG_TSEC_ENET 549 #ifdef CONFIG_TSEC_ENET 550 551 #define CONFIG_TSECV2 552 553 #define CONFIG_MII /* MII PHY management */ 554 #define CONFIG_TSEC1 1 555 #define CONFIG_TSEC1_NAME "eTSEC1" 556 #define CONFIG_TSEC2 1 557 #define CONFIG_TSEC2_NAME "eTSEC2" 558 559 #define TSEC1_PHY_ADDR 1 560 #define TSEC2_PHY_ADDR 2 561 562 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 563 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 564 565 #define TSEC1_PHYIDX 0 566 #define TSEC2_PHYIDX 0 567 568 #define CONFIG_ETHPRIME "eTSEC1" 569 570 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 571 #endif 572 573 /* 574 * Dynamic MTD Partition support with mtdparts 575 */ 576 #define CONFIG_MTD_DEVICE 577 #define CONFIG_MTD_PARTITIONS 578 #define CONFIG_CMD_MTDPARTS 579 #define CONFIG_FLASH_CFI_MTD 580 #ifdef CONFIG_PHYS_64BIT 581 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 582 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 583 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 584 "512k(dtb),768k(u-boot)" 585 #else 586 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 587 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 588 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 589 "512k(dtb),768k(u-boot)" 590 #endif 591 592 /* 593 * Environment 594 */ 595 #ifdef CONFIG_SPIFLASH 596 #define CONFIG_ENV_IS_IN_SPI_FLASH 597 #define CONFIG_ENV_SPI_BUS 0 598 #define CONFIG_ENV_SPI_CS 0 599 #define CONFIG_ENV_SPI_MAX_HZ 10000000 600 #define CONFIG_ENV_SPI_MODE 0 601 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 602 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 603 #define CONFIG_ENV_SECT_SIZE 0x10000 604 #elif defined(CONFIG_SDCARD) 605 #define CONFIG_ENV_IS_IN_MMC 606 #define CONFIG_FSL_FIXED_MMC_LOCATION 607 #define CONFIG_ENV_SIZE 0x2000 608 #define CONFIG_SYS_MMC_ENV_DEV 0 609 #elif defined(CONFIG_NAND) 610 #ifdef CONFIG_TPL_BUILD 611 #define CONFIG_ENV_SIZE 0x2000 612 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 613 #else 614 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 615 #endif 616 #define CONFIG_ENV_IS_IN_NAND 617 #define CONFIG_ENV_OFFSET (1024 * 1024) 618 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 619 #elif defined(CONFIG_SYS_RAMBOOT) 620 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 621 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 622 #define CONFIG_ENV_SIZE 0x2000 623 #else 624 #define CONFIG_ENV_IS_IN_FLASH 625 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 626 #define CONFIG_ENV_SIZE 0x2000 627 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 628 #endif 629 630 #define CONFIG_LOADS_ECHO 631 #define CONFIG_SYS_LOADS_BAUD_CHANGE 632 633 /* 634 * Command line configuration. 635 */ 636 #define CONFIG_CMD_ERRATA 637 #define CONFIG_CMD_IRQ 638 #define CONFIG_CMD_REGINFO 639 640 #ifdef CONFIG_PCI 641 #define CONFIG_CMD_PCI 642 #endif 643 644 /* 645 * USB 646 */ 647 #define CONFIG_HAS_FSL_DR_USB 648 #ifdef CONFIG_HAS_FSL_DR_USB 649 #define CONFIG_USB_EHCI 650 651 #ifdef CONFIG_USB_EHCI 652 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 653 #define CONFIG_USB_EHCI_FSL 654 #endif 655 #endif 656 657 /* 658 * Miscellaneous configurable options 659 */ 660 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 661 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 662 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 663 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 664 #ifdef CONFIG_CMD_KGDB 665 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 666 #else 667 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 668 #endif 669 /* Print Buffer Size */ 670 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 671 #define CONFIG_SYS_MAXARGS 16 672 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 673 674 /* 675 * For booting Linux, the board info and command line data 676 * have to be in the first 64 MB of memory, since this is 677 * the maximum mapped by the Linux kernel during initialization. 678 */ 679 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 680 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 681 682 #ifdef CONFIG_CMD_KGDB 683 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 684 #endif 685 686 /* 687 * Environment Configuration 688 */ 689 690 #define CONFIG_HOSTNAME p1022ds 691 #define CONFIG_ROOTPATH "/opt/nfsroot" 692 #define CONFIG_BOOTFILE "uImage" 693 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 694 695 #define CONFIG_LOADADDR 1000000 696 697 698 #define CONFIG_BAUDRATE 115200 699 700 #define CONFIG_EXTRA_ENV_SETTINGS \ 701 "netdev=eth0\0" \ 702 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 703 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 704 "tftpflash=tftpboot $loadaddr $uboot && " \ 705 "protect off $ubootaddr +$filesize && " \ 706 "erase $ubootaddr +$filesize && " \ 707 "cp.b $loadaddr $ubootaddr $filesize && " \ 708 "protect on $ubootaddr +$filesize && " \ 709 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 710 "consoledev=ttyS0\0" \ 711 "ramdiskaddr=2000000\0" \ 712 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 713 "fdtaddr=1e00000\0" \ 714 "fdtfile=p1022ds.dtb\0" \ 715 "bdev=sda3\0" \ 716 "hwconfig=esdhc;audclk:12\0" 717 718 #define CONFIG_HDBOOT \ 719 "setenv bootargs root=/dev/$bdev rw " \ 720 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 721 "tftp $loadaddr $bootfile;" \ 722 "tftp $fdtaddr $fdtfile;" \ 723 "bootm $loadaddr - $fdtaddr" 724 725 #define CONFIG_NFSBOOTCOMMAND \ 726 "setenv bootargs root=/dev/nfs rw " \ 727 "nfsroot=$serverip:$rootpath " \ 728 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 729 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 730 "tftp $loadaddr $bootfile;" \ 731 "tftp $fdtaddr $fdtfile;" \ 732 "bootm $loadaddr - $fdtaddr" 733 734 #define CONFIG_RAMBOOTCOMMAND \ 735 "setenv bootargs root=/dev/ram rw " \ 736 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 737 "tftp $ramdiskaddr $ramdiskfile;" \ 738 "tftp $loadaddr $bootfile;" \ 739 "tftp $fdtaddr $fdtfile;" \ 740 "bootm $loadaddr $ramdiskaddr $fdtaddr" 741 742 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 743 744 #endif 745