1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_36BIT 15 #define CONFIG_PHYS_64BIT 16 #endif 17 18 #ifdef CONFIG_SDCARD 19 #define CONFIG_SPL 20 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 21 #define CONFIG_SPL_ENV_SUPPORT 22 #define CONFIG_SPL_SERIAL_SUPPORT 23 #define CONFIG_SPL_MMC_SUPPORT 24 #define CONFIG_SPL_MMC_MINIMAL 25 #define CONFIG_SPL_FLUSH_IMAGE 26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 27 #define CONFIG_SPL_LIBGENERIC_SUPPORT 28 #define CONFIG_SPL_LIBCOMMON_SUPPORT 29 #define CONFIG_SPL_I2C_SUPPORT 30 #define CONFIG_FSL_LAW /* Use common FSL init code */ 31 #define CONFIG_SYS_TEXT_BASE 0x11001000 32 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 33 #define CONFIG_SPL_PAD_TO 0x18000 34 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 35 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 36 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 37 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 38 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 40 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 41 #define CONFIG_SPL_MMC_BOOT 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SPL_COMMON_INIT_DDR 44 #endif 45 #endif 46 47 #ifdef CONFIG_SPIFLASH 48 #define CONFIG_RAMBOOT_SPIFLASH 49 #define CONFIG_SYS_RAMBOOT 50 #define CONFIG_SYS_EXTRA_ENV_RELOC 51 #define CONFIG_SYS_TEXT_BASE 0x11000000 52 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 53 #endif 54 55 #define CONFIG_NAND_FSL_ELBC 56 57 #ifdef CONFIG_NAND 58 #define CONFIG_SPL 59 #define CONFIG_SPL_INIT_MINIMAL 60 #define CONFIG_SPL_SERIAL_SUPPORT 61 #define CONFIG_SPL_NAND_SUPPORT 62 #define CONFIG_SPL_FLUSH_IMAGE 63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 64 65 #define CONFIG_SYS_TEXT_BASE 0x00201000 66 #define CONFIG_SPL_TEXT_BASE 0xfffff000 67 #define CONFIG_SPL_MAX_SIZE 4096 68 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 69 #define CONFIG_SPL_RELOC_STACK 0x00100000 70 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE) 71 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 72 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 73 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 75 #endif 76 77 /* High Level Configuration Options */ 78 #define CONFIG_BOOKE /* BOOKE */ 79 #define CONFIG_E500 /* BOOKE e500 family */ 80 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ 81 #define CONFIG_P1022 82 #define CONFIG_P1022DS 83 #define CONFIG_MP /* support multiple processors */ 84 85 #ifndef CONFIG_SYS_TEXT_BASE 86 #define CONFIG_SYS_TEXT_BASE 0xeff80000 87 #endif 88 89 #ifndef CONFIG_RESET_VECTOR_ADDRESS 90 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 91 #endif 92 93 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 94 #define CONFIG_PCI /* Enable PCI/PCIE */ 95 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 96 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 97 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 98 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 99 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 100 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 101 102 #define CONFIG_ENABLE_36BIT_PHYS 103 104 #ifdef CONFIG_PHYS_64BIT 105 #define CONFIG_ADDR_MAP 106 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 107 #endif 108 109 #define CONFIG_FSL_LAW /* Use common FSL init code */ 110 111 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 112 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 113 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 114 115 /* 116 * These can be toggled for performance analysis, otherwise use default. 117 */ 118 #define CONFIG_L2_CACHE 119 #define CONFIG_BTB 120 121 #define CONFIG_SYS_MEMTEST_START 0x00000000 122 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 123 124 #define CONFIG_SYS_CCSRBAR 0xffe00000 125 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 126 127 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 128 SPL code*/ 129 #ifdef CONFIG_SPL_BUILD 130 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 131 #endif 132 133 134 /* DDR Setup */ 135 #define CONFIG_DDR_SPD 136 #define CONFIG_VERY_BIG_RAM 137 #define CONFIG_FSL_DDR3 138 139 #ifdef CONFIG_DDR_ECC 140 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 141 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 142 #endif 143 144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 147 #define CONFIG_NUM_DDR_CONTROLLERS 1 148 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 149 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 150 151 /* I2C addresses of SPD EEPROMs */ 152 #define CONFIG_SYS_SPD_BUS_NUM 1 153 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 154 155 /* These are used when DDR doesn't use SPD. */ 156 #define CONFIG_SYS_SDRAM_SIZE 2048 157 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 158 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 159 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 160 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 161 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 162 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 163 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 164 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 165 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 166 #define CONFIG_SYS_DDR_MODE_1 0x00441221 167 #define CONFIG_SYS_DDR_MODE_2 0x00000000 168 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 169 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 170 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 171 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 172 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 173 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 174 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 175 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 176 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 177 178 179 /* 180 * Memory map 181 * 182 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 183 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 184 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 185 * 186 * Localbus cacheable (TBD) 187 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 188 * 189 * Localbus non-cacheable 190 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 191 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 192 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 193 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 194 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 195 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 196 */ 197 198 /* 199 * Local Bus Definitions 200 */ 201 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 202 #ifdef CONFIG_PHYS_64BIT 203 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 204 #else 205 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 206 #endif 207 208 #define CONFIG_FLASH_BR_PRELIM \ 209 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 210 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 211 212 #ifdef CONFIG_NAND 213 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 214 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 215 #else 216 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 217 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 218 #endif 219 220 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 221 #define CONFIG_SYS_FLASH_QUIET_TEST 222 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 223 224 #define CONFIG_SYS_MAX_FLASH_BANKS 1 225 #define CONFIG_SYS_MAX_FLASH_SECT 1024 226 227 #ifndef CONFIG_SYS_MONITOR_BASE 228 #ifdef CONFIG_SPL_BUILD 229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 230 #else 231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 232 #endif 233 #endif 234 235 #define CONFIG_FLASH_CFI_DRIVER 236 #define CONFIG_SYS_FLASH_CFI 237 #define CONFIG_SYS_FLASH_EMPTY_INFO 238 239 /* Nand Flash */ 240 #if defined(CONFIG_NAND_FSL_ELBC) 241 #define CONFIG_SYS_NAND_BASE 0xff800000 242 #ifdef CONFIG_PHYS_64BIT 243 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 244 #else 245 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 246 #endif 247 248 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 249 #define CONFIG_SYS_MAX_NAND_DEVICE 1 250 #define CONFIG_MTD_NAND_VERIFY_WRITE 251 #define CONFIG_CMD_NAND 1 252 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 253 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 254 255 /* NAND flash config */ 256 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 257 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 258 | BR_PS_8 /* Port Size = 8 bit */ \ 259 | BR_MS_FCM /* MSEL = FCM */ \ 260 | BR_V) /* valid */ 261 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 262 | OR_FCM_PGS /* Large Page*/ \ 263 | OR_FCM_CSCT \ 264 | OR_FCM_CST \ 265 | OR_FCM_CHT \ 266 | OR_FCM_SCY_1 \ 267 | OR_FCM_TRLX \ 268 | OR_FCM_EHTR) 269 #ifdef CONFIG_NAND 270 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 271 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 272 #else 273 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 274 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 275 #endif 276 277 #endif /* CONFIG_NAND_FSL_ELBC */ 278 279 #define CONFIG_BOARD_EARLY_INIT_F 280 #define CONFIG_BOARD_EARLY_INIT_R 281 #define CONFIG_MISC_INIT_R 282 #define CONFIG_HWCONFIG 283 284 #define CONFIG_FSL_NGPIXIS 285 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 286 #ifdef CONFIG_PHYS_64BIT 287 #define PIXIS_BASE_PHYS 0xfffdf0000ull 288 #else 289 #define PIXIS_BASE_PHYS PIXIS_BASE 290 #endif 291 292 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 293 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 294 295 #define PIXIS_LBMAP_SWITCH 7 296 #define PIXIS_LBMAP_MASK 0xF0 297 #define PIXIS_LBMAP_ALTBANK 0x20 298 #define PIXIS_SPD 0x07 299 #define PIXIS_SPD_SYSCLK_MASK 0x07 300 #define PIXIS_ELBC_SPI_MASK 0xc0 301 #define PIXIS_SPI 0x80 302 303 #define CONFIG_SYS_INIT_RAM_LOCK 304 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 305 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 306 307 #define CONFIG_SYS_GBL_DATA_OFFSET \ 308 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 309 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 310 311 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 312 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 313 314 /* 315 * Config the L2 Cache as L2 SRAM 316 */ 317 #if defined(CONFIG_SPL_BUILD) 318 #if defined(CONFIG_SDCARD) 319 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 320 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 321 #define CONFIG_SYS_L2_SIZE (256 << 10) 322 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 323 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 324 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 325 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 326 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 327 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 328 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 329 #endif 330 #endif 331 332 /* 333 * Serial Port 334 */ 335 #define CONFIG_CONS_INDEX 1 336 #define CONFIG_SYS_NS16550 337 #define CONFIG_SYS_NS16550_SERIAL 338 #define CONFIG_SYS_NS16550_REG_SIZE 1 339 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 340 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 341 #define CONFIG_NS16550_MIN_FUNCTIONS 342 #endif 343 344 #define CONFIG_SYS_BAUDRATE_TABLE \ 345 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 346 347 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 348 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 349 350 /* Use the HUSH parser */ 351 #define CONFIG_SYS_HUSH_PARSER 352 353 /* Video */ 354 355 #ifdef CONFIG_FSL_DIU_FB 356 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 357 #define CONFIG_VIDEO 358 #define CONFIG_CMD_BMP 359 #define CONFIG_CFB_CONSOLE 360 #define CONFIG_VIDEO_SW_CURSOR 361 #define CONFIG_VGA_AS_SINGLE_DEVICE 362 #define CONFIG_VIDEO_LOGO 363 #define CONFIG_VIDEO_BMP_LOGO 364 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 365 /* 366 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 367 * disable empty flash sector detection, which is I/O-intensive. 368 */ 369 #undef CONFIG_SYS_FLASH_EMPTY_INFO 370 #endif 371 372 #ifndef CONFIG_FSL_DIU_FB 373 #endif 374 375 #ifdef CONFIG_ATI 376 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 377 #define CONFIG_VIDEO 378 #define CONFIG_BIOSEMU 379 #define CONFIG_VIDEO_SW_CURSOR 380 #define CONFIG_ATI_RADEON_FB 381 #define CONFIG_VIDEO_LOGO 382 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 383 #define CONFIG_CFB_CONSOLE 384 #define CONFIG_VGA_AS_SINGLE_DEVICE 385 #endif 386 387 /* 388 * Pass open firmware flat tree 389 */ 390 #define CONFIG_OF_LIBFDT 391 #define CONFIG_OF_BOARD_SETUP 392 #define CONFIG_OF_STDOUT_VIA_ALIAS 393 394 /* new uImage format support */ 395 #define CONFIG_FIT 396 #define CONFIG_FIT_VERBOSE 397 398 /* I2C */ 399 #define CONFIG_SYS_I2C 400 #define CONFIG_SYS_I2C_FSL 401 #define CONFIG_SYS_FSL_I2C_SPEED 400000 402 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 403 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 404 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 405 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 406 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 407 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 408 409 /* 410 * I2C2 EEPROM 411 */ 412 #define CONFIG_ID_EEPROM 413 #define CONFIG_SYS_I2C_EEPROM_NXID 414 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 415 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 416 #define CONFIG_SYS_EEPROM_BUS_NUM 1 417 418 /* 419 * eSPI - Enhanced SPI 420 */ 421 #define CONFIG_SPI_FLASH 422 #define CONFIG_SPI_FLASH_SPANSION 423 424 #define CONFIG_HARD_SPI 425 #define CONFIG_FSL_ESPI 426 427 #define CONFIG_CMD_SF 428 #define CONFIG_SF_DEFAULT_SPEED 10000000 429 #define CONFIG_SF_DEFAULT_MODE 0 430 431 /* 432 * General PCI 433 * Memory space is mapped 1-1, but I/O space must start from 0. 434 */ 435 436 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 437 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 438 #ifdef CONFIG_PHYS_64BIT 439 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 440 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 441 #else 442 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 443 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 444 #endif 445 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 446 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 447 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 450 #else 451 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 452 #endif 453 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 454 455 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 456 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 457 #ifdef CONFIG_PHYS_64BIT 458 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 459 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 460 #else 461 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 462 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 463 #endif 464 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 465 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 466 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 469 #else 470 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 471 #endif 472 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 473 474 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 475 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 478 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 479 #else 480 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 481 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 482 #endif 483 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 484 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 485 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 486 #ifdef CONFIG_PHYS_64BIT 487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 488 #else 489 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 490 #endif 491 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 492 493 #ifdef CONFIG_PCI 494 #define CONFIG_PCI_INDIRECT_BRIDGE 495 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 496 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 497 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 498 #endif 499 500 /* SATA */ 501 #define CONFIG_LIBATA 502 #define CONFIG_FSL_SATA 503 #define CONFIG_FSL_SATA_V2 504 505 #define CONFIG_SYS_SATA_MAX_DEVICE 2 506 #define CONFIG_SATA1 507 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 508 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 509 #define CONFIG_SATA2 510 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 511 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 512 513 #ifdef CONFIG_FSL_SATA 514 #define CONFIG_LBA48 515 #define CONFIG_CMD_SATA 516 #define CONFIG_DOS_PARTITION 517 #define CONFIG_CMD_EXT2 518 #endif 519 520 #define CONFIG_MMC 521 #ifdef CONFIG_MMC 522 #define CONFIG_CMD_MMC 523 #define CONFIG_FSL_ESDHC 524 #define CONFIG_GENERIC_MMC 525 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 526 #endif 527 528 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 529 #define CONFIG_CMD_EXT2 530 #define CONFIG_CMD_FAT 531 #define CONFIG_DOS_PARTITION 532 #endif 533 534 #define CONFIG_TSEC_ENET 535 #ifdef CONFIG_TSEC_ENET 536 537 #define CONFIG_TSECV2 538 539 #define CONFIG_MII /* MII PHY management */ 540 #define CONFIG_TSEC1 1 541 #define CONFIG_TSEC1_NAME "eTSEC1" 542 #define CONFIG_TSEC2 1 543 #define CONFIG_TSEC2_NAME "eTSEC2" 544 545 #define TSEC1_PHY_ADDR 1 546 #define TSEC2_PHY_ADDR 2 547 548 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 549 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 550 551 #define TSEC1_PHYIDX 0 552 #define TSEC2_PHYIDX 0 553 554 #define CONFIG_ETHPRIME "eTSEC1" 555 556 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 557 #endif 558 559 /* 560 * Environment 561 */ 562 #ifdef CONFIG_RAMBOOT_SPIFLASH 563 #define CONFIG_ENV_IS_IN_SPI_FLASH 564 #define CONFIG_ENV_SPI_BUS 0 565 #define CONFIG_ENV_SPI_CS 0 566 #define CONFIG_ENV_SPI_MAX_HZ 10000000 567 #define CONFIG_ENV_SPI_MODE 0 568 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 569 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 570 #define CONFIG_ENV_SECT_SIZE 0x10000 571 #elif defined(CONFIG_SDCARD) 572 #define CONFIG_ENV_IS_IN_MMC 573 #define CONFIG_FSL_FIXED_MMC_LOCATION 574 #define CONFIG_ENV_SIZE 0x2000 575 #define CONFIG_SYS_MMC_ENV_DEV 0 576 #elif defined(CONFIG_NAND) 577 #define CONFIG_ENV_IS_IN_NAND 578 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 579 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 580 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 581 #elif defined(CONFIG_SYS_RAMBOOT) 582 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 583 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 584 #define CONFIG_ENV_SIZE 0x2000 585 #else 586 #define CONFIG_ENV_IS_IN_FLASH 587 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 588 #define CONFIG_ENV_ADDR 0xfff80000 589 #else 590 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 591 #endif 592 #define CONFIG_ENV_SIZE 0x2000 593 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 594 #endif 595 596 #define CONFIG_LOADS_ECHO 597 #define CONFIG_SYS_LOADS_BAUD_CHANGE 598 599 /* 600 * Command line configuration. 601 */ 602 #include <config_cmd_default.h> 603 604 #define CONFIG_CMD_ELF 605 #define CONFIG_CMD_ERRATA 606 #define CONFIG_CMD_IRQ 607 #define CONFIG_CMD_I2C 608 #define CONFIG_CMD_MII 609 #define CONFIG_CMD_PING 610 #define CONFIG_CMD_SETEXPR 611 #define CONFIG_CMD_REGINFO 612 613 #ifdef CONFIG_PCI 614 #define CONFIG_CMD_PCI 615 #define CONFIG_CMD_NET 616 #endif 617 618 /* 619 * USB 620 */ 621 #define CONFIG_HAS_FSL_DR_USB 622 #ifdef CONFIG_HAS_FSL_DR_USB 623 #define CONFIG_USB_EHCI 624 625 #ifdef CONFIG_USB_EHCI 626 #define CONFIG_CMD_USB 627 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 628 #define CONFIG_USB_EHCI_FSL 629 #define CONFIG_USB_STORAGE 630 #define CONFIG_CMD_FAT 631 #endif 632 #endif 633 634 /* 635 * Miscellaneous configurable options 636 */ 637 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 638 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 639 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 640 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 641 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 642 #ifdef CONFIG_CMD_KGDB 643 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 644 #else 645 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 646 #endif 647 /* Print Buffer Size */ 648 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 649 #define CONFIG_SYS_MAXARGS 16 650 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 651 #define CONFIG_SYS_HZ 1000 652 653 /* 654 * For booting Linux, the board info and command line data 655 * have to be in the first 64 MB of memory, since this is 656 * the maximum mapped by the Linux kernel during initialization. 657 */ 658 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 659 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 660 661 #ifdef CONFIG_CMD_KGDB 662 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 663 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 664 #endif 665 666 /* 667 * Environment Configuration 668 */ 669 670 #define CONFIG_HOSTNAME p1022ds 671 #define CONFIG_ROOTPATH "/opt/nfsroot" 672 #define CONFIG_BOOTFILE "uImage" 673 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 674 675 #define CONFIG_LOADADDR 1000000 676 677 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 678 679 #define CONFIG_BAUDRATE 115200 680 681 #define CONFIG_EXTRA_ENV_SETTINGS \ 682 "netdev=eth0\0" \ 683 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 684 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 685 "tftpflash=tftpboot $loadaddr $uboot && " \ 686 "protect off $ubootaddr +$filesize && " \ 687 "erase $ubootaddr +$filesize && " \ 688 "cp.b $loadaddr $ubootaddr $filesize && " \ 689 "protect on $ubootaddr +$filesize && " \ 690 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 691 "consoledev=ttyS0\0" \ 692 "ramdiskaddr=2000000\0" \ 693 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 694 "fdtaddr=c00000\0" \ 695 "fdtfile=p1022ds.dtb\0" \ 696 "bdev=sda3\0" \ 697 "hwconfig=esdhc;audclk:12\0" 698 699 #define CONFIG_HDBOOT \ 700 "setenv bootargs root=/dev/$bdev rw " \ 701 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 702 "tftp $loadaddr $bootfile;" \ 703 "tftp $fdtaddr $fdtfile;" \ 704 "bootm $loadaddr - $fdtaddr" 705 706 #define CONFIG_NFSBOOTCOMMAND \ 707 "setenv bootargs root=/dev/nfs rw " \ 708 "nfsroot=$serverip:$rootpath " \ 709 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 710 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 711 "tftp $loadaddr $bootfile;" \ 712 "tftp $fdtaddr $fdtfile;" \ 713 "bootm $loadaddr - $fdtaddr" 714 715 #define CONFIG_RAMBOOTCOMMAND \ 716 "setenv bootargs root=/dev/ram rw " \ 717 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 718 "tftp $ramdiskaddr $ramdiskfile;" \ 719 "tftp $loadaddr $bootfile;" \ 720 "tftp $fdtaddr $fdtfile;" \ 721 "bootm $loadaddr $ramdiskaddr $fdtaddr" 722 723 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 724 725 #endif 726