1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_P1010 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 #define CONFIG_NAND_FSL_IFC 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_SPL_MMC_MINIMAL 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 25 #define CONFIG_FSL_LAW /* Use common FSL init code */ 26 #define CONFIG_SYS_TEXT_BASE 0x11001000 27 #define CONFIG_SPL_TEXT_BASE 0xD0001000 28 #define CONFIG_SPL_PAD_TO 0x18000 29 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 30 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 31 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 32 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 33 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 34 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 35 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 36 #define CONFIG_SPL_MMC_BOOT 37 #ifdef CONFIG_SPL_BUILD 38 #define CONFIG_SPL_COMMON_INIT_DDR 39 #endif 40 #endif 41 42 #ifdef CONFIG_SPIFLASH 43 #ifdef CONFIG_SECURE_BOOT 44 #define CONFIG_RAMBOOT_SPIFLASH 45 #define CONFIG_SYS_TEXT_BASE 0x11000000 46 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 47 #else 48 #define CONFIG_SPL_SPI_SUPPORT 49 #define CONFIG_SPL_SPI_FLASH_MINIMAL 50 #define CONFIG_SPL_FLUSH_IMAGE 51 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 52 #define CONFIG_FSL_LAW /* Use common FSL init code */ 53 #define CONFIG_SYS_TEXT_BASE 0x11001000 54 #define CONFIG_SPL_TEXT_BASE 0xD0001000 55 #define CONFIG_SPL_PAD_TO 0x18000 56 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 63 #define CONFIG_SPL_SPI_BOOT 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SPL_COMMON_INIT_DDR 66 #endif 67 #endif 68 #endif 69 70 #ifdef CONFIG_NAND 71 #ifdef CONFIG_SECURE_BOOT 72 #define CONFIG_SPL_INIT_MINIMAL 73 #define CONFIG_SPL_NAND_BOOT 74 #define CONFIG_SPL_FLUSH_IMAGE 75 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 76 77 #define CONFIG_SYS_TEXT_BASE 0x00201000 78 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 79 #define CONFIG_SPL_MAX_SIZE 8192 80 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 81 #define CONFIG_SPL_RELOC_STACK 0x00100000 82 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 83 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 84 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 85 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 86 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 87 #else 88 #ifdef CONFIG_TPL_BUILD 89 #define CONFIG_SPL_NAND_BOOT 90 #define CONFIG_SPL_FLUSH_IMAGE 91 #define CONFIG_SPL_NAND_INIT 92 #define CONFIG_SPL_COMMON_INIT_DDR 93 #define CONFIG_SPL_MAX_SIZE (128 << 10) 94 #define CONFIG_SPL_TEXT_BASE 0xD0001000 95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 96 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 97 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 98 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 99 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 100 #elif defined(CONFIG_SPL_BUILD) 101 #define CONFIG_SPL_INIT_MINIMAL 102 #define CONFIG_SPL_NAND_MINIMAL 103 #define CONFIG_SPL_FLUSH_IMAGE 104 #define CONFIG_SPL_TEXT_BASE 0xff800000 105 #define CONFIG_SPL_MAX_SIZE 8192 106 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 107 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 108 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 109 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 110 #endif 111 #define CONFIG_SPL_PAD_TO 0x20000 112 #define CONFIG_TPL_PAD_TO 0x20000 113 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 114 #define CONFIG_SYS_TEXT_BASE 0x11001000 115 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 116 #endif 117 #endif 118 119 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 120 #define CONFIG_RAMBOOT_NAND 121 #define CONFIG_SYS_TEXT_BASE 0x11000000 122 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 123 #endif 124 125 #ifndef CONFIG_SYS_TEXT_BASE 126 #define CONFIG_SYS_TEXT_BASE 0xeff40000 127 #endif 128 129 #ifndef CONFIG_RESET_VECTOR_ADDRESS 130 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 131 #endif 132 133 #ifdef CONFIG_SPL_BUILD 134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 135 #else 136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 137 #endif 138 139 /* High Level Configuration Options */ 140 #define CONFIG_BOOKE /* BOOKE */ 141 #define CONFIG_E500 /* BOOKE e500 family */ 142 #define CONFIG_FSL_IFC /* Enable IFC Support */ 143 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 144 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 145 146 #define CONFIG_PCI /* Enable PCI/PCIE */ 147 #if defined(CONFIG_PCI) 148 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 149 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 150 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 151 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 152 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 153 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 154 155 #define CONFIG_CMD_PCI 156 157 /* 158 * PCI Windows 159 * Memory space is mapped 1-1, but I/O space must start from 0. 160 */ 161 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 162 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 163 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 164 #ifdef CONFIG_PHYS_64BIT 165 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 166 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 167 #else 168 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 169 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 170 #endif 171 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 172 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 173 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 174 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 175 #ifdef CONFIG_PHYS_64BIT 176 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 177 #else 178 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 179 #endif 180 181 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 182 #if defined(CONFIG_P1010RDB_PA) 183 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 184 #elif defined(CONFIG_P1010RDB_PB) 185 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 186 #endif 187 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 188 #ifdef CONFIG_PHYS_64BIT 189 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 190 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 191 #else 192 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 193 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 194 #endif 195 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 196 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 197 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 198 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 199 #ifdef CONFIG_PHYS_64BIT 200 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 201 #else 202 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 203 #endif 204 205 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 206 207 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 208 #define CONFIG_DOS_PARTITION 209 #endif 210 211 #define CONFIG_FSL_LAW /* Use common FSL init code */ 212 #define CONFIG_TSEC_ENET 213 #define CONFIG_ENV_OVERWRITE 214 215 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 216 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 217 218 #define CONFIG_MISC_INIT_R 219 #define CONFIG_HWCONFIG 220 /* 221 * These can be toggled for performance analysis, otherwise use default. 222 */ 223 #define CONFIG_L2_CACHE /* toggle L2 cache */ 224 #define CONFIG_BTB /* toggle branch predition */ 225 226 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 227 228 #define CONFIG_ENABLE_36BIT_PHYS 229 230 #ifdef CONFIG_PHYS_64BIT 231 #define CONFIG_ADDR_MAP 1 232 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 233 #endif 234 235 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 236 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 237 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 238 239 /* DDR Setup */ 240 #define CONFIG_SYS_FSL_DDR3 241 #define CONFIG_SYS_DDR_RAW_TIMING 242 #define CONFIG_DDR_SPD 243 #define CONFIG_SYS_SPD_BUS_NUM 1 244 #define SPD_EEPROM_ADDRESS 0x52 245 246 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 247 248 #ifndef __ASSEMBLY__ 249 extern unsigned long get_sdram_size(void); 250 #endif 251 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 252 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 253 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 254 255 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 256 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 257 258 /* DDR3 Controller Settings */ 259 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 260 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 261 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 262 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 263 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 264 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 265 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 266 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 267 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 268 #define CONFIG_SYS_DDR_RCW_1 0x00000000 269 #define CONFIG_SYS_DDR_RCW_2 0x00000000 270 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 271 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 272 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 273 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 274 275 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 276 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 277 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 278 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 279 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 280 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 281 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 282 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 283 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 284 285 /* settings for DDR3 at 667MT/s */ 286 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 287 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 288 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 289 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 290 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 291 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 292 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 293 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 294 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 295 296 #define CONFIG_SYS_CCSRBAR 0xffe00000 297 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 298 299 /* Don't relocate CCSRBAR while in NAND_SPL */ 300 #ifdef CONFIG_SPL_BUILD 301 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 302 #endif 303 304 /* 305 * Memory map 306 * 307 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 308 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 309 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 310 * 311 * Localbus non-cacheable 312 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 313 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 314 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 315 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 316 */ 317 318 /* 319 * IFC Definitions 320 */ 321 /* NOR Flash on IFC */ 322 #ifdef CONFIG_SPL_BUILD 323 #define CONFIG_SYS_NO_FLASH 324 #endif 325 326 #define CONFIG_SYS_FLASH_BASE 0xee000000 327 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 328 329 #ifdef CONFIG_PHYS_64BIT 330 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 331 #else 332 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 333 #endif 334 335 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 336 CSPR_PORT_SIZE_16 | \ 337 CSPR_MSEL_NOR | \ 338 CSPR_V) 339 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 340 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 341 /* NOR Flash Timing Params */ 342 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 343 FTIM0_NOR_TEADC(0x5) | \ 344 FTIM0_NOR_TEAHC(0x5) 345 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 346 FTIM1_NOR_TRAD_NOR(0x0f) 347 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 348 FTIM2_NOR_TCH(0x4) | \ 349 FTIM2_NOR_TWP(0x1c) 350 #define CONFIG_SYS_NOR_FTIM3 0x0 351 352 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 353 #define CONFIG_SYS_FLASH_QUIET_TEST 354 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 355 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 356 357 #undef CONFIG_SYS_FLASH_CHECKSUM 358 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 359 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 360 361 /* CFI for NOR Flash */ 362 #define CONFIG_FLASH_CFI_DRIVER 363 #define CONFIG_SYS_FLASH_CFI 364 #define CONFIG_SYS_FLASH_EMPTY_INFO 365 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 366 367 /* NAND Flash on IFC */ 368 #define CONFIG_SYS_NAND_BASE 0xff800000 369 #ifdef CONFIG_PHYS_64BIT 370 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 371 #else 372 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 373 #endif 374 375 #define CONFIG_MTD_DEVICE 376 #define CONFIG_MTD_PARTITION 377 #define CONFIG_CMD_MTDPARTS 378 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 379 #define MTDPARTS_DEFAULT \ 380 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 381 382 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 383 | CSPR_PORT_SIZE_8 \ 384 | CSPR_MSEL_NAND \ 385 | CSPR_V) 386 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 387 388 #if defined(CONFIG_P1010RDB_PA) 389 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 390 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 391 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 392 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 393 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 394 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 395 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 396 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 397 398 #elif defined(CONFIG_P1010RDB_PB) 399 #define CONFIG_SYS_NAND_ONFI_DETECTION 400 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 401 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 402 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 403 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 404 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 405 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 406 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 407 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 408 #endif 409 410 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 411 #define CONFIG_SYS_MAX_NAND_DEVICE 1 412 #define CONFIG_CMD_NAND 413 414 #if defined(CONFIG_P1010RDB_PA) 415 /* NAND Flash Timing Params */ 416 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 417 FTIM0_NAND_TWP(0x0C) | \ 418 FTIM0_NAND_TWCHT(0x04) | \ 419 FTIM0_NAND_TWH(0x05) 420 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 421 FTIM1_NAND_TWBE(0x1d) | \ 422 FTIM1_NAND_TRR(0x07) | \ 423 FTIM1_NAND_TRP(0x0c) 424 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 425 FTIM2_NAND_TREH(0x05) | \ 426 FTIM2_NAND_TWHRE(0x0f) 427 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 428 429 #elif defined(CONFIG_P1010RDB_PB) 430 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 431 /* ONFI NAND Flash mode0 Timing Params */ 432 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 433 FTIM0_NAND_TWP(0x18) | \ 434 FTIM0_NAND_TWCHT(0x07) | \ 435 FTIM0_NAND_TWH(0x0a)) 436 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 437 FTIM1_NAND_TWBE(0x39) | \ 438 FTIM1_NAND_TRR(0x0e) | \ 439 FTIM1_NAND_TRP(0x18)) 440 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 441 FTIM2_NAND_TREH(0x0a) | \ 442 FTIM2_NAND_TWHRE(0x1e)) 443 #define CONFIG_SYS_NAND_FTIM3 0x0 444 #endif 445 446 #define CONFIG_SYS_NAND_DDR_LAW 11 447 448 /* Set up IFC registers for boot location NOR/NAND */ 449 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 450 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 451 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 452 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 453 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 454 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 455 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 456 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 457 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 458 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 459 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 460 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 461 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 462 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 463 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 464 #else 465 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 466 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 467 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 468 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 469 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 470 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 471 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 472 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 473 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 474 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 475 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 476 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 477 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 478 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 479 #endif 480 481 /* CPLD on IFC */ 482 #define CONFIG_SYS_CPLD_BASE 0xffb00000 483 484 #ifdef CONFIG_PHYS_64BIT 485 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 486 #else 487 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 488 #endif 489 490 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 491 | CSPR_PORT_SIZE_8 \ 492 | CSPR_MSEL_GPCM \ 493 | CSPR_V) 494 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 495 #define CONFIG_SYS_CSOR3 0x0 496 /* CPLD Timing parameters for IFC CS3 */ 497 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 498 FTIM0_GPCM_TEADC(0x0e) | \ 499 FTIM0_GPCM_TEAHC(0x0e)) 500 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 501 FTIM1_GPCM_TRAD(0x1f)) 502 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 503 FTIM2_GPCM_TCH(0x8) | \ 504 FTIM2_GPCM_TWP(0x1f)) 505 #define CONFIG_SYS_CS3_FTIM3 0x0 506 507 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 508 defined(CONFIG_RAMBOOT_NAND) 509 #define CONFIG_SYS_RAMBOOT 510 #define CONFIG_SYS_EXTRA_ENV_RELOC 511 #else 512 #undef CONFIG_SYS_RAMBOOT 513 #endif 514 515 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 516 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 517 #define CONFIG_A003399_NOR_WORKAROUND 518 #endif 519 #endif 520 521 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 522 #define CONFIG_BOARD_EARLY_INIT_R 523 524 #define CONFIG_SYS_INIT_RAM_LOCK 525 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 526 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 527 528 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 529 - GENERATED_GBL_DATA_SIZE) 530 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 531 532 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 533 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 534 535 /* 536 * Config the L2 Cache as L2 SRAM 537 */ 538 #if defined(CONFIG_SPL_BUILD) 539 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 540 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 541 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 542 #define CONFIG_SYS_L2_SIZE (256 << 10) 543 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 544 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 545 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 546 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 547 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 548 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 549 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 550 #elif defined(CONFIG_NAND) 551 #ifdef CONFIG_TPL_BUILD 552 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 553 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 554 #define CONFIG_SYS_L2_SIZE (256 << 10) 555 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 556 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 557 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 558 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 559 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 560 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 561 #else 562 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 563 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 564 #define CONFIG_SYS_L2_SIZE (256 << 10) 565 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 566 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 567 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 568 #endif 569 #endif 570 #endif 571 572 /* Serial Port */ 573 #define CONFIG_CONS_INDEX 1 574 #undef CONFIG_SERIAL_SOFTWARE_FIFO 575 #define CONFIG_SYS_NS16550_SERIAL 576 #define CONFIG_SYS_NS16550_REG_SIZE 1 577 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 578 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 579 #define CONFIG_NS16550_MIN_FUNCTIONS 580 #endif 581 582 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 583 584 #define CONFIG_SYS_BAUDRATE_TABLE \ 585 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 586 587 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 588 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 589 590 /* I2C */ 591 #define CONFIG_SYS_I2C 592 #define CONFIG_SYS_I2C_FSL 593 #define CONFIG_SYS_FSL_I2C_SPEED 400000 594 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 595 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 596 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 597 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 598 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 599 #define I2C_PCA9557_ADDR1 0x18 600 #define I2C_PCA9557_ADDR2 0x19 601 #define I2C_PCA9557_BUS_NUM 0 602 603 /* I2C EEPROM */ 604 #if defined(CONFIG_P1010RDB_PB) 605 #define CONFIG_ID_EEPROM 606 #ifdef CONFIG_ID_EEPROM 607 #define CONFIG_SYS_I2C_EEPROM_NXID 608 #endif 609 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 610 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 611 #define CONFIG_SYS_EEPROM_BUS_NUM 0 612 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 613 #endif 614 /* enable read and write access to EEPROM */ 615 #define CONFIG_CMD_EEPROM 616 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 617 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 618 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 619 620 /* RTC */ 621 #define CONFIG_RTC_PT7C4338 622 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 623 624 /* 625 * SPI interface will not be available in case of NAND boot SPI CS0 will be 626 * used for SLIC 627 */ 628 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 629 /* eSPI - Enhanced SPI */ 630 #define CONFIG_SF_DEFAULT_SPEED 10000000 631 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 632 #endif 633 634 #if defined(CONFIG_TSEC_ENET) 635 #define CONFIG_MII /* MII PHY management */ 636 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 637 #define CONFIG_TSEC1 1 638 #define CONFIG_TSEC1_NAME "eTSEC1" 639 #define CONFIG_TSEC2 1 640 #define CONFIG_TSEC2_NAME "eTSEC2" 641 #define CONFIG_TSEC3 1 642 #define CONFIG_TSEC3_NAME "eTSEC3" 643 644 #define TSEC1_PHY_ADDR 1 645 #define TSEC2_PHY_ADDR 0 646 #define TSEC3_PHY_ADDR 2 647 648 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 649 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 650 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 651 652 #define TSEC1_PHYIDX 0 653 #define TSEC2_PHYIDX 0 654 #define TSEC3_PHYIDX 0 655 656 #define CONFIG_ETHPRIME "eTSEC1" 657 658 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 659 660 /* TBI PHY configuration for SGMII mode */ 661 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 662 TBICR_PHY_RESET \ 663 | TBICR_ANEG_ENABLE \ 664 | TBICR_FULL_DUPLEX \ 665 | TBICR_SPEED1_SET \ 666 ) 667 668 #endif /* CONFIG_TSEC_ENET */ 669 670 /* SATA */ 671 #define CONFIG_FSL_SATA 672 #define CONFIG_FSL_SATA_V2 673 #define CONFIG_LIBATA 674 675 #ifdef CONFIG_FSL_SATA 676 #define CONFIG_SYS_SATA_MAX_DEVICE 2 677 #define CONFIG_SATA1 678 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 679 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 680 #define CONFIG_SATA2 681 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 682 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 683 684 #define CONFIG_CMD_SATA 685 #define CONFIG_LBA48 686 #endif /* #ifdef CONFIG_FSL_SATA */ 687 688 #define CONFIG_MMC 689 #ifdef CONFIG_MMC 690 #define CONFIG_DOS_PARTITION 691 #define CONFIG_FSL_ESDHC 692 #define CONFIG_GENERIC_MMC 693 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 694 #endif 695 696 #define CONFIG_HAS_FSL_DR_USB 697 698 #if defined(CONFIG_HAS_FSL_DR_USB) 699 #define CONFIG_USB_EHCI 700 701 #ifdef CONFIG_USB_EHCI 702 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 703 #define CONFIG_USB_EHCI_FSL 704 #endif 705 #endif 706 707 /* 708 * Environment 709 */ 710 #if defined(CONFIG_SDCARD) 711 #define CONFIG_ENV_IS_IN_MMC 712 #define CONFIG_FSL_FIXED_MMC_LOCATION 713 #define CONFIG_SYS_MMC_ENV_DEV 0 714 #define CONFIG_ENV_SIZE 0x2000 715 #elif defined(CONFIG_SPIFLASH) 716 #define CONFIG_ENV_IS_IN_SPI_FLASH 717 #define CONFIG_ENV_SPI_BUS 0 718 #define CONFIG_ENV_SPI_CS 0 719 #define CONFIG_ENV_SPI_MAX_HZ 10000000 720 #define CONFIG_ENV_SPI_MODE 0 721 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 722 #define CONFIG_ENV_SECT_SIZE 0x10000 723 #define CONFIG_ENV_SIZE 0x2000 724 #elif defined(CONFIG_NAND) 725 #define CONFIG_ENV_IS_IN_NAND 726 #ifdef CONFIG_TPL_BUILD 727 #define CONFIG_ENV_SIZE 0x2000 728 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 729 #else 730 #if defined(CONFIG_P1010RDB_PA) 731 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 732 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 733 #elif defined(CONFIG_P1010RDB_PB) 734 #define CONFIG_ENV_SIZE (16 * 1024) 735 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 736 #endif 737 #endif 738 #define CONFIG_ENV_OFFSET (1024 * 1024) 739 #elif defined(CONFIG_SYS_RAMBOOT) 740 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 741 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 742 #define CONFIG_ENV_SIZE 0x2000 743 #else 744 #define CONFIG_ENV_IS_IN_FLASH 745 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 746 #define CONFIG_ENV_SIZE 0x2000 747 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 748 #endif 749 750 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 751 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 752 753 /* 754 * Command line configuration. 755 */ 756 #define CONFIG_CMD_DATE 757 #define CONFIG_CMD_ERRATA 758 #define CONFIG_CMD_IRQ 759 #define CONFIG_CMD_REGINFO 760 761 #undef CONFIG_WATCHDOG /* watchdog disabled */ 762 763 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 764 || defined(CONFIG_FSL_SATA) 765 #define CONFIG_DOS_PARTITION 766 #endif 767 768 /* Hash command with SHA acceleration supported in hardware */ 769 #ifdef CONFIG_FSL_CAAM 770 #define CONFIG_CMD_HASH 771 #define CONFIG_SHA_HW_ACCEL 772 #endif 773 774 /* 775 * Miscellaneous configurable options 776 */ 777 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 778 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 779 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 780 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 781 782 #if defined(CONFIG_CMD_KGDB) 783 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 784 #else 785 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 786 #endif 787 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 788 /* Print Buffer Size */ 789 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 790 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 791 792 /* 793 * For booting Linux, the board info and command line data 794 * have to be in the first 64 MB of memory, since this is 795 * the maximum mapped by the Linux kernel during initialization. 796 */ 797 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 798 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 799 800 #if defined(CONFIG_CMD_KGDB) 801 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 802 #endif 803 804 /* 805 * Environment Configuration 806 */ 807 808 #if defined(CONFIG_TSEC_ENET) 809 #define CONFIG_HAS_ETH0 810 #define CONFIG_HAS_ETH1 811 #define CONFIG_HAS_ETH2 812 #endif 813 814 #define CONFIG_ROOTPATH "/opt/nfsroot" 815 #define CONFIG_BOOTFILE "uImage" 816 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 817 818 /* default location for tftp and bootm */ 819 #define CONFIG_LOADADDR 1000000 820 821 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 822 823 #define CONFIG_BAUDRATE 115200 824 825 #define CONFIG_EXTRA_ENV_SETTINGS \ 826 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 827 "netdev=eth0\0" \ 828 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 829 "loadaddr=1000000\0" \ 830 "consoledev=ttyS0\0" \ 831 "ramdiskaddr=2000000\0" \ 832 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 833 "fdtaddr=1e00000\0" \ 834 "fdtfile=p1010rdb.dtb\0" \ 835 "bdev=sda1\0" \ 836 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 837 "othbootargs=ramdisk_size=600000\0" \ 838 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 839 "console=$consoledev,$baudrate $othbootargs; " \ 840 "usb start;" \ 841 "fatload usb 0:2 $loadaddr $bootfile;" \ 842 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 843 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 844 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 845 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 846 "console=$consoledev,$baudrate $othbootargs; " \ 847 "usb start;" \ 848 "ext2load usb 0:4 $loadaddr $bootfile;" \ 849 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 850 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 851 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 852 CONFIG_BOOTMODE 853 854 #if defined(CONFIG_P1010RDB_PA) 855 #define CONFIG_BOOTMODE \ 856 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 857 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 858 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 859 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 860 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 861 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 862 863 #elif defined(CONFIG_P1010RDB_PB) 864 #define CONFIG_BOOTMODE \ 865 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 866 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 867 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 868 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 869 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 870 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 871 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 872 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 873 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 874 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 875 #endif 876 877 #define CONFIG_RAMBOOTCOMMAND \ 878 "setenv bootargs root=/dev/ram rw " \ 879 "console=$consoledev,$baudrate $othbootargs; " \ 880 "tftp $ramdiskaddr $ramdiskfile;" \ 881 "tftp $loadaddr $bootfile;" \ 882 "tftp $fdtaddr $fdtfile;" \ 883 "bootm $loadaddr $ramdiskaddr $fdtaddr" 884 885 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 886 887 #include <asm/fsl_secure_boot.h> 888 889 #endif /* __CONFIG_H */ 890