1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_P1010 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 #define CONFIG_NAND_FSL_IFC 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 23 #define CONFIG_SPL_ENV_SUPPORT 24 #define CONFIG_SPL_SERIAL_SUPPORT 25 #define CONFIG_SPL_MMC_SUPPORT 26 #define CONFIG_SPL_MMC_MINIMAL 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_SPL_LIBGENERIC_SUPPORT 30 #define CONFIG_SPL_LIBCOMMON_SUPPORT 31 #define CONFIG_SPL_I2C_SUPPORT 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_SYS_TEXT_BASE 0x11001000 34 #define CONFIG_SPL_TEXT_BASE 0xD0001000 35 #define CONFIG_SPL_PAD_TO 0x18000 36 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 37 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 38 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 39 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 40 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 42 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 43 #define CONFIG_SPL_MMC_BOOT 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_COMMON_INIT_DDR 46 #endif 47 #endif 48 49 #ifdef CONFIG_SPIFLASH 50 #ifdef CONFIG_SECURE_BOOT 51 #define CONFIG_RAMBOOT_SPIFLASH 52 #define CONFIG_SYS_TEXT_BASE 0x11000000 53 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 54 #else 55 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 56 #define CONFIG_SPL_ENV_SUPPORT 57 #define CONFIG_SPL_SERIAL_SUPPORT 58 #define CONFIG_SPL_SPI_SUPPORT 59 #define CONFIG_SPL_SPI_FLASH_SUPPORT 60 #define CONFIG_SPL_SPI_FLASH_MINIMAL 61 #define CONFIG_SPL_FLUSH_IMAGE 62 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 63 #define CONFIG_SPL_LIBGENERIC_SUPPORT 64 #define CONFIG_SPL_LIBCOMMON_SUPPORT 65 #define CONFIG_SPL_I2C_SUPPORT 66 #define CONFIG_FSL_LAW /* Use common FSL init code */ 67 #define CONFIG_SYS_TEXT_BASE 0x11001000 68 #define CONFIG_SPL_TEXT_BASE 0xD0001000 69 #define CONFIG_SPL_PAD_TO 0x18000 70 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 75 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 77 #define CONFIG_SPL_SPI_BOOT 78 #ifdef CONFIG_SPL_BUILD 79 #define CONFIG_SPL_COMMON_INIT_DDR 80 #endif 81 #endif 82 #endif 83 84 #ifdef CONFIG_NAND 85 #ifdef CONFIG_SECURE_BOOT 86 #define CONFIG_SPL_INIT_MINIMAL 87 #define CONFIG_SPL_SERIAL_SUPPORT 88 #define CONFIG_SPL_NAND_SUPPORT 89 #define CONFIG_SPL_NAND_BOOT 90 #define CONFIG_SPL_FLUSH_IMAGE 91 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 92 93 #define CONFIG_SYS_TEXT_BASE 0x00201000 94 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 95 #define CONFIG_SPL_MAX_SIZE 8192 96 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 97 #define CONFIG_SPL_RELOC_STACK 0x00100000 98 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 99 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 100 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 101 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 102 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 103 #else 104 #ifdef CONFIG_TPL_BUILD 105 #define CONFIG_SPL_NAND_BOOT 106 #define CONFIG_SPL_FLUSH_IMAGE 107 #define CONFIG_TPL_ENV_SUPPORT 108 #define CONFIG_SPL_NAND_INIT 109 #define CONFIG_TPL_SERIAL_SUPPORT 110 #define CONFIG_TPL_LIBGENERIC_SUPPORT 111 #define CONFIG_TPL_LIBCOMMON_SUPPORT 112 #define CONFIG_TPL_I2C_SUPPORT 113 #define CONFIG_TPL_NAND_SUPPORT 114 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 115 #define CONFIG_SPL_COMMON_INIT_DDR 116 #define CONFIG_SPL_MAX_SIZE (128 << 10) 117 #define CONFIG_SPL_TEXT_BASE 0xD0001000 118 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 119 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 120 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 121 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 122 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 123 #elif defined(CONFIG_SPL_BUILD) 124 #define CONFIG_SPL_INIT_MINIMAL 125 #define CONFIG_SPL_SERIAL_SUPPORT 126 #define CONFIG_SPL_NAND_SUPPORT 127 #define CONFIG_SPL_NAND_MINIMAL 128 #define CONFIG_SPL_FLUSH_IMAGE 129 #define CONFIG_SPL_TEXT_BASE 0xff800000 130 #define CONFIG_SPL_MAX_SIZE 8192 131 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 132 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 133 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 134 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 135 #endif 136 #define CONFIG_SPL_PAD_TO 0x20000 137 #define CONFIG_TPL_PAD_TO 0x20000 138 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 139 #define CONFIG_SYS_TEXT_BASE 0x11001000 140 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 141 #endif 142 #endif 143 144 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 145 #define CONFIG_RAMBOOT_NAND 146 #define CONFIG_SYS_TEXT_BASE 0x11000000 147 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 148 #endif 149 150 #ifndef CONFIG_SYS_TEXT_BASE 151 #define CONFIG_SYS_TEXT_BASE 0xeff40000 152 #endif 153 154 #ifndef CONFIG_RESET_VECTOR_ADDRESS 155 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 156 #endif 157 158 #ifdef CONFIG_SPL_BUILD 159 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 160 #else 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 162 #endif 163 164 /* High Level Configuration Options */ 165 #define CONFIG_BOOKE /* BOOKE */ 166 #define CONFIG_E500 /* BOOKE e500 family */ 167 #define CONFIG_FSL_IFC /* Enable IFC Support */ 168 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 169 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 170 171 #define CONFIG_PCI /* Enable PCI/PCIE */ 172 #if defined(CONFIG_PCI) 173 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 174 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 175 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 176 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 177 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 178 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 179 180 #define CONFIG_CMD_PCI 181 182 /* 183 * PCI Windows 184 * Memory space is mapped 1-1, but I/O space must start from 0. 185 */ 186 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 187 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 188 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 189 #ifdef CONFIG_PHYS_64BIT 190 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 191 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 192 #else 193 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 194 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 195 #endif 196 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 197 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 198 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 199 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 200 #ifdef CONFIG_PHYS_64BIT 201 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 202 #else 203 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 204 #endif 205 206 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 207 #if defined(CONFIG_P1010RDB_PA) 208 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 209 #elif defined(CONFIG_P1010RDB_PB) 210 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 211 #endif 212 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 213 #ifdef CONFIG_PHYS_64BIT 214 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 215 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 216 #else 217 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 218 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 219 #endif 220 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 221 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 222 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 223 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 224 #ifdef CONFIG_PHYS_64BIT 225 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 226 #else 227 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 228 #endif 229 230 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 231 232 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 233 #define CONFIG_DOS_PARTITION 234 #endif 235 236 #define CONFIG_FSL_LAW /* Use common FSL init code */ 237 #define CONFIG_TSEC_ENET 238 #define CONFIG_ENV_OVERWRITE 239 240 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 241 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 242 243 #define CONFIG_MISC_INIT_R 244 #define CONFIG_HWCONFIG 245 /* 246 * These can be toggled for performance analysis, otherwise use default. 247 */ 248 #define CONFIG_L2_CACHE /* toggle L2 cache */ 249 #define CONFIG_BTB /* toggle branch predition */ 250 251 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 252 253 #define CONFIG_ENABLE_36BIT_PHYS 254 255 #ifdef CONFIG_PHYS_64BIT 256 #define CONFIG_ADDR_MAP 1 257 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 258 #endif 259 260 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 261 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 262 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 263 264 /* DDR Setup */ 265 #define CONFIG_SYS_FSL_DDR3 266 #define CONFIG_SYS_DDR_RAW_TIMING 267 #define CONFIG_DDR_SPD 268 #define CONFIG_SYS_SPD_BUS_NUM 1 269 #define SPD_EEPROM_ADDRESS 0x52 270 271 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 272 273 #ifndef __ASSEMBLY__ 274 extern unsigned long get_sdram_size(void); 275 #endif 276 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 277 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 278 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 279 280 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 281 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 282 283 /* DDR3 Controller Settings */ 284 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 285 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 286 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 287 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 288 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 289 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 290 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 291 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 292 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 293 #define CONFIG_SYS_DDR_RCW_1 0x00000000 294 #define CONFIG_SYS_DDR_RCW_2 0x00000000 295 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 296 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 297 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 298 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 299 300 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 301 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 302 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 303 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 304 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 305 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 306 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 307 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 308 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 309 310 /* settings for DDR3 at 667MT/s */ 311 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 312 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 313 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 314 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 315 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 316 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 317 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 318 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 319 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 320 321 #define CONFIG_SYS_CCSRBAR 0xffe00000 322 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 323 324 /* Don't relocate CCSRBAR while in NAND_SPL */ 325 #ifdef CONFIG_SPL_BUILD 326 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 327 #endif 328 329 /* 330 * Memory map 331 * 332 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 333 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 334 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 335 * 336 * Localbus non-cacheable 337 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 338 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 339 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 340 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 341 */ 342 343 /* 344 * IFC Definitions 345 */ 346 /* NOR Flash on IFC */ 347 #ifdef CONFIG_SPL_BUILD 348 #define CONFIG_SYS_NO_FLASH 349 #endif 350 351 #define CONFIG_SYS_FLASH_BASE 0xee000000 352 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 353 354 #ifdef CONFIG_PHYS_64BIT 355 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 356 #else 357 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 358 #endif 359 360 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 361 CSPR_PORT_SIZE_16 | \ 362 CSPR_MSEL_NOR | \ 363 CSPR_V) 364 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 365 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 366 /* NOR Flash Timing Params */ 367 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 368 FTIM0_NOR_TEADC(0x5) | \ 369 FTIM0_NOR_TEAHC(0x5) 370 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 371 FTIM1_NOR_TRAD_NOR(0x0f) 372 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 373 FTIM2_NOR_TCH(0x4) | \ 374 FTIM2_NOR_TWP(0x1c) 375 #define CONFIG_SYS_NOR_FTIM3 0x0 376 377 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 378 #define CONFIG_SYS_FLASH_QUIET_TEST 379 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 380 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 381 382 #undef CONFIG_SYS_FLASH_CHECKSUM 383 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 384 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 385 386 /* CFI for NOR Flash */ 387 #define CONFIG_FLASH_CFI_DRIVER 388 #define CONFIG_SYS_FLASH_CFI 389 #define CONFIG_SYS_FLASH_EMPTY_INFO 390 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 391 392 /* NAND Flash on IFC */ 393 #define CONFIG_SYS_NAND_BASE 0xff800000 394 #ifdef CONFIG_PHYS_64BIT 395 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 396 #else 397 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 398 #endif 399 400 #define CONFIG_MTD_DEVICE 401 #define CONFIG_MTD_PARTITION 402 #define CONFIG_CMD_MTDPARTS 403 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 404 #define MTDPARTS_DEFAULT \ 405 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 406 407 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 408 | CSPR_PORT_SIZE_8 \ 409 | CSPR_MSEL_NAND \ 410 | CSPR_V) 411 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 412 413 #if defined(CONFIG_P1010RDB_PA) 414 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 415 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 416 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 417 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 418 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 419 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 420 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 421 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 422 423 #elif defined(CONFIG_P1010RDB_PB) 424 #define CONFIG_SYS_NAND_ONFI_DETECTION 425 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 426 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 427 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 428 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 429 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 430 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 431 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 432 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 433 #endif 434 435 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 436 #define CONFIG_SYS_MAX_NAND_DEVICE 1 437 #define CONFIG_CMD_NAND 438 439 #if defined(CONFIG_P1010RDB_PA) 440 /* NAND Flash Timing Params */ 441 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 442 FTIM0_NAND_TWP(0x0C) | \ 443 FTIM0_NAND_TWCHT(0x04) | \ 444 FTIM0_NAND_TWH(0x05) 445 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 446 FTIM1_NAND_TWBE(0x1d) | \ 447 FTIM1_NAND_TRR(0x07) | \ 448 FTIM1_NAND_TRP(0x0c) 449 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 450 FTIM2_NAND_TREH(0x05) | \ 451 FTIM2_NAND_TWHRE(0x0f) 452 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 453 454 #elif defined(CONFIG_P1010RDB_PB) 455 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 456 /* ONFI NAND Flash mode0 Timing Params */ 457 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 458 FTIM0_NAND_TWP(0x18) | \ 459 FTIM0_NAND_TWCHT(0x07) | \ 460 FTIM0_NAND_TWH(0x0a)) 461 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 462 FTIM1_NAND_TWBE(0x39) | \ 463 FTIM1_NAND_TRR(0x0e) | \ 464 FTIM1_NAND_TRP(0x18)) 465 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 466 FTIM2_NAND_TREH(0x0a) | \ 467 FTIM2_NAND_TWHRE(0x1e)) 468 #define CONFIG_SYS_NAND_FTIM3 0x0 469 #endif 470 471 #define CONFIG_SYS_NAND_DDR_LAW 11 472 473 /* Set up IFC registers for boot location NOR/NAND */ 474 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 475 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 476 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 477 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 478 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 479 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 480 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 481 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 482 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 483 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 484 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 485 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 486 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 487 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 488 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 489 #else 490 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 491 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 492 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 493 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 494 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 495 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 496 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 497 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 498 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 499 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 500 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 501 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 502 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 503 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 504 #endif 505 506 /* CPLD on IFC */ 507 #define CONFIG_SYS_CPLD_BASE 0xffb00000 508 509 #ifdef CONFIG_PHYS_64BIT 510 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 511 #else 512 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 513 #endif 514 515 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 516 | CSPR_PORT_SIZE_8 \ 517 | CSPR_MSEL_GPCM \ 518 | CSPR_V) 519 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 520 #define CONFIG_SYS_CSOR3 0x0 521 /* CPLD Timing parameters for IFC CS3 */ 522 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 523 FTIM0_GPCM_TEADC(0x0e) | \ 524 FTIM0_GPCM_TEAHC(0x0e)) 525 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 526 FTIM1_GPCM_TRAD(0x1f)) 527 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 528 FTIM2_GPCM_TCH(0x8) | \ 529 FTIM2_GPCM_TWP(0x1f)) 530 #define CONFIG_SYS_CS3_FTIM3 0x0 531 532 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 533 defined(CONFIG_RAMBOOT_NAND) 534 #define CONFIG_SYS_RAMBOOT 535 #define CONFIG_SYS_EXTRA_ENV_RELOC 536 #else 537 #undef CONFIG_SYS_RAMBOOT 538 #endif 539 540 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 541 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 542 #define CONFIG_A003399_NOR_WORKAROUND 543 #endif 544 #endif 545 546 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 547 #define CONFIG_BOARD_EARLY_INIT_R 548 549 #define CONFIG_SYS_INIT_RAM_LOCK 550 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 551 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 552 553 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 554 - GENERATED_GBL_DATA_SIZE) 555 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 556 557 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 558 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 559 560 /* 561 * Config the L2 Cache as L2 SRAM 562 */ 563 #if defined(CONFIG_SPL_BUILD) 564 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 565 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 566 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 567 #define CONFIG_SYS_L2_SIZE (256 << 10) 568 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 569 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 570 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 571 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 572 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 573 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 574 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 575 #elif defined(CONFIG_NAND) 576 #ifdef CONFIG_TPL_BUILD 577 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 578 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 579 #define CONFIG_SYS_L2_SIZE (256 << 10) 580 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 581 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 582 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 583 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 584 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 585 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 586 #else 587 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 588 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 589 #define CONFIG_SYS_L2_SIZE (256 << 10) 590 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 591 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 592 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 593 #endif 594 #endif 595 #endif 596 597 /* Serial Port */ 598 #define CONFIG_CONS_INDEX 1 599 #undef CONFIG_SERIAL_SOFTWARE_FIFO 600 #define CONFIG_SYS_NS16550_SERIAL 601 #define CONFIG_SYS_NS16550_REG_SIZE 1 602 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 603 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 604 #define CONFIG_NS16550_MIN_FUNCTIONS 605 #endif 606 607 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 608 609 #define CONFIG_SYS_BAUDRATE_TABLE \ 610 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 611 612 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 613 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 614 615 /* I2C */ 616 #define CONFIG_SYS_I2C 617 #define CONFIG_SYS_I2C_FSL 618 #define CONFIG_SYS_FSL_I2C_SPEED 400000 619 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 620 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 621 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 622 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 623 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 624 #define I2C_PCA9557_ADDR1 0x18 625 #define I2C_PCA9557_ADDR2 0x19 626 #define I2C_PCA9557_BUS_NUM 0 627 628 /* I2C EEPROM */ 629 #if defined(CONFIG_P1010RDB_PB) 630 #define CONFIG_ID_EEPROM 631 #ifdef CONFIG_ID_EEPROM 632 #define CONFIG_SYS_I2C_EEPROM_NXID 633 #endif 634 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 635 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 636 #define CONFIG_SYS_EEPROM_BUS_NUM 0 637 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 638 #endif 639 /* enable read and write access to EEPROM */ 640 #define CONFIG_CMD_EEPROM 641 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 642 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 643 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 644 645 /* RTC */ 646 #define CONFIG_RTC_PT7C4338 647 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 648 649 /* 650 * SPI interface will not be available in case of NAND boot SPI CS0 will be 651 * used for SLIC 652 */ 653 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 654 /* eSPI - Enhanced SPI */ 655 #define CONFIG_SF_DEFAULT_SPEED 10000000 656 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 657 #endif 658 659 #if defined(CONFIG_TSEC_ENET) 660 #define CONFIG_MII /* MII PHY management */ 661 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 662 #define CONFIG_TSEC1 1 663 #define CONFIG_TSEC1_NAME "eTSEC1" 664 #define CONFIG_TSEC2 1 665 #define CONFIG_TSEC2_NAME "eTSEC2" 666 #define CONFIG_TSEC3 1 667 #define CONFIG_TSEC3_NAME "eTSEC3" 668 669 #define TSEC1_PHY_ADDR 1 670 #define TSEC2_PHY_ADDR 0 671 #define TSEC3_PHY_ADDR 2 672 673 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 674 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 675 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 676 677 #define TSEC1_PHYIDX 0 678 #define TSEC2_PHYIDX 0 679 #define TSEC3_PHYIDX 0 680 681 #define CONFIG_ETHPRIME "eTSEC1" 682 683 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 684 685 /* TBI PHY configuration for SGMII mode */ 686 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 687 TBICR_PHY_RESET \ 688 | TBICR_ANEG_ENABLE \ 689 | TBICR_FULL_DUPLEX \ 690 | TBICR_SPEED1_SET \ 691 ) 692 693 #endif /* CONFIG_TSEC_ENET */ 694 695 /* SATA */ 696 #define CONFIG_FSL_SATA 697 #define CONFIG_FSL_SATA_V2 698 #define CONFIG_LIBATA 699 700 #ifdef CONFIG_FSL_SATA 701 #define CONFIG_SYS_SATA_MAX_DEVICE 2 702 #define CONFIG_SATA1 703 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 704 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 705 #define CONFIG_SATA2 706 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 707 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 708 709 #define CONFIG_CMD_SATA 710 #define CONFIG_LBA48 711 #endif /* #ifdef CONFIG_FSL_SATA */ 712 713 #define CONFIG_MMC 714 #ifdef CONFIG_MMC 715 #define CONFIG_DOS_PARTITION 716 #define CONFIG_FSL_ESDHC 717 #define CONFIG_GENERIC_MMC 718 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 719 #endif 720 721 #define CONFIG_HAS_FSL_DR_USB 722 723 #if defined(CONFIG_HAS_FSL_DR_USB) 724 #define CONFIG_USB_EHCI 725 726 #ifdef CONFIG_USB_EHCI 727 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 728 #define CONFIG_USB_EHCI_FSL 729 #endif 730 #endif 731 732 /* 733 * Environment 734 */ 735 #if defined(CONFIG_SDCARD) 736 #define CONFIG_ENV_IS_IN_MMC 737 #define CONFIG_FSL_FIXED_MMC_LOCATION 738 #define CONFIG_SYS_MMC_ENV_DEV 0 739 #define CONFIG_ENV_SIZE 0x2000 740 #elif defined(CONFIG_SPIFLASH) 741 #define CONFIG_ENV_IS_IN_SPI_FLASH 742 #define CONFIG_ENV_SPI_BUS 0 743 #define CONFIG_ENV_SPI_CS 0 744 #define CONFIG_ENV_SPI_MAX_HZ 10000000 745 #define CONFIG_ENV_SPI_MODE 0 746 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 747 #define CONFIG_ENV_SECT_SIZE 0x10000 748 #define CONFIG_ENV_SIZE 0x2000 749 #elif defined(CONFIG_NAND) 750 #define CONFIG_ENV_IS_IN_NAND 751 #ifdef CONFIG_TPL_BUILD 752 #define CONFIG_ENV_SIZE 0x2000 753 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 754 #else 755 #if defined(CONFIG_P1010RDB_PA) 756 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 757 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 758 #elif defined(CONFIG_P1010RDB_PB) 759 #define CONFIG_ENV_SIZE (16 * 1024) 760 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 761 #endif 762 #endif 763 #define CONFIG_ENV_OFFSET (1024 * 1024) 764 #elif defined(CONFIG_SYS_RAMBOOT) 765 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 766 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 767 #define CONFIG_ENV_SIZE 0x2000 768 #else 769 #define CONFIG_ENV_IS_IN_FLASH 770 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 771 #define CONFIG_ENV_SIZE 0x2000 772 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 773 #endif 774 775 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 776 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 777 778 /* 779 * Command line configuration. 780 */ 781 #define CONFIG_CMD_DATE 782 #define CONFIG_CMD_ERRATA 783 #define CONFIG_CMD_IRQ 784 #define CONFIG_CMD_REGINFO 785 786 #undef CONFIG_WATCHDOG /* watchdog disabled */ 787 788 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 789 || defined(CONFIG_FSL_SATA) 790 #define CONFIG_DOS_PARTITION 791 #endif 792 793 /* Hash command with SHA acceleration supported in hardware */ 794 #ifdef CONFIG_FSL_CAAM 795 #define CONFIG_CMD_HASH 796 #define CONFIG_SHA_HW_ACCEL 797 #endif 798 799 /* 800 * Miscellaneous configurable options 801 */ 802 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 803 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 804 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 805 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 806 807 #if defined(CONFIG_CMD_KGDB) 808 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 809 #else 810 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 811 #endif 812 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 813 /* Print Buffer Size */ 814 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 815 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 816 817 /* 818 * For booting Linux, the board info and command line data 819 * have to be in the first 64 MB of memory, since this is 820 * the maximum mapped by the Linux kernel during initialization. 821 */ 822 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 823 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 824 825 #if defined(CONFIG_CMD_KGDB) 826 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 827 #endif 828 829 /* 830 * Environment Configuration 831 */ 832 833 #if defined(CONFIG_TSEC_ENET) 834 #define CONFIG_HAS_ETH0 835 #define CONFIG_HAS_ETH1 836 #define CONFIG_HAS_ETH2 837 #endif 838 839 #define CONFIG_ROOTPATH "/opt/nfsroot" 840 #define CONFIG_BOOTFILE "uImage" 841 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 842 843 /* default location for tftp and bootm */ 844 #define CONFIG_LOADADDR 1000000 845 846 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 847 848 #define CONFIG_BAUDRATE 115200 849 850 #define CONFIG_EXTRA_ENV_SETTINGS \ 851 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 852 "netdev=eth0\0" \ 853 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 854 "loadaddr=1000000\0" \ 855 "consoledev=ttyS0\0" \ 856 "ramdiskaddr=2000000\0" \ 857 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 858 "fdtaddr=1e00000\0" \ 859 "fdtfile=p1010rdb.dtb\0" \ 860 "bdev=sda1\0" \ 861 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 862 "othbootargs=ramdisk_size=600000\0" \ 863 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 864 "console=$consoledev,$baudrate $othbootargs; " \ 865 "usb start;" \ 866 "fatload usb 0:2 $loadaddr $bootfile;" \ 867 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 868 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 869 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 870 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 871 "console=$consoledev,$baudrate $othbootargs; " \ 872 "usb start;" \ 873 "ext2load usb 0:4 $loadaddr $bootfile;" \ 874 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 875 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 876 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 877 CONFIG_BOOTMODE 878 879 #if defined(CONFIG_P1010RDB_PA) 880 #define CONFIG_BOOTMODE \ 881 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 882 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 883 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 884 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 885 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 886 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 887 888 #elif defined(CONFIG_P1010RDB_PB) 889 #define CONFIG_BOOTMODE \ 890 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 891 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 892 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 893 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 894 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 895 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 896 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 897 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 898 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 899 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 900 #endif 901 902 #define CONFIG_RAMBOOTCOMMAND \ 903 "setenv bootargs root=/dev/ram rw " \ 904 "console=$consoledev,$baudrate $othbootargs; " \ 905 "tftp $ramdiskaddr $ramdiskfile;" \ 906 "tftp $loadaddr $bootfile;" \ 907 "tftp $fdtaddr $fdtfile;" \ 908 "bootm $loadaddr $ramdiskaddr $fdtaddr" 909 910 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 911 912 #include <asm/fsl_secure_boot.h> 913 914 #endif /* __CONFIG_H */ 915