1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_P1010 15 #define CONFIG_E500 /* BOOKE e500 family */ 16 #include <asm/config_mpc85xx.h> 17 #define CONFIG_NAND_FSL_IFC 18 19 #ifdef CONFIG_SDCARD 20 #define CONFIG_SPL_MMC_MINIMAL 21 #define CONFIG_SPL_FLUSH_IMAGE 22 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 23 #define CONFIG_FSL_LAW /* Use common FSL init code */ 24 #define CONFIG_SYS_TEXT_BASE 0x11001000 25 #define CONFIG_SPL_TEXT_BASE 0xD0001000 26 #define CONFIG_SPL_PAD_TO 0x18000 27 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 28 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 29 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 30 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 31 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 32 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 33 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 34 #define CONFIG_SPL_MMC_BOOT 35 #ifdef CONFIG_SPL_BUILD 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #endif 38 #endif 39 40 #ifdef CONFIG_SPIFLASH 41 #ifdef CONFIG_SECURE_BOOT 42 #define CONFIG_RAMBOOT_SPIFLASH 43 #define CONFIG_SYS_TEXT_BASE 0x11000000 44 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 45 #else 46 #define CONFIG_SPL_SPI_FLASH_MINIMAL 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_FSL_LAW /* Use common FSL init code */ 50 #define CONFIG_SYS_TEXT_BASE 0x11001000 51 #define CONFIG_SPL_TEXT_BASE 0xD0001000 52 #define CONFIG_SPL_PAD_TO 0x18000 53 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 58 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 60 #define CONFIG_SPL_SPI_BOOT 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_COMMON_INIT_DDR 63 #endif 64 #endif 65 #endif 66 67 #ifdef CONFIG_NAND 68 #ifdef CONFIG_SECURE_BOOT 69 #define CONFIG_SPL_INIT_MINIMAL 70 #define CONFIG_SPL_NAND_BOOT 71 #define CONFIG_SPL_FLUSH_IMAGE 72 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 73 74 #define CONFIG_SYS_TEXT_BASE 0x00201000 75 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 76 #define CONFIG_SPL_MAX_SIZE 8192 77 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 78 #define CONFIG_SPL_RELOC_STACK 0x00100000 79 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 80 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 81 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 82 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 84 #else 85 #ifdef CONFIG_TPL_BUILD 86 #define CONFIG_SPL_NAND_BOOT 87 #define CONFIG_SPL_FLUSH_IMAGE 88 #define CONFIG_SPL_NAND_INIT 89 #define CONFIG_SPL_COMMON_INIT_DDR 90 #define CONFIG_SPL_MAX_SIZE (128 << 10) 91 #define CONFIG_SPL_TEXT_BASE 0xD0001000 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 94 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 95 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 96 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 97 #elif defined(CONFIG_SPL_BUILD) 98 #define CONFIG_SPL_INIT_MINIMAL 99 #define CONFIG_SPL_NAND_MINIMAL 100 #define CONFIG_SPL_FLUSH_IMAGE 101 #define CONFIG_SPL_TEXT_BASE 0xff800000 102 #define CONFIG_SPL_MAX_SIZE 8192 103 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 104 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 105 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 106 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 107 #endif 108 #define CONFIG_SPL_PAD_TO 0x20000 109 #define CONFIG_TPL_PAD_TO 0x20000 110 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 111 #define CONFIG_SYS_TEXT_BASE 0x11001000 112 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 113 #endif 114 #endif 115 116 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 117 #define CONFIG_RAMBOOT_NAND 118 #define CONFIG_SYS_TEXT_BASE 0x11000000 119 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 120 #endif 121 122 #ifndef CONFIG_SYS_TEXT_BASE 123 #define CONFIG_SYS_TEXT_BASE 0xeff40000 124 #endif 125 126 #ifndef CONFIG_RESET_VECTOR_ADDRESS 127 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 128 #endif 129 130 #ifdef CONFIG_SPL_BUILD 131 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 132 #else 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 134 #endif 135 136 /* High Level Configuration Options */ 137 #define CONFIG_BOOKE /* BOOKE */ 138 #define CONFIG_E500 /* BOOKE e500 family */ 139 #define CONFIG_FSL_IFC /* Enable IFC Support */ 140 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 141 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 142 143 #if defined(CONFIG_PCI) 144 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 145 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 146 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 147 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 148 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 149 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 150 151 #define CONFIG_CMD_PCI 152 153 /* 154 * PCI Windows 155 * Memory space is mapped 1-1, but I/O space must start from 0. 156 */ 157 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 158 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 159 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 162 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 163 #else 164 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 165 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 166 #endif 167 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 168 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 169 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 170 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 171 #ifdef CONFIG_PHYS_64BIT 172 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 173 #else 174 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 175 #endif 176 177 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 178 #if defined(CONFIG_P1010RDB_PA) 179 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 180 #elif defined(CONFIG_P1010RDB_PB) 181 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 182 #endif 183 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 184 #ifdef CONFIG_PHYS_64BIT 185 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 186 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 187 #else 188 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 189 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 190 #endif 191 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 192 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 193 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 194 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 195 #ifdef CONFIG_PHYS_64BIT 196 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 197 #else 198 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 199 #endif 200 201 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 202 203 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 204 #define CONFIG_DOS_PARTITION 205 #endif 206 207 #define CONFIG_FSL_LAW /* Use common FSL init code */ 208 #define CONFIG_TSEC_ENET 209 #define CONFIG_ENV_OVERWRITE 210 211 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 212 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 213 214 #define CONFIG_MISC_INIT_R 215 #define CONFIG_HWCONFIG 216 /* 217 * These can be toggled for performance analysis, otherwise use default. 218 */ 219 #define CONFIG_L2_CACHE /* toggle L2 cache */ 220 #define CONFIG_BTB /* toggle branch predition */ 221 222 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 223 224 #define CONFIG_ENABLE_36BIT_PHYS 225 226 #ifdef CONFIG_PHYS_64BIT 227 #define CONFIG_ADDR_MAP 1 228 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 229 #endif 230 231 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 232 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 233 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 234 235 /* DDR Setup */ 236 #define CONFIG_SYS_FSL_DDR3 237 #define CONFIG_SYS_DDR_RAW_TIMING 238 #define CONFIG_DDR_SPD 239 #define CONFIG_SYS_SPD_BUS_NUM 1 240 #define SPD_EEPROM_ADDRESS 0x52 241 242 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 243 244 #ifndef __ASSEMBLY__ 245 extern unsigned long get_sdram_size(void); 246 #endif 247 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 248 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 249 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 250 251 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 252 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 253 254 /* DDR3 Controller Settings */ 255 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 256 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 257 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 258 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 259 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 260 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 261 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 262 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 263 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 264 #define CONFIG_SYS_DDR_RCW_1 0x00000000 265 #define CONFIG_SYS_DDR_RCW_2 0x00000000 266 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 267 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 268 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 269 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 270 271 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 272 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 273 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 274 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 275 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 276 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 277 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 278 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 279 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 280 281 /* settings for DDR3 at 667MT/s */ 282 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 283 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 284 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 285 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 286 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 287 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 288 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 289 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 290 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 291 292 #define CONFIG_SYS_CCSRBAR 0xffe00000 293 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 294 295 /* Don't relocate CCSRBAR while in NAND_SPL */ 296 #ifdef CONFIG_SPL_BUILD 297 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 298 #endif 299 300 /* 301 * Memory map 302 * 303 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 304 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 305 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 306 * 307 * Localbus non-cacheable 308 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 309 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 310 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 311 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 312 */ 313 314 /* 315 * IFC Definitions 316 */ 317 /* NOR Flash on IFC */ 318 #ifdef CONFIG_SPL_BUILD 319 #define CONFIG_SYS_NO_FLASH 320 #endif 321 322 #define CONFIG_SYS_FLASH_BASE 0xee000000 323 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 324 325 #ifdef CONFIG_PHYS_64BIT 326 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 327 #else 328 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 329 #endif 330 331 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 332 CSPR_PORT_SIZE_16 | \ 333 CSPR_MSEL_NOR | \ 334 CSPR_V) 335 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 336 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 337 /* NOR Flash Timing Params */ 338 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 339 FTIM0_NOR_TEADC(0x5) | \ 340 FTIM0_NOR_TEAHC(0x5) 341 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 342 FTIM1_NOR_TRAD_NOR(0x0f) 343 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 344 FTIM2_NOR_TCH(0x4) | \ 345 FTIM2_NOR_TWP(0x1c) 346 #define CONFIG_SYS_NOR_FTIM3 0x0 347 348 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 349 #define CONFIG_SYS_FLASH_QUIET_TEST 350 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 351 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 352 353 #undef CONFIG_SYS_FLASH_CHECKSUM 354 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 355 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 356 357 /* CFI for NOR Flash */ 358 #define CONFIG_FLASH_CFI_DRIVER 359 #define CONFIG_SYS_FLASH_CFI 360 #define CONFIG_SYS_FLASH_EMPTY_INFO 361 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 362 363 /* NAND Flash on IFC */ 364 #define CONFIG_SYS_NAND_BASE 0xff800000 365 #ifdef CONFIG_PHYS_64BIT 366 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 367 #else 368 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 369 #endif 370 371 #define CONFIG_MTD_DEVICE 372 #define CONFIG_MTD_PARTITION 373 #define CONFIG_CMD_MTDPARTS 374 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 375 #define MTDPARTS_DEFAULT \ 376 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 377 378 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 379 | CSPR_PORT_SIZE_8 \ 380 | CSPR_MSEL_NAND \ 381 | CSPR_V) 382 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 383 384 #if defined(CONFIG_P1010RDB_PA) 385 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 386 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 387 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 388 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 389 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 390 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 391 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 392 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 393 394 #elif defined(CONFIG_P1010RDB_PB) 395 #define CONFIG_SYS_NAND_ONFI_DETECTION 396 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 397 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 398 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 399 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 400 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 401 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 402 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 403 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 404 #endif 405 406 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 407 #define CONFIG_SYS_MAX_NAND_DEVICE 1 408 #define CONFIG_CMD_NAND 409 410 #if defined(CONFIG_P1010RDB_PA) 411 /* NAND Flash Timing Params */ 412 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 413 FTIM0_NAND_TWP(0x0C) | \ 414 FTIM0_NAND_TWCHT(0x04) | \ 415 FTIM0_NAND_TWH(0x05) 416 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 417 FTIM1_NAND_TWBE(0x1d) | \ 418 FTIM1_NAND_TRR(0x07) | \ 419 FTIM1_NAND_TRP(0x0c) 420 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 421 FTIM2_NAND_TREH(0x05) | \ 422 FTIM2_NAND_TWHRE(0x0f) 423 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 424 425 #elif defined(CONFIG_P1010RDB_PB) 426 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 427 /* ONFI NAND Flash mode0 Timing Params */ 428 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 429 FTIM0_NAND_TWP(0x18) | \ 430 FTIM0_NAND_TWCHT(0x07) | \ 431 FTIM0_NAND_TWH(0x0a)) 432 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 433 FTIM1_NAND_TWBE(0x39) | \ 434 FTIM1_NAND_TRR(0x0e) | \ 435 FTIM1_NAND_TRP(0x18)) 436 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 437 FTIM2_NAND_TREH(0x0a) | \ 438 FTIM2_NAND_TWHRE(0x1e)) 439 #define CONFIG_SYS_NAND_FTIM3 0x0 440 #endif 441 442 #define CONFIG_SYS_NAND_DDR_LAW 11 443 444 /* Set up IFC registers for boot location NOR/NAND */ 445 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 446 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 447 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 448 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 449 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 450 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 451 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 452 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 453 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 454 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 455 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 456 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 457 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 458 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 459 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 460 #else 461 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 462 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 463 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 464 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 465 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 466 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 467 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 468 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 469 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 470 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 471 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 472 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 473 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 474 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 475 #endif 476 477 /* CPLD on IFC */ 478 #define CONFIG_SYS_CPLD_BASE 0xffb00000 479 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 482 #else 483 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 484 #endif 485 486 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 487 | CSPR_PORT_SIZE_8 \ 488 | CSPR_MSEL_GPCM \ 489 | CSPR_V) 490 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 491 #define CONFIG_SYS_CSOR3 0x0 492 /* CPLD Timing parameters for IFC CS3 */ 493 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 494 FTIM0_GPCM_TEADC(0x0e) | \ 495 FTIM0_GPCM_TEAHC(0x0e)) 496 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 497 FTIM1_GPCM_TRAD(0x1f)) 498 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 499 FTIM2_GPCM_TCH(0x8) | \ 500 FTIM2_GPCM_TWP(0x1f)) 501 #define CONFIG_SYS_CS3_FTIM3 0x0 502 503 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 504 defined(CONFIG_RAMBOOT_NAND) 505 #define CONFIG_SYS_RAMBOOT 506 #define CONFIG_SYS_EXTRA_ENV_RELOC 507 #else 508 #undef CONFIG_SYS_RAMBOOT 509 #endif 510 511 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 512 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 513 #define CONFIG_A003399_NOR_WORKAROUND 514 #endif 515 #endif 516 517 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 518 #define CONFIG_BOARD_EARLY_INIT_R 519 520 #define CONFIG_SYS_INIT_RAM_LOCK 521 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 522 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 523 524 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 525 - GENERATED_GBL_DATA_SIZE) 526 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 527 528 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 529 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 530 531 /* 532 * Config the L2 Cache as L2 SRAM 533 */ 534 #if defined(CONFIG_SPL_BUILD) 535 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 536 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 537 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 538 #define CONFIG_SYS_L2_SIZE (256 << 10) 539 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 540 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 541 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 542 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 543 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 544 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 545 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 546 #elif defined(CONFIG_NAND) 547 #ifdef CONFIG_TPL_BUILD 548 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 549 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 550 #define CONFIG_SYS_L2_SIZE (256 << 10) 551 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 552 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 553 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 554 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 555 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 556 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 557 #else 558 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 559 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 560 #define CONFIG_SYS_L2_SIZE (256 << 10) 561 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 562 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 563 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 564 #endif 565 #endif 566 #endif 567 568 /* Serial Port */ 569 #define CONFIG_CONS_INDEX 1 570 #undef CONFIG_SERIAL_SOFTWARE_FIFO 571 #define CONFIG_SYS_NS16550_SERIAL 572 #define CONFIG_SYS_NS16550_REG_SIZE 1 573 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 574 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 575 #define CONFIG_NS16550_MIN_FUNCTIONS 576 #endif 577 578 #define CONFIG_SYS_BAUDRATE_TABLE \ 579 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 580 581 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 582 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 583 584 /* I2C */ 585 #define CONFIG_SYS_I2C 586 #define CONFIG_SYS_I2C_FSL 587 #define CONFIG_SYS_FSL_I2C_SPEED 400000 588 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 589 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 590 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 591 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 592 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 593 #define I2C_PCA9557_ADDR1 0x18 594 #define I2C_PCA9557_ADDR2 0x19 595 #define I2C_PCA9557_BUS_NUM 0 596 597 /* I2C EEPROM */ 598 #if defined(CONFIG_P1010RDB_PB) 599 #define CONFIG_ID_EEPROM 600 #ifdef CONFIG_ID_EEPROM 601 #define CONFIG_SYS_I2C_EEPROM_NXID 602 #endif 603 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 604 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 605 #define CONFIG_SYS_EEPROM_BUS_NUM 0 606 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 607 #endif 608 /* enable read and write access to EEPROM */ 609 #define CONFIG_CMD_EEPROM 610 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 611 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 612 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 613 614 /* RTC */ 615 #define CONFIG_RTC_PT7C4338 616 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 617 618 /* 619 * SPI interface will not be available in case of NAND boot SPI CS0 will be 620 * used for SLIC 621 */ 622 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 623 /* eSPI - Enhanced SPI */ 624 #define CONFIG_SF_DEFAULT_SPEED 10000000 625 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 626 #endif 627 628 #if defined(CONFIG_TSEC_ENET) 629 #define CONFIG_MII /* MII PHY management */ 630 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 631 #define CONFIG_TSEC1 1 632 #define CONFIG_TSEC1_NAME "eTSEC1" 633 #define CONFIG_TSEC2 1 634 #define CONFIG_TSEC2_NAME "eTSEC2" 635 #define CONFIG_TSEC3 1 636 #define CONFIG_TSEC3_NAME "eTSEC3" 637 638 #define TSEC1_PHY_ADDR 1 639 #define TSEC2_PHY_ADDR 0 640 #define TSEC3_PHY_ADDR 2 641 642 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 643 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 644 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 645 646 #define TSEC1_PHYIDX 0 647 #define TSEC2_PHYIDX 0 648 #define TSEC3_PHYIDX 0 649 650 #define CONFIG_ETHPRIME "eTSEC1" 651 652 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 653 654 /* TBI PHY configuration for SGMII mode */ 655 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 656 TBICR_PHY_RESET \ 657 | TBICR_ANEG_ENABLE \ 658 | TBICR_FULL_DUPLEX \ 659 | TBICR_SPEED1_SET \ 660 ) 661 662 #endif /* CONFIG_TSEC_ENET */ 663 664 /* SATA */ 665 #define CONFIG_FSL_SATA 666 #define CONFIG_FSL_SATA_V2 667 #define CONFIG_LIBATA 668 669 #ifdef CONFIG_FSL_SATA 670 #define CONFIG_SYS_SATA_MAX_DEVICE 2 671 #define CONFIG_SATA1 672 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 673 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 674 #define CONFIG_SATA2 675 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 676 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 677 678 #define CONFIG_CMD_SATA 679 #define CONFIG_LBA48 680 #endif /* #ifdef CONFIG_FSL_SATA */ 681 682 #define CONFIG_MMC 683 #ifdef CONFIG_MMC 684 #define CONFIG_DOS_PARTITION 685 #define CONFIG_FSL_ESDHC 686 #define CONFIG_GENERIC_MMC 687 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 688 #endif 689 690 #define CONFIG_HAS_FSL_DR_USB 691 692 #if defined(CONFIG_HAS_FSL_DR_USB) 693 #define CONFIG_USB_EHCI 694 695 #ifdef CONFIG_USB_EHCI 696 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 697 #define CONFIG_USB_EHCI_FSL 698 #endif 699 #endif 700 701 /* 702 * Environment 703 */ 704 #if defined(CONFIG_SDCARD) 705 #define CONFIG_ENV_IS_IN_MMC 706 #define CONFIG_FSL_FIXED_MMC_LOCATION 707 #define CONFIG_SYS_MMC_ENV_DEV 0 708 #define CONFIG_ENV_SIZE 0x2000 709 #elif defined(CONFIG_SPIFLASH) 710 #define CONFIG_ENV_IS_IN_SPI_FLASH 711 #define CONFIG_ENV_SPI_BUS 0 712 #define CONFIG_ENV_SPI_CS 0 713 #define CONFIG_ENV_SPI_MAX_HZ 10000000 714 #define CONFIG_ENV_SPI_MODE 0 715 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 716 #define CONFIG_ENV_SECT_SIZE 0x10000 717 #define CONFIG_ENV_SIZE 0x2000 718 #elif defined(CONFIG_NAND) 719 #define CONFIG_ENV_IS_IN_NAND 720 #ifdef CONFIG_TPL_BUILD 721 #define CONFIG_ENV_SIZE 0x2000 722 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 723 #else 724 #if defined(CONFIG_P1010RDB_PA) 725 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 726 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 727 #elif defined(CONFIG_P1010RDB_PB) 728 #define CONFIG_ENV_SIZE (16 * 1024) 729 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 730 #endif 731 #endif 732 #define CONFIG_ENV_OFFSET (1024 * 1024) 733 #elif defined(CONFIG_SYS_RAMBOOT) 734 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 735 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 736 #define CONFIG_ENV_SIZE 0x2000 737 #else 738 #define CONFIG_ENV_IS_IN_FLASH 739 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 740 #define CONFIG_ENV_SIZE 0x2000 741 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 742 #endif 743 744 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 745 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 746 747 /* 748 * Command line configuration. 749 */ 750 #define CONFIG_CMD_DATE 751 #define CONFIG_CMD_ERRATA 752 #define CONFIG_CMD_IRQ 753 #define CONFIG_CMD_REGINFO 754 755 #undef CONFIG_WATCHDOG /* watchdog disabled */ 756 757 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 758 || defined(CONFIG_FSL_SATA) 759 #define CONFIG_DOS_PARTITION 760 #endif 761 762 /* Hash command with SHA acceleration supported in hardware */ 763 #ifdef CONFIG_FSL_CAAM 764 #define CONFIG_CMD_HASH 765 #define CONFIG_SHA_HW_ACCEL 766 #endif 767 768 /* 769 * Miscellaneous configurable options 770 */ 771 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 772 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 773 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 774 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 775 776 #if defined(CONFIG_CMD_KGDB) 777 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 778 #else 779 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 780 #endif 781 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 782 /* Print Buffer Size */ 783 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 784 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 785 786 /* 787 * For booting Linux, the board info and command line data 788 * have to be in the first 64 MB of memory, since this is 789 * the maximum mapped by the Linux kernel during initialization. 790 */ 791 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 792 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 793 794 #if defined(CONFIG_CMD_KGDB) 795 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 796 #endif 797 798 /* 799 * Environment Configuration 800 */ 801 802 #if defined(CONFIG_TSEC_ENET) 803 #define CONFIG_HAS_ETH0 804 #define CONFIG_HAS_ETH1 805 #define CONFIG_HAS_ETH2 806 #endif 807 808 #define CONFIG_ROOTPATH "/opt/nfsroot" 809 #define CONFIG_BOOTFILE "uImage" 810 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 811 812 /* default location for tftp and bootm */ 813 #define CONFIG_LOADADDR 1000000 814 815 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 816 817 #define CONFIG_BAUDRATE 115200 818 819 #define CONFIG_EXTRA_ENV_SETTINGS \ 820 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 821 "netdev=eth0\0" \ 822 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 823 "loadaddr=1000000\0" \ 824 "consoledev=ttyS0\0" \ 825 "ramdiskaddr=2000000\0" \ 826 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 827 "fdtaddr=1e00000\0" \ 828 "fdtfile=p1010rdb.dtb\0" \ 829 "bdev=sda1\0" \ 830 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 831 "othbootargs=ramdisk_size=600000\0" \ 832 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 833 "console=$consoledev,$baudrate $othbootargs; " \ 834 "usb start;" \ 835 "fatload usb 0:2 $loadaddr $bootfile;" \ 836 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 837 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 838 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 839 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 840 "console=$consoledev,$baudrate $othbootargs; " \ 841 "usb start;" \ 842 "ext2load usb 0:4 $loadaddr $bootfile;" \ 843 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 844 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 845 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 846 CONFIG_BOOTMODE 847 848 #if defined(CONFIG_P1010RDB_PA) 849 #define CONFIG_BOOTMODE \ 850 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 851 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 852 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 853 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 854 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 855 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 856 857 #elif defined(CONFIG_P1010RDB_PB) 858 #define CONFIG_BOOTMODE \ 859 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 860 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 861 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 862 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 863 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 864 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 865 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 866 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 867 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 868 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 869 #endif 870 871 #define CONFIG_RAMBOOTCOMMAND \ 872 "setenv bootargs root=/dev/ram rw " \ 873 "console=$consoledev,$baudrate $othbootargs; " \ 874 "tftp $ramdiskaddr $ramdiskfile;" \ 875 "tftp $loadaddr $bootfile;" \ 876 "tftp $fdtaddr $fdtfile;" \ 877 "bootm $loadaddr $ramdiskaddr $fdtaddr" 878 879 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 880 881 #include <asm/fsl_secure_boot.h> 882 883 #endif /* __CONFIG_H */ 884