1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_P1010 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 #define CONFIG_NAND_FSL_IFC 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 23 #define CONFIG_SPL_SERIAL_SUPPORT 24 #define CONFIG_SPL_MMC_SUPPORT 25 #define CONFIG_SPL_MMC_MINIMAL 26 #define CONFIG_SPL_FLUSH_IMAGE 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 28 #define CONFIG_SPL_LIBGENERIC_SUPPORT 29 #define CONFIG_SPL_LIBCOMMON_SUPPORT 30 #define CONFIG_SPL_I2C_SUPPORT 31 #define CONFIG_FSL_LAW /* Use common FSL init code */ 32 #define CONFIG_SYS_TEXT_BASE 0x11001000 33 #define CONFIG_SPL_TEXT_BASE 0xD0001000 34 #define CONFIG_SPL_PAD_TO 0x18000 35 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 37 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 38 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 41 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 42 #define CONFIG_SPL_MMC_BOOT 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SPL_COMMON_INIT_DDR 45 #endif 46 #endif 47 48 #ifdef CONFIG_SPIFLASH 49 #ifdef CONFIG_SECURE_BOOT 50 #define CONFIG_RAMBOOT_SPIFLASH 51 #define CONFIG_SYS_TEXT_BASE 0x11000000 52 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 53 #else 54 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 55 #define CONFIG_SPL_SERIAL_SUPPORT 56 #define CONFIG_SPL_SPI_SUPPORT 57 #define CONFIG_SPL_SPI_FLASH_SUPPORT 58 #define CONFIG_SPL_SPI_FLASH_MINIMAL 59 #define CONFIG_SPL_FLUSH_IMAGE 60 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 61 #define CONFIG_SPL_LIBGENERIC_SUPPORT 62 #define CONFIG_SPL_LIBCOMMON_SUPPORT 63 #define CONFIG_SPL_I2C_SUPPORT 64 #define CONFIG_FSL_LAW /* Use common FSL init code */ 65 #define CONFIG_SYS_TEXT_BASE 0x11001000 66 #define CONFIG_SPL_TEXT_BASE 0xD0001000 67 #define CONFIG_SPL_PAD_TO 0x18000 68 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 75 #define CONFIG_SPL_SPI_BOOT 76 #ifdef CONFIG_SPL_BUILD 77 #define CONFIG_SPL_COMMON_INIT_DDR 78 #endif 79 #endif 80 #endif 81 82 #ifdef CONFIG_NAND 83 #ifdef CONFIG_SECURE_BOOT 84 #define CONFIG_SPL_INIT_MINIMAL 85 #define CONFIG_SPL_SERIAL_SUPPORT 86 #define CONFIG_SPL_NAND_SUPPORT 87 #define CONFIG_SPL_NAND_BOOT 88 #define CONFIG_SPL_FLUSH_IMAGE 89 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 90 91 #define CONFIG_SYS_TEXT_BASE 0x00201000 92 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 93 #define CONFIG_SPL_MAX_SIZE 8192 94 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 95 #define CONFIG_SPL_RELOC_STACK 0x00100000 96 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 97 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 98 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 99 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 100 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 101 #else 102 #ifdef CONFIG_TPL_BUILD 103 #define CONFIG_SPL_NAND_BOOT 104 #define CONFIG_SPL_FLUSH_IMAGE 105 #define CONFIG_SPL_NAND_INIT 106 #define CONFIG_TPL_SERIAL_SUPPORT 107 #define CONFIG_TPL_LIBGENERIC_SUPPORT 108 #define CONFIG_TPL_LIBCOMMON_SUPPORT 109 #define CONFIG_TPL_I2C_SUPPORT 110 #define CONFIG_TPL_NAND_SUPPORT 111 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 112 #define CONFIG_SPL_COMMON_INIT_DDR 113 #define CONFIG_SPL_MAX_SIZE (128 << 10) 114 #define CONFIG_SPL_TEXT_BASE 0xD0001000 115 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 116 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 117 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 118 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 119 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 120 #elif defined(CONFIG_SPL_BUILD) 121 #define CONFIG_SPL_INIT_MINIMAL 122 #define CONFIG_SPL_SERIAL_SUPPORT 123 #define CONFIG_SPL_NAND_SUPPORT 124 #define CONFIG_SPL_NAND_MINIMAL 125 #define CONFIG_SPL_FLUSH_IMAGE 126 #define CONFIG_SPL_TEXT_BASE 0xff800000 127 #define CONFIG_SPL_MAX_SIZE 8192 128 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 129 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 130 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 131 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 132 #endif 133 #define CONFIG_SPL_PAD_TO 0x20000 134 #define CONFIG_TPL_PAD_TO 0x20000 135 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 136 #define CONFIG_SYS_TEXT_BASE 0x11001000 137 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 138 #endif 139 #endif 140 141 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 142 #define CONFIG_RAMBOOT_NAND 143 #define CONFIG_SYS_TEXT_BASE 0x11000000 144 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 145 #endif 146 147 #ifndef CONFIG_SYS_TEXT_BASE 148 #define CONFIG_SYS_TEXT_BASE 0xeff40000 149 #endif 150 151 #ifndef CONFIG_RESET_VECTOR_ADDRESS 152 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 153 #endif 154 155 #ifdef CONFIG_SPL_BUILD 156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 157 #else 158 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 159 #endif 160 161 /* High Level Configuration Options */ 162 #define CONFIG_BOOKE /* BOOKE */ 163 #define CONFIG_E500 /* BOOKE e500 family */ 164 #define CONFIG_FSL_IFC /* Enable IFC Support */ 165 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 166 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 167 168 #define CONFIG_PCI /* Enable PCI/PCIE */ 169 #if defined(CONFIG_PCI) 170 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 171 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 172 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 173 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 174 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 175 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 176 177 #define CONFIG_CMD_PCI 178 179 /* 180 * PCI Windows 181 * Memory space is mapped 1-1, but I/O space must start from 0. 182 */ 183 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 184 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 185 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 186 #ifdef CONFIG_PHYS_64BIT 187 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 188 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 189 #else 190 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 191 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 192 #endif 193 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 194 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 195 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 196 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 197 #ifdef CONFIG_PHYS_64BIT 198 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 199 #else 200 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 201 #endif 202 203 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 204 #if defined(CONFIG_P1010RDB_PA) 205 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 206 #elif defined(CONFIG_P1010RDB_PB) 207 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 208 #endif 209 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 210 #ifdef CONFIG_PHYS_64BIT 211 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 212 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 213 #else 214 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 215 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 216 #endif 217 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 218 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 219 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 220 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 221 #ifdef CONFIG_PHYS_64BIT 222 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 223 #else 224 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 225 #endif 226 227 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 228 229 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 230 #define CONFIG_DOS_PARTITION 231 #endif 232 233 #define CONFIG_FSL_LAW /* Use common FSL init code */ 234 #define CONFIG_TSEC_ENET 235 #define CONFIG_ENV_OVERWRITE 236 237 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 238 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 239 240 #define CONFIG_MISC_INIT_R 241 #define CONFIG_HWCONFIG 242 /* 243 * These can be toggled for performance analysis, otherwise use default. 244 */ 245 #define CONFIG_L2_CACHE /* toggle L2 cache */ 246 #define CONFIG_BTB /* toggle branch predition */ 247 248 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 249 250 #define CONFIG_ENABLE_36BIT_PHYS 251 252 #ifdef CONFIG_PHYS_64BIT 253 #define CONFIG_ADDR_MAP 1 254 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 255 #endif 256 257 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 258 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 259 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 260 261 /* DDR Setup */ 262 #define CONFIG_SYS_FSL_DDR3 263 #define CONFIG_SYS_DDR_RAW_TIMING 264 #define CONFIG_DDR_SPD 265 #define CONFIG_SYS_SPD_BUS_NUM 1 266 #define SPD_EEPROM_ADDRESS 0x52 267 268 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 269 270 #ifndef __ASSEMBLY__ 271 extern unsigned long get_sdram_size(void); 272 #endif 273 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 274 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 275 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 276 277 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 278 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 279 280 /* DDR3 Controller Settings */ 281 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 282 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 283 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 284 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 285 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 286 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 287 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 288 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 289 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 290 #define CONFIG_SYS_DDR_RCW_1 0x00000000 291 #define CONFIG_SYS_DDR_RCW_2 0x00000000 292 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 293 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 294 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 295 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 296 297 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 298 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 299 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 300 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 301 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 302 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 303 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 304 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 305 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 306 307 /* settings for DDR3 at 667MT/s */ 308 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 309 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 310 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 311 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 312 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 313 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 314 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 315 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 316 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 317 318 #define CONFIG_SYS_CCSRBAR 0xffe00000 319 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 320 321 /* Don't relocate CCSRBAR while in NAND_SPL */ 322 #ifdef CONFIG_SPL_BUILD 323 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 324 #endif 325 326 /* 327 * Memory map 328 * 329 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 330 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 331 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 332 * 333 * Localbus non-cacheable 334 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 335 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 336 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 337 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 338 */ 339 340 /* 341 * IFC Definitions 342 */ 343 /* NOR Flash on IFC */ 344 #ifdef CONFIG_SPL_BUILD 345 #define CONFIG_SYS_NO_FLASH 346 #endif 347 348 #define CONFIG_SYS_FLASH_BASE 0xee000000 349 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 350 351 #ifdef CONFIG_PHYS_64BIT 352 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 353 #else 354 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 355 #endif 356 357 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 358 CSPR_PORT_SIZE_16 | \ 359 CSPR_MSEL_NOR | \ 360 CSPR_V) 361 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 362 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 363 /* NOR Flash Timing Params */ 364 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 365 FTIM0_NOR_TEADC(0x5) | \ 366 FTIM0_NOR_TEAHC(0x5) 367 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 368 FTIM1_NOR_TRAD_NOR(0x0f) 369 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 370 FTIM2_NOR_TCH(0x4) | \ 371 FTIM2_NOR_TWP(0x1c) 372 #define CONFIG_SYS_NOR_FTIM3 0x0 373 374 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 375 #define CONFIG_SYS_FLASH_QUIET_TEST 376 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 377 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 378 379 #undef CONFIG_SYS_FLASH_CHECKSUM 380 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 381 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 382 383 /* CFI for NOR Flash */ 384 #define CONFIG_FLASH_CFI_DRIVER 385 #define CONFIG_SYS_FLASH_CFI 386 #define CONFIG_SYS_FLASH_EMPTY_INFO 387 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 388 389 /* NAND Flash on IFC */ 390 #define CONFIG_SYS_NAND_BASE 0xff800000 391 #ifdef CONFIG_PHYS_64BIT 392 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 393 #else 394 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 395 #endif 396 397 #define CONFIG_MTD_DEVICE 398 #define CONFIG_MTD_PARTITION 399 #define CONFIG_CMD_MTDPARTS 400 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 401 #define MTDPARTS_DEFAULT \ 402 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 403 404 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 405 | CSPR_PORT_SIZE_8 \ 406 | CSPR_MSEL_NAND \ 407 | CSPR_V) 408 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 409 410 #if defined(CONFIG_P1010RDB_PA) 411 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 412 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 413 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 414 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 415 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 416 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 417 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 418 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 419 420 #elif defined(CONFIG_P1010RDB_PB) 421 #define CONFIG_SYS_NAND_ONFI_DETECTION 422 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 423 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 424 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 425 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 426 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 427 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 428 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 429 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 430 #endif 431 432 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 433 #define CONFIG_SYS_MAX_NAND_DEVICE 1 434 #define CONFIG_CMD_NAND 435 436 #if defined(CONFIG_P1010RDB_PA) 437 /* NAND Flash Timing Params */ 438 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 439 FTIM0_NAND_TWP(0x0C) | \ 440 FTIM0_NAND_TWCHT(0x04) | \ 441 FTIM0_NAND_TWH(0x05) 442 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 443 FTIM1_NAND_TWBE(0x1d) | \ 444 FTIM1_NAND_TRR(0x07) | \ 445 FTIM1_NAND_TRP(0x0c) 446 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 447 FTIM2_NAND_TREH(0x05) | \ 448 FTIM2_NAND_TWHRE(0x0f) 449 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 450 451 #elif defined(CONFIG_P1010RDB_PB) 452 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 453 /* ONFI NAND Flash mode0 Timing Params */ 454 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 455 FTIM0_NAND_TWP(0x18) | \ 456 FTIM0_NAND_TWCHT(0x07) | \ 457 FTIM0_NAND_TWH(0x0a)) 458 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 459 FTIM1_NAND_TWBE(0x39) | \ 460 FTIM1_NAND_TRR(0x0e) | \ 461 FTIM1_NAND_TRP(0x18)) 462 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 463 FTIM2_NAND_TREH(0x0a) | \ 464 FTIM2_NAND_TWHRE(0x1e)) 465 #define CONFIG_SYS_NAND_FTIM3 0x0 466 #endif 467 468 #define CONFIG_SYS_NAND_DDR_LAW 11 469 470 /* Set up IFC registers for boot location NOR/NAND */ 471 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 472 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 473 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 474 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 475 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 476 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 477 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 478 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 479 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 480 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 481 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 482 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 483 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 484 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 485 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 486 #else 487 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 488 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 489 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 490 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 491 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 492 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 493 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 494 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 495 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 496 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 497 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 498 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 499 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 500 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 501 #endif 502 503 /* CPLD on IFC */ 504 #define CONFIG_SYS_CPLD_BASE 0xffb00000 505 506 #ifdef CONFIG_PHYS_64BIT 507 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 508 #else 509 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 510 #endif 511 512 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 513 | CSPR_PORT_SIZE_8 \ 514 | CSPR_MSEL_GPCM \ 515 | CSPR_V) 516 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 517 #define CONFIG_SYS_CSOR3 0x0 518 /* CPLD Timing parameters for IFC CS3 */ 519 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 520 FTIM0_GPCM_TEADC(0x0e) | \ 521 FTIM0_GPCM_TEAHC(0x0e)) 522 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 523 FTIM1_GPCM_TRAD(0x1f)) 524 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 525 FTIM2_GPCM_TCH(0x8) | \ 526 FTIM2_GPCM_TWP(0x1f)) 527 #define CONFIG_SYS_CS3_FTIM3 0x0 528 529 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 530 defined(CONFIG_RAMBOOT_NAND) 531 #define CONFIG_SYS_RAMBOOT 532 #define CONFIG_SYS_EXTRA_ENV_RELOC 533 #else 534 #undef CONFIG_SYS_RAMBOOT 535 #endif 536 537 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 538 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 539 #define CONFIG_A003399_NOR_WORKAROUND 540 #endif 541 #endif 542 543 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 544 #define CONFIG_BOARD_EARLY_INIT_R 545 546 #define CONFIG_SYS_INIT_RAM_LOCK 547 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 548 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 549 550 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 551 - GENERATED_GBL_DATA_SIZE) 552 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 553 554 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 555 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 556 557 /* 558 * Config the L2 Cache as L2 SRAM 559 */ 560 #if defined(CONFIG_SPL_BUILD) 561 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 562 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 563 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 564 #define CONFIG_SYS_L2_SIZE (256 << 10) 565 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 566 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 567 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 568 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 569 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 570 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 571 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 572 #elif defined(CONFIG_NAND) 573 #ifdef CONFIG_TPL_BUILD 574 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 575 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 576 #define CONFIG_SYS_L2_SIZE (256 << 10) 577 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 578 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 579 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 580 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 581 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 582 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 583 #else 584 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 585 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 586 #define CONFIG_SYS_L2_SIZE (256 << 10) 587 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 588 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 589 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 590 #endif 591 #endif 592 #endif 593 594 /* Serial Port */ 595 #define CONFIG_CONS_INDEX 1 596 #undef CONFIG_SERIAL_SOFTWARE_FIFO 597 #define CONFIG_SYS_NS16550_SERIAL 598 #define CONFIG_SYS_NS16550_REG_SIZE 1 599 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 600 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 601 #define CONFIG_NS16550_MIN_FUNCTIONS 602 #endif 603 604 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 605 606 #define CONFIG_SYS_BAUDRATE_TABLE \ 607 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 608 609 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 610 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 611 612 /* I2C */ 613 #define CONFIG_SYS_I2C 614 #define CONFIG_SYS_I2C_FSL 615 #define CONFIG_SYS_FSL_I2C_SPEED 400000 616 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 617 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 618 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 619 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 620 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 621 #define I2C_PCA9557_ADDR1 0x18 622 #define I2C_PCA9557_ADDR2 0x19 623 #define I2C_PCA9557_BUS_NUM 0 624 625 /* I2C EEPROM */ 626 #if defined(CONFIG_P1010RDB_PB) 627 #define CONFIG_ID_EEPROM 628 #ifdef CONFIG_ID_EEPROM 629 #define CONFIG_SYS_I2C_EEPROM_NXID 630 #endif 631 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 632 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 633 #define CONFIG_SYS_EEPROM_BUS_NUM 0 634 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 635 #endif 636 /* enable read and write access to EEPROM */ 637 #define CONFIG_CMD_EEPROM 638 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 639 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 640 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 641 642 /* RTC */ 643 #define CONFIG_RTC_PT7C4338 644 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 645 646 /* 647 * SPI interface will not be available in case of NAND boot SPI CS0 will be 648 * used for SLIC 649 */ 650 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 651 /* eSPI - Enhanced SPI */ 652 #define CONFIG_SF_DEFAULT_SPEED 10000000 653 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 654 #endif 655 656 #if defined(CONFIG_TSEC_ENET) 657 #define CONFIG_MII /* MII PHY management */ 658 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 659 #define CONFIG_TSEC1 1 660 #define CONFIG_TSEC1_NAME "eTSEC1" 661 #define CONFIG_TSEC2 1 662 #define CONFIG_TSEC2_NAME "eTSEC2" 663 #define CONFIG_TSEC3 1 664 #define CONFIG_TSEC3_NAME "eTSEC3" 665 666 #define TSEC1_PHY_ADDR 1 667 #define TSEC2_PHY_ADDR 0 668 #define TSEC3_PHY_ADDR 2 669 670 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 671 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 672 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 673 674 #define TSEC1_PHYIDX 0 675 #define TSEC2_PHYIDX 0 676 #define TSEC3_PHYIDX 0 677 678 #define CONFIG_ETHPRIME "eTSEC1" 679 680 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 681 682 /* TBI PHY configuration for SGMII mode */ 683 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 684 TBICR_PHY_RESET \ 685 | TBICR_ANEG_ENABLE \ 686 | TBICR_FULL_DUPLEX \ 687 | TBICR_SPEED1_SET \ 688 ) 689 690 #endif /* CONFIG_TSEC_ENET */ 691 692 /* SATA */ 693 #define CONFIG_FSL_SATA 694 #define CONFIG_FSL_SATA_V2 695 #define CONFIG_LIBATA 696 697 #ifdef CONFIG_FSL_SATA 698 #define CONFIG_SYS_SATA_MAX_DEVICE 2 699 #define CONFIG_SATA1 700 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 701 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 702 #define CONFIG_SATA2 703 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 704 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 705 706 #define CONFIG_CMD_SATA 707 #define CONFIG_LBA48 708 #endif /* #ifdef CONFIG_FSL_SATA */ 709 710 #define CONFIG_MMC 711 #ifdef CONFIG_MMC 712 #define CONFIG_DOS_PARTITION 713 #define CONFIG_FSL_ESDHC 714 #define CONFIG_GENERIC_MMC 715 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 716 #endif 717 718 #define CONFIG_HAS_FSL_DR_USB 719 720 #if defined(CONFIG_HAS_FSL_DR_USB) 721 #define CONFIG_USB_EHCI 722 723 #ifdef CONFIG_USB_EHCI 724 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 725 #define CONFIG_USB_EHCI_FSL 726 #endif 727 #endif 728 729 /* 730 * Environment 731 */ 732 #if defined(CONFIG_SDCARD) 733 #define CONFIG_ENV_IS_IN_MMC 734 #define CONFIG_FSL_FIXED_MMC_LOCATION 735 #define CONFIG_SYS_MMC_ENV_DEV 0 736 #define CONFIG_ENV_SIZE 0x2000 737 #elif defined(CONFIG_SPIFLASH) 738 #define CONFIG_ENV_IS_IN_SPI_FLASH 739 #define CONFIG_ENV_SPI_BUS 0 740 #define CONFIG_ENV_SPI_CS 0 741 #define CONFIG_ENV_SPI_MAX_HZ 10000000 742 #define CONFIG_ENV_SPI_MODE 0 743 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 744 #define CONFIG_ENV_SECT_SIZE 0x10000 745 #define CONFIG_ENV_SIZE 0x2000 746 #elif defined(CONFIG_NAND) 747 #define CONFIG_ENV_IS_IN_NAND 748 #ifdef CONFIG_TPL_BUILD 749 #define CONFIG_ENV_SIZE 0x2000 750 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 751 #else 752 #if defined(CONFIG_P1010RDB_PA) 753 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 754 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 755 #elif defined(CONFIG_P1010RDB_PB) 756 #define CONFIG_ENV_SIZE (16 * 1024) 757 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 758 #endif 759 #endif 760 #define CONFIG_ENV_OFFSET (1024 * 1024) 761 #elif defined(CONFIG_SYS_RAMBOOT) 762 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 763 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 764 #define CONFIG_ENV_SIZE 0x2000 765 #else 766 #define CONFIG_ENV_IS_IN_FLASH 767 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 768 #define CONFIG_ENV_SIZE 0x2000 769 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 770 #endif 771 772 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 773 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 774 775 /* 776 * Command line configuration. 777 */ 778 #define CONFIG_CMD_DATE 779 #define CONFIG_CMD_ERRATA 780 #define CONFIG_CMD_IRQ 781 #define CONFIG_CMD_REGINFO 782 783 #undef CONFIG_WATCHDOG /* watchdog disabled */ 784 785 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 786 || defined(CONFIG_FSL_SATA) 787 #define CONFIG_DOS_PARTITION 788 #endif 789 790 /* Hash command with SHA acceleration supported in hardware */ 791 #ifdef CONFIG_FSL_CAAM 792 #define CONFIG_CMD_HASH 793 #define CONFIG_SHA_HW_ACCEL 794 #endif 795 796 /* 797 * Miscellaneous configurable options 798 */ 799 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 800 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 801 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 802 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 803 804 #if defined(CONFIG_CMD_KGDB) 805 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 806 #else 807 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 808 #endif 809 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 810 /* Print Buffer Size */ 811 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 812 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 813 814 /* 815 * For booting Linux, the board info and command line data 816 * have to be in the first 64 MB of memory, since this is 817 * the maximum mapped by the Linux kernel during initialization. 818 */ 819 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 820 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 821 822 #if defined(CONFIG_CMD_KGDB) 823 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 824 #endif 825 826 /* 827 * Environment Configuration 828 */ 829 830 #if defined(CONFIG_TSEC_ENET) 831 #define CONFIG_HAS_ETH0 832 #define CONFIG_HAS_ETH1 833 #define CONFIG_HAS_ETH2 834 #endif 835 836 #define CONFIG_ROOTPATH "/opt/nfsroot" 837 #define CONFIG_BOOTFILE "uImage" 838 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 839 840 /* default location for tftp and bootm */ 841 #define CONFIG_LOADADDR 1000000 842 843 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 844 845 #define CONFIG_BAUDRATE 115200 846 847 #define CONFIG_EXTRA_ENV_SETTINGS \ 848 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 849 "netdev=eth0\0" \ 850 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 851 "loadaddr=1000000\0" \ 852 "consoledev=ttyS0\0" \ 853 "ramdiskaddr=2000000\0" \ 854 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 855 "fdtaddr=1e00000\0" \ 856 "fdtfile=p1010rdb.dtb\0" \ 857 "bdev=sda1\0" \ 858 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 859 "othbootargs=ramdisk_size=600000\0" \ 860 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 861 "console=$consoledev,$baudrate $othbootargs; " \ 862 "usb start;" \ 863 "fatload usb 0:2 $loadaddr $bootfile;" \ 864 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 865 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 866 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 867 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 868 "console=$consoledev,$baudrate $othbootargs; " \ 869 "usb start;" \ 870 "ext2load usb 0:4 $loadaddr $bootfile;" \ 871 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 872 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 873 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 874 CONFIG_BOOTMODE 875 876 #if defined(CONFIG_P1010RDB_PA) 877 #define CONFIG_BOOTMODE \ 878 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 879 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 880 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 881 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 882 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 883 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 884 885 #elif defined(CONFIG_P1010RDB_PB) 886 #define CONFIG_BOOTMODE \ 887 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 888 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 889 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 890 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 891 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 892 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 893 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 894 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 895 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 896 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 897 #endif 898 899 #define CONFIG_RAMBOOTCOMMAND \ 900 "setenv bootargs root=/dev/ram rw " \ 901 "console=$consoledev,$baudrate $othbootargs; " \ 902 "tftp $ramdiskaddr $ramdiskfile;" \ 903 "tftp $loadaddr $bootfile;" \ 904 "tftp $fdtaddr $fdtfile;" \ 905 "bootm $loadaddr $ramdiskaddr $fdtaddr" 906 907 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 908 909 #include <asm/fsl_secure_boot.h> 910 911 #endif /* __CONFIG_H */ 912