1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_36BIT 15 #define CONFIG_PHYS_64BIT 16 #endif 17 18 #define CONFIG_P1010 19 #define CONFIG_E500 /* BOOKE e500 family */ 20 #include <asm/config_mpc85xx.h> 21 #define CONFIG_NAND_FSL_IFC 22 23 #ifdef CONFIG_SDCARD 24 #define CONFIG_RAMBOOT_SDCARD 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 27 #endif 28 29 #ifdef CONFIG_SPIFLASH 30 #define CONFIG_RAMBOOT_SPIFLASH 31 #define CONFIG_SYS_TEXT_BASE 0x11000000 32 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 33 #endif 34 35 #ifdef CONFIG_NAND 36 #define CONFIG_SPL 37 #define CONFIG_SPL_INIT_MINIMAL 38 #define CONFIG_SPL_SERIAL_SUPPORT 39 #define CONFIG_SPL_NAND_SUPPORT 40 #define CONFIG_SPL_NAND_MINIMAL 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 44 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 46 #define CONFIG_SPL_MAX_SIZE 8192 47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 48 #define CONFIG_SPL_RELOC_STACK 0x00100000 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #endif 55 56 57 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 58 #define CONFIG_RAMBOOT_NAND 59 #define CONFIG_SYS_TEXT_BASE 0x11000000 60 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 61 #endif 62 63 #ifndef CONFIG_SYS_TEXT_BASE 64 #define CONFIG_SYS_TEXT_BASE 0xeff80000 65 #endif 66 67 #ifndef CONFIG_RESET_VECTOR_ADDRESS 68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 69 #endif 70 71 #ifdef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 73 #else 74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 75 #endif 76 77 /* High Level Configuration Options */ 78 #define CONFIG_BOOKE /* BOOKE */ 79 #define CONFIG_E500 /* BOOKE e500 family */ 80 #define CONFIG_MPC85xx 81 #define CONFIG_FSL_IFC /* Enable IFC Support */ 82 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 83 84 #define CONFIG_PCI /* Enable PCI/PCIE */ 85 #if defined(CONFIG_PCI) 86 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 87 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 88 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 89 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 90 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 91 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 92 93 #define CONFIG_CMD_NET 94 #define CONFIG_CMD_PCI 95 96 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 97 98 /* 99 * PCI Windows 100 * Memory space is mapped 1-1, but I/O space must start from 0. 101 */ 102 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 103 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 104 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 105 #ifdef CONFIG_PHYS_64BIT 106 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 107 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 108 #else 109 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 110 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 111 #endif 112 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 113 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 114 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 115 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 118 #else 119 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 120 #endif 121 122 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 123 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 124 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 125 #ifdef CONFIG_PHYS_64BIT 126 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 127 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 128 #else 129 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 130 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 131 #endif 132 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 133 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 134 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 135 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 136 #ifdef CONFIG_PHYS_64BIT 137 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 138 #else 139 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 140 #endif 141 142 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 143 144 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 145 #define CONFIG_DOS_PARTITION 146 #endif 147 148 #define CONFIG_FSL_LAW /* Use common FSL init code */ 149 #define CONFIG_TSEC_ENET 150 #define CONFIG_ENV_OVERWRITE 151 152 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 153 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 154 155 #define CONFIG_MISC_INIT_R 156 #define CONFIG_HWCONFIG 157 /* 158 * These can be toggled for performance analysis, otherwise use default. 159 */ 160 #define CONFIG_L2_CACHE /* toggle L2 cache */ 161 #define CONFIG_BTB /* toggle branch predition */ 162 163 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 164 165 #define CONFIG_ENABLE_36BIT_PHYS 166 167 #ifdef CONFIG_PHYS_64BIT 168 #define CONFIG_ADDR_MAP 1 169 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 170 #endif 171 172 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 173 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 174 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 175 176 /* DDR Setup */ 177 #define CONFIG_FSL_DDR3 178 #define CONFIG_SYS_DDR_RAW_TIMING 179 #define CONFIG_DDR_SPD 180 #define CONFIG_SYS_SPD_BUS_NUM 1 181 #define SPD_EEPROM_ADDRESS 0x52 182 183 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 184 185 #ifndef __ASSEMBLY__ 186 extern unsigned long get_sdram_size(void); 187 #endif 188 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 189 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 190 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 191 192 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 193 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 194 195 /* DDR3 Controller Settings */ 196 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 197 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 198 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 199 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 200 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 201 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 202 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 203 204 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 205 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 206 #define CONFIG_SYS_DDR_RCW_1 0x00000000 207 #define CONFIG_SYS_DDR_RCW_2 0x00000000 208 #define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */ 209 #define CONFIG_SYS_DDR_CONTROL_2 0x04401010 210 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 211 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 212 213 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 214 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 215 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644 216 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 217 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 218 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 219 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 220 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 221 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 222 223 /* settings for DDR3 at 667MT/s */ 224 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 225 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 226 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 227 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 228 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 229 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 230 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 231 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 232 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 233 234 #define CONFIG_SYS_CCSRBAR 0xffe00000 235 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 236 237 /* Don't relocate CCSRBAR while in NAND_SPL */ 238 #ifdef CONFIG_SPL_BUILD 239 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 240 #endif 241 242 /* 243 * Memory map 244 * 245 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 246 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 247 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 248 * 249 * Localbus non-cacheable 250 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 251 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 252 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 253 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 254 */ 255 256 /* 257 * IFC Definitions 258 */ 259 /* NOR Flash on IFC */ 260 #ifdef CONFIG_SPL_BUILD 261 #define CONFIG_SYS_NO_FLASH 262 #endif 263 264 #define CONFIG_SYS_FLASH_BASE 0xee000000 265 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 266 267 #ifdef CONFIG_PHYS_64BIT 268 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 269 #else 270 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 271 #endif 272 273 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 274 CSPR_PORT_SIZE_16 | \ 275 CSPR_MSEL_NOR | \ 276 CSPR_V) 277 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 278 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 279 /* NOR Flash Timing Params */ 280 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 281 FTIM0_NOR_TEADC(0x5) | \ 282 FTIM0_NOR_TEAHC(0x5) 283 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 284 FTIM1_NOR_TRAD_NOR(0x0f) 285 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 286 FTIM2_NOR_TCH(0x4) | \ 287 FTIM2_NOR_TWP(0x1c) 288 #define CONFIG_SYS_NOR_FTIM3 0x0 289 290 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 291 #define CONFIG_SYS_FLASH_QUIET_TEST 292 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 293 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 294 295 #undef CONFIG_SYS_FLASH_CHECKSUM 296 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 297 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 298 299 /* CFI for NOR Flash */ 300 #define CONFIG_FLASH_CFI_DRIVER 301 #define CONFIG_SYS_FLASH_CFI 302 #define CONFIG_SYS_FLASH_EMPTY_INFO 303 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 304 305 /* NAND Flash on IFC */ 306 #define CONFIG_SYS_NAND_BASE 0xff800000 307 #ifdef CONFIG_PHYS_64BIT 308 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 309 #else 310 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 311 #endif 312 313 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 314 | CSPR_PORT_SIZE_8 \ 315 | CSPR_MSEL_NAND \ 316 | CSPR_V) 317 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 318 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 319 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 320 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 321 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 322 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 323 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 324 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 325 326 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 327 #define CONFIG_SYS_MAX_NAND_DEVICE 1 328 #define CONFIG_MTD_NAND_VERIFY_WRITE 329 #define CONFIG_CMD_NAND 330 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 331 332 /* NAND Flash Timing Params */ 333 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 334 FTIM0_NAND_TWP(0x0C) | \ 335 FTIM0_NAND_TWCHT(0x04) | \ 336 FTIM0_NAND_TWH(0x05) 337 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 338 FTIM1_NAND_TWBE(0x1d) | \ 339 FTIM1_NAND_TRR(0x07) | \ 340 FTIM1_NAND_TRP(0x0c) 341 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 342 FTIM2_NAND_TREH(0x05) | \ 343 FTIM2_NAND_TWHRE(0x0f) 344 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 345 346 #define CONFIG_SYS_NAND_DDR_LAW 11 347 348 /* Set up IFC registers for boot location NOR/NAND */ 349 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 357 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 358 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 359 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 360 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 361 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 362 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 363 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 364 #else 365 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 366 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 367 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 368 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 369 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 370 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 371 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 372 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 373 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 374 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 375 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 376 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 377 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 378 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 379 #endif 380 381 /* CPLD on IFC */ 382 #define CONFIG_SYS_CPLD_BASE 0xffb00000 383 384 #ifdef CONFIG_PHYS_64BIT 385 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 386 #else 387 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 388 #endif 389 390 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 391 | CSPR_PORT_SIZE_8 \ 392 | CSPR_MSEL_GPCM \ 393 | CSPR_V) 394 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 395 #define CONFIG_SYS_CSOR3 0x0 396 /* CPLD Timing parameters for IFC CS3 */ 397 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 398 FTIM0_GPCM_TEADC(0x0e) | \ 399 FTIM0_GPCM_TEAHC(0x0e)) 400 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 401 FTIM1_GPCM_TRAD(0x1f)) 402 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 403 FTIM2_GPCM_TCH(0x0) | \ 404 FTIM2_GPCM_TWP(0x1f)) 405 #define CONFIG_SYS_CS3_FTIM3 0x0 406 407 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 408 #define CONFIG_SYS_RAMBOOT 409 #define CONFIG_SYS_EXTRA_ENV_RELOC 410 #else 411 #undef CONFIG_SYS_RAMBOOT 412 #endif 413 414 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 415 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ 416 && !defined(CONFIG_SECURE_BOOT) 417 #define CONFIG_A003399_NOR_WORKAROUND 418 #endif 419 #endif 420 421 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 422 #define CONFIG_BOARD_EARLY_INIT_R 423 424 #define CONFIG_SYS_INIT_RAM_LOCK 425 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 426 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 427 428 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 429 - GENERATED_GBL_DATA_SIZE) 430 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 431 432 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 433 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 434 435 /* Serial Port */ 436 #define CONFIG_CONS_INDEX 1 437 #undef CONFIG_SERIAL_SOFTWARE_FIFO 438 #define CONFIG_SYS_NS16550 439 #define CONFIG_SYS_NS16550_SERIAL 440 #define CONFIG_SYS_NS16550_REG_SIZE 1 441 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 442 #ifdef CONFIG_SPL_BUILD 443 #define CONFIG_NS16550_MIN_FUNCTIONS 444 #endif 445 446 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 447 448 #define CONFIG_SYS_BAUDRATE_TABLE \ 449 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 450 451 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 452 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 453 454 /* Use the HUSH parser */ 455 #define CONFIG_SYS_HUSH_PARSER 456 457 /* 458 * Pass open firmware flat tree 459 */ 460 #define CONFIG_OF_LIBFDT 461 #define CONFIG_OF_BOARD_SETUP 462 #define CONFIG_OF_STDOUT_VIA_ALIAS 463 464 /* new uImage format support */ 465 #define CONFIG_FIT 466 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 467 468 /* I2C */ 469 #define CONFIG_SYS_I2C 470 #define CONFIG_SYS_I2C_FSL 471 #define CONFIG_SYS_FSL_I2C_SPEED 400000 472 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 473 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 474 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 475 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 476 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 477 #define I2C_PCA9557_ADDR1 0x18 478 #define I2C_PCA9557_BUS_NUM 0 479 480 /* I2C EEPROM */ 481 #undef CONFIG_ID_EEPROM 482 /* enable read and write access to EEPROM */ 483 #define CONFIG_CMD_EEPROM 484 #define CONFIG_SYS_I2C_MULTI_EEPROMS 485 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 486 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 487 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 488 489 /* RTC */ 490 #define CONFIG_RTC_PT7C4338 491 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 492 493 #define CONFIG_CMD_I2C 494 495 /* 496 * SPI interface will not be available in case of NAND boot SPI CS0 will be 497 * used for SLIC 498 */ 499 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 500 /* eSPI - Enhanced SPI */ 501 #define CONFIG_FSL_ESPI 502 #define CONFIG_SPI_FLASH 503 #define CONFIG_SPI_FLASH_SPANSION 504 #define CONFIG_CMD_SF 505 #define CONFIG_SF_DEFAULT_SPEED 10000000 506 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 507 #endif 508 509 #if defined(CONFIG_TSEC_ENET) 510 #define CONFIG_MII /* MII PHY management */ 511 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 512 #define CONFIG_TSEC1 1 513 #define CONFIG_TSEC1_NAME "eTSEC1" 514 #define CONFIG_TSEC2 1 515 #define CONFIG_TSEC2_NAME "eTSEC2" 516 #define CONFIG_TSEC3 1 517 #define CONFIG_TSEC3_NAME "eTSEC3" 518 519 #define TSEC1_PHY_ADDR 1 520 #define TSEC2_PHY_ADDR 0 521 #define TSEC3_PHY_ADDR 2 522 523 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 524 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 525 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 526 527 #define TSEC1_PHYIDX 0 528 #define TSEC2_PHYIDX 0 529 #define TSEC3_PHYIDX 0 530 531 #define CONFIG_ETHPRIME "eTSEC1" 532 533 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 534 535 /* TBI PHY configuration for SGMII mode */ 536 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 537 TBICR_PHY_RESET \ 538 | TBICR_ANEG_ENABLE \ 539 | TBICR_FULL_DUPLEX \ 540 | TBICR_SPEED1_SET \ 541 ) 542 543 #endif /* CONFIG_TSEC_ENET */ 544 545 546 /* SATA */ 547 #define CONFIG_FSL_SATA 548 #define CONFIG_FSL_SATA_V2 549 #define CONFIG_LIBATA 550 551 #ifdef CONFIG_FSL_SATA 552 #define CONFIG_SYS_SATA_MAX_DEVICE 2 553 #define CONFIG_SATA1 554 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 555 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 556 #define CONFIG_SATA2 557 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 558 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 559 560 #define CONFIG_CMD_SATA 561 #define CONFIG_LBA48 562 #endif /* #ifdef CONFIG_FSL_SATA */ 563 564 #define CONFIG_MMC 565 #ifdef CONFIG_MMC 566 #define CONFIG_CMD_MMC 567 #define CONFIG_DOS_PARTITION 568 #define CONFIG_FSL_ESDHC 569 #define CONFIG_GENERIC_MMC 570 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 571 #endif 572 573 #define CONFIG_HAS_FSL_DR_USB 574 575 #if defined(CONFIG_HAS_FSL_DR_USB) 576 #define CONFIG_USB_EHCI 577 578 #ifdef CONFIG_USB_EHCI 579 #define CONFIG_CMD_USB 580 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 581 #define CONFIG_USB_EHCI_FSL 582 #define CONFIG_USB_STORAGE 583 #endif 584 #endif 585 586 /* 587 * Environment 588 */ 589 #if defined(CONFIG_RAMBOOT_SDCARD) 590 #define CONFIG_ENV_IS_IN_MMC 591 #define CONFIG_FSL_FIXED_MMC_LOCATION 592 #define CONFIG_SYS_MMC_ENV_DEV 0 593 #define CONFIG_ENV_SIZE 0x2000 594 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 595 #define CONFIG_ENV_IS_IN_SPI_FLASH 596 #define CONFIG_ENV_SPI_BUS 0 597 #define CONFIG_ENV_SPI_CS 0 598 #define CONFIG_ENV_SPI_MAX_HZ 10000000 599 #define CONFIG_ENV_SPI_MODE 0 600 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 601 #define CONFIG_ENV_SECT_SIZE 0x10000 602 #define CONFIG_ENV_SIZE 0x2000 603 #elif defined(CONFIG_NAND) 604 #define CONFIG_ENV_IS_IN_NAND 605 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 606 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 607 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 608 #elif defined(CONFIG_SYS_RAMBOOT) 609 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 610 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 611 #define CONFIG_ENV_SIZE 0x2000 612 #else 613 #define CONFIG_ENV_IS_IN_FLASH 614 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 615 #define CONFIG_ENV_ADDR 0xfff80000 616 #else 617 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 618 #endif 619 #define CONFIG_ENV_SIZE 0x2000 620 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 621 #endif 622 623 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 624 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 625 626 /* 627 * Command line configuration. 628 */ 629 #include <config_cmd_default.h> 630 631 #define CONFIG_CMD_DATE 632 #define CONFIG_CMD_ERRATA 633 #define CONFIG_CMD_ELF 634 #define CONFIG_CMD_IRQ 635 #define CONFIG_CMD_MII 636 #define CONFIG_CMD_PING 637 #define CONFIG_CMD_SETEXPR 638 #define CONFIG_CMD_REGINFO 639 640 #undef CONFIG_WATCHDOG /* watchdog disabled */ 641 642 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 643 || defined(CONFIG_FSL_SATA) 644 #define CONFIG_CMD_EXT2 645 #define CONFIG_CMD_FAT 646 #define CONFIG_DOS_PARTITION 647 #endif 648 649 /* 650 * Miscellaneous configurable options 651 */ 652 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 653 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 654 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 655 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 656 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 657 658 #if defined(CONFIG_CMD_KGDB) 659 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 660 #else 661 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 662 #endif 663 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 664 /* Print Buffer Size */ 665 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 666 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 667 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ 668 669 /* 670 * Internal Definitions 671 * 672 * Boot Flags 673 */ 674 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 675 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 676 677 /* 678 * For booting Linux, the board info and command line data 679 * have to be in the first 64 MB of memory, since this is 680 * the maximum mapped by the Linux kernel during initialization. 681 */ 682 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 683 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 684 685 #if defined(CONFIG_CMD_KGDB) 686 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 687 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 688 #endif 689 690 /* 691 * Environment Configuration 692 */ 693 694 #if defined(CONFIG_TSEC_ENET) 695 #define CONFIG_HAS_ETH0 696 #define CONFIG_HAS_ETH1 697 #define CONFIG_HAS_ETH2 698 #endif 699 700 #define CONFIG_HOSTNAME P1010RDB 701 #define CONFIG_ROOTPATH "/opt/nfsroot" 702 #define CONFIG_BOOTFILE "uImage" 703 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 704 705 /* default location for tftp and bootm */ 706 #define CONFIG_LOADADDR 1000000 707 708 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 709 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 710 711 #define CONFIG_BAUDRATE 115200 712 713 #define CONFIG_EXTRA_ENV_SETTINGS \ 714 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 715 "netdev=eth0\0" \ 716 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 717 "loadaddr=1000000\0" \ 718 "consoledev=ttyS0\0" \ 719 "ramdiskaddr=2000000\0" \ 720 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 721 "fdtaddr=c00000\0" \ 722 "fdtfile=p1010rdb.dtb\0" \ 723 "bdev=sda1\0" \ 724 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 725 "othbootargs=ramdisk_size=600000\0" \ 726 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 727 "console=$consoledev,$baudrate $othbootargs; " \ 728 "usb start;" \ 729 "fatload usb 0:2 $loadaddr $bootfile;" \ 730 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 731 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 732 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 733 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 734 "console=$consoledev,$baudrate $othbootargs; " \ 735 "usb start;" \ 736 "ext2load usb 0:4 $loadaddr $bootfile;" \ 737 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 738 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 739 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 740 741 #define CONFIG_RAMBOOTCOMMAND \ 742 "setenv bootargs root=/dev/ram rw " \ 743 "console=$consoledev,$baudrate $othbootargs; " \ 744 "tftp $ramdiskaddr $ramdiskfile;" \ 745 "tftp $loadaddr $bootfile;" \ 746 "tftp $fdtaddr $fdtfile;" \ 747 "bootm $loadaddr $ramdiskaddr $fdtaddr" 748 749 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 750 751 #include <asm/fsl_secure_boot.h> 752 753 #endif /* __CONFIG_H */ 754