1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_P1010 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 #define CONFIG_NAND_FSL_IFC 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 23 #define CONFIG_SPL_SERIAL_SUPPORT 24 #define CONFIG_SPL_MMC_SUPPORT 25 #define CONFIG_SPL_MMC_MINIMAL 26 #define CONFIG_SPL_FLUSH_IMAGE 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 28 #define CONFIG_SPL_LIBGENERIC_SUPPORT 29 #define CONFIG_SPL_LIBCOMMON_SUPPORT 30 #define CONFIG_FSL_LAW /* Use common FSL init code */ 31 #define CONFIG_SYS_TEXT_BASE 0x11001000 32 #define CONFIG_SPL_TEXT_BASE 0xD0001000 33 #define CONFIG_SPL_PAD_TO 0x18000 34 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 35 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 36 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 37 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 38 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 40 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 41 #define CONFIG_SPL_MMC_BOOT 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SPL_COMMON_INIT_DDR 44 #endif 45 #endif 46 47 #ifdef CONFIG_SPIFLASH 48 #ifdef CONFIG_SECURE_BOOT 49 #define CONFIG_RAMBOOT_SPIFLASH 50 #define CONFIG_SYS_TEXT_BASE 0x11000000 51 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 52 #else 53 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 54 #define CONFIG_SPL_SERIAL_SUPPORT 55 #define CONFIG_SPL_SPI_SUPPORT 56 #define CONFIG_SPL_SPI_FLASH_SUPPORT 57 #define CONFIG_SPL_SPI_FLASH_MINIMAL 58 #define CONFIG_SPL_FLUSH_IMAGE 59 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 60 #define CONFIG_SPL_LIBGENERIC_SUPPORT 61 #define CONFIG_SPL_LIBCOMMON_SUPPORT 62 #define CONFIG_FSL_LAW /* Use common FSL init code */ 63 #define CONFIG_SYS_TEXT_BASE 0x11001000 64 #define CONFIG_SPL_TEXT_BASE 0xD0001000 65 #define CONFIG_SPL_PAD_TO 0x18000 66 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 72 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 73 #define CONFIG_SPL_SPI_BOOT 74 #ifdef CONFIG_SPL_BUILD 75 #define CONFIG_SPL_COMMON_INIT_DDR 76 #endif 77 #endif 78 #endif 79 80 #ifdef CONFIG_NAND 81 #ifdef CONFIG_SECURE_BOOT 82 #define CONFIG_SPL_INIT_MINIMAL 83 #define CONFIG_SPL_SERIAL_SUPPORT 84 #define CONFIG_SPL_NAND_SUPPORT 85 #define CONFIG_SPL_NAND_BOOT 86 #define CONFIG_SPL_FLUSH_IMAGE 87 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 88 89 #define CONFIG_SYS_TEXT_BASE 0x00201000 90 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 91 #define CONFIG_SPL_MAX_SIZE 8192 92 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 93 #define CONFIG_SPL_RELOC_STACK 0x00100000 94 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 95 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 96 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 97 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 98 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 99 #else 100 #ifdef CONFIG_TPL_BUILD 101 #define CONFIG_SPL_NAND_BOOT 102 #define CONFIG_SPL_FLUSH_IMAGE 103 #define CONFIG_SPL_NAND_INIT 104 #define CONFIG_TPL_SERIAL_SUPPORT 105 #define CONFIG_TPL_LIBGENERIC_SUPPORT 106 #define CONFIG_TPL_LIBCOMMON_SUPPORT 107 #define CONFIG_TPL_NAND_SUPPORT 108 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 109 #define CONFIG_SPL_COMMON_INIT_DDR 110 #define CONFIG_SPL_MAX_SIZE (128 << 10) 111 #define CONFIG_SPL_TEXT_BASE 0xD0001000 112 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 113 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 114 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 115 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 116 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 117 #elif defined(CONFIG_SPL_BUILD) 118 #define CONFIG_SPL_INIT_MINIMAL 119 #define CONFIG_SPL_SERIAL_SUPPORT 120 #define CONFIG_SPL_NAND_SUPPORT 121 #define CONFIG_SPL_NAND_MINIMAL 122 #define CONFIG_SPL_FLUSH_IMAGE 123 #define CONFIG_SPL_TEXT_BASE 0xff800000 124 #define CONFIG_SPL_MAX_SIZE 8192 125 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 126 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 127 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 128 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 129 #endif 130 #define CONFIG_SPL_PAD_TO 0x20000 131 #define CONFIG_TPL_PAD_TO 0x20000 132 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 133 #define CONFIG_SYS_TEXT_BASE 0x11001000 134 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 135 #endif 136 #endif 137 138 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 139 #define CONFIG_RAMBOOT_NAND 140 #define CONFIG_SYS_TEXT_BASE 0x11000000 141 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 142 #endif 143 144 #ifndef CONFIG_SYS_TEXT_BASE 145 #define CONFIG_SYS_TEXT_BASE 0xeff40000 146 #endif 147 148 #ifndef CONFIG_RESET_VECTOR_ADDRESS 149 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 150 #endif 151 152 #ifdef CONFIG_SPL_BUILD 153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 154 #else 155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 156 #endif 157 158 /* High Level Configuration Options */ 159 #define CONFIG_BOOKE /* BOOKE */ 160 #define CONFIG_E500 /* BOOKE e500 family */ 161 #define CONFIG_FSL_IFC /* Enable IFC Support */ 162 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 163 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 164 165 #define CONFIG_PCI /* Enable PCI/PCIE */ 166 #if defined(CONFIG_PCI) 167 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 168 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 169 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 170 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 171 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 172 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 173 174 #define CONFIG_CMD_PCI 175 176 /* 177 * PCI Windows 178 * Memory space is mapped 1-1, but I/O space must start from 0. 179 */ 180 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 181 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 182 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 183 #ifdef CONFIG_PHYS_64BIT 184 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 185 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 186 #else 187 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 188 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 189 #endif 190 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 191 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 192 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 193 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 194 #ifdef CONFIG_PHYS_64BIT 195 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 196 #else 197 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 198 #endif 199 200 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 201 #if defined(CONFIG_P1010RDB_PA) 202 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 203 #elif defined(CONFIG_P1010RDB_PB) 204 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 205 #endif 206 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 207 #ifdef CONFIG_PHYS_64BIT 208 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 209 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 210 #else 211 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 212 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 213 #endif 214 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 215 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 216 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 217 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 218 #ifdef CONFIG_PHYS_64BIT 219 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 220 #else 221 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 222 #endif 223 224 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 225 226 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 227 #define CONFIG_DOS_PARTITION 228 #endif 229 230 #define CONFIG_FSL_LAW /* Use common FSL init code */ 231 #define CONFIG_TSEC_ENET 232 #define CONFIG_ENV_OVERWRITE 233 234 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 235 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 236 237 #define CONFIG_MISC_INIT_R 238 #define CONFIG_HWCONFIG 239 /* 240 * These can be toggled for performance analysis, otherwise use default. 241 */ 242 #define CONFIG_L2_CACHE /* toggle L2 cache */ 243 #define CONFIG_BTB /* toggle branch predition */ 244 245 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 246 247 #define CONFIG_ENABLE_36BIT_PHYS 248 249 #ifdef CONFIG_PHYS_64BIT 250 #define CONFIG_ADDR_MAP 1 251 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 252 #endif 253 254 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 255 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 256 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 257 258 /* DDR Setup */ 259 #define CONFIG_SYS_FSL_DDR3 260 #define CONFIG_SYS_DDR_RAW_TIMING 261 #define CONFIG_DDR_SPD 262 #define CONFIG_SYS_SPD_BUS_NUM 1 263 #define SPD_EEPROM_ADDRESS 0x52 264 265 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 266 267 #ifndef __ASSEMBLY__ 268 extern unsigned long get_sdram_size(void); 269 #endif 270 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 271 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 272 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 273 274 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 275 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 276 277 /* DDR3 Controller Settings */ 278 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 279 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 280 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 281 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 282 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 283 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 284 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 285 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 286 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 287 #define CONFIG_SYS_DDR_RCW_1 0x00000000 288 #define CONFIG_SYS_DDR_RCW_2 0x00000000 289 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 290 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 291 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 292 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 293 294 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 295 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 296 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 297 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 298 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 299 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 300 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 301 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 302 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 303 304 /* settings for DDR3 at 667MT/s */ 305 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 306 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 307 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 308 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 309 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 310 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 311 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 312 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 313 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 314 315 #define CONFIG_SYS_CCSRBAR 0xffe00000 316 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 317 318 /* Don't relocate CCSRBAR while in NAND_SPL */ 319 #ifdef CONFIG_SPL_BUILD 320 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 321 #endif 322 323 /* 324 * Memory map 325 * 326 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 327 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 328 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 329 * 330 * Localbus non-cacheable 331 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 332 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 333 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 334 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 335 */ 336 337 /* 338 * IFC Definitions 339 */ 340 /* NOR Flash on IFC */ 341 #ifdef CONFIG_SPL_BUILD 342 #define CONFIG_SYS_NO_FLASH 343 #endif 344 345 #define CONFIG_SYS_FLASH_BASE 0xee000000 346 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 347 348 #ifdef CONFIG_PHYS_64BIT 349 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 350 #else 351 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 352 #endif 353 354 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 355 CSPR_PORT_SIZE_16 | \ 356 CSPR_MSEL_NOR | \ 357 CSPR_V) 358 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 359 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 360 /* NOR Flash Timing Params */ 361 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 362 FTIM0_NOR_TEADC(0x5) | \ 363 FTIM0_NOR_TEAHC(0x5) 364 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 365 FTIM1_NOR_TRAD_NOR(0x0f) 366 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 367 FTIM2_NOR_TCH(0x4) | \ 368 FTIM2_NOR_TWP(0x1c) 369 #define CONFIG_SYS_NOR_FTIM3 0x0 370 371 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 372 #define CONFIG_SYS_FLASH_QUIET_TEST 373 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 374 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 375 376 #undef CONFIG_SYS_FLASH_CHECKSUM 377 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 378 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 379 380 /* CFI for NOR Flash */ 381 #define CONFIG_FLASH_CFI_DRIVER 382 #define CONFIG_SYS_FLASH_CFI 383 #define CONFIG_SYS_FLASH_EMPTY_INFO 384 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 385 386 /* NAND Flash on IFC */ 387 #define CONFIG_SYS_NAND_BASE 0xff800000 388 #ifdef CONFIG_PHYS_64BIT 389 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 390 #else 391 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 392 #endif 393 394 #define CONFIG_MTD_DEVICE 395 #define CONFIG_MTD_PARTITION 396 #define CONFIG_CMD_MTDPARTS 397 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 398 #define MTDPARTS_DEFAULT \ 399 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 400 401 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 402 | CSPR_PORT_SIZE_8 \ 403 | CSPR_MSEL_NAND \ 404 | CSPR_V) 405 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 406 407 #if defined(CONFIG_P1010RDB_PA) 408 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 409 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 410 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 411 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 412 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 413 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 414 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 415 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 416 417 #elif defined(CONFIG_P1010RDB_PB) 418 #define CONFIG_SYS_NAND_ONFI_DETECTION 419 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 420 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 421 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 422 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 423 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 424 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 425 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 426 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 427 #endif 428 429 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 430 #define CONFIG_SYS_MAX_NAND_DEVICE 1 431 #define CONFIG_CMD_NAND 432 433 #if defined(CONFIG_P1010RDB_PA) 434 /* NAND Flash Timing Params */ 435 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 436 FTIM0_NAND_TWP(0x0C) | \ 437 FTIM0_NAND_TWCHT(0x04) | \ 438 FTIM0_NAND_TWH(0x05) 439 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 440 FTIM1_NAND_TWBE(0x1d) | \ 441 FTIM1_NAND_TRR(0x07) | \ 442 FTIM1_NAND_TRP(0x0c) 443 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 444 FTIM2_NAND_TREH(0x05) | \ 445 FTIM2_NAND_TWHRE(0x0f) 446 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 447 448 #elif defined(CONFIG_P1010RDB_PB) 449 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 450 /* ONFI NAND Flash mode0 Timing Params */ 451 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 452 FTIM0_NAND_TWP(0x18) | \ 453 FTIM0_NAND_TWCHT(0x07) | \ 454 FTIM0_NAND_TWH(0x0a)) 455 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 456 FTIM1_NAND_TWBE(0x39) | \ 457 FTIM1_NAND_TRR(0x0e) | \ 458 FTIM1_NAND_TRP(0x18)) 459 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 460 FTIM2_NAND_TREH(0x0a) | \ 461 FTIM2_NAND_TWHRE(0x1e)) 462 #define CONFIG_SYS_NAND_FTIM3 0x0 463 #endif 464 465 #define CONFIG_SYS_NAND_DDR_LAW 11 466 467 /* Set up IFC registers for boot location NOR/NAND */ 468 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 469 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 470 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 471 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 472 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 473 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 474 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 475 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 476 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 477 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 478 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 479 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 480 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 481 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 482 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 483 #else 484 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 485 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 486 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 487 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 488 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 489 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 490 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 491 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 492 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 493 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 494 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 495 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 496 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 497 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 498 #endif 499 500 /* CPLD on IFC */ 501 #define CONFIG_SYS_CPLD_BASE 0xffb00000 502 503 #ifdef CONFIG_PHYS_64BIT 504 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 505 #else 506 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 507 #endif 508 509 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 510 | CSPR_PORT_SIZE_8 \ 511 | CSPR_MSEL_GPCM \ 512 | CSPR_V) 513 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 514 #define CONFIG_SYS_CSOR3 0x0 515 /* CPLD Timing parameters for IFC CS3 */ 516 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 517 FTIM0_GPCM_TEADC(0x0e) | \ 518 FTIM0_GPCM_TEAHC(0x0e)) 519 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 520 FTIM1_GPCM_TRAD(0x1f)) 521 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 522 FTIM2_GPCM_TCH(0x8) | \ 523 FTIM2_GPCM_TWP(0x1f)) 524 #define CONFIG_SYS_CS3_FTIM3 0x0 525 526 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 527 defined(CONFIG_RAMBOOT_NAND) 528 #define CONFIG_SYS_RAMBOOT 529 #define CONFIG_SYS_EXTRA_ENV_RELOC 530 #else 531 #undef CONFIG_SYS_RAMBOOT 532 #endif 533 534 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 535 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 536 #define CONFIG_A003399_NOR_WORKAROUND 537 #endif 538 #endif 539 540 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 541 #define CONFIG_BOARD_EARLY_INIT_R 542 543 #define CONFIG_SYS_INIT_RAM_LOCK 544 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 545 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 546 547 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 548 - GENERATED_GBL_DATA_SIZE) 549 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 550 551 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 552 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 553 554 /* 555 * Config the L2 Cache as L2 SRAM 556 */ 557 #if defined(CONFIG_SPL_BUILD) 558 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 559 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 560 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 561 #define CONFIG_SYS_L2_SIZE (256 << 10) 562 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 563 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 564 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 565 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 566 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 567 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 568 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 569 #elif defined(CONFIG_NAND) 570 #ifdef CONFIG_TPL_BUILD 571 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 572 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 573 #define CONFIG_SYS_L2_SIZE (256 << 10) 574 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 575 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 576 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 577 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 578 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 579 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 580 #else 581 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 582 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 583 #define CONFIG_SYS_L2_SIZE (256 << 10) 584 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 585 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 586 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 587 #endif 588 #endif 589 #endif 590 591 /* Serial Port */ 592 #define CONFIG_CONS_INDEX 1 593 #undef CONFIG_SERIAL_SOFTWARE_FIFO 594 #define CONFIG_SYS_NS16550_SERIAL 595 #define CONFIG_SYS_NS16550_REG_SIZE 1 596 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 597 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 598 #define CONFIG_NS16550_MIN_FUNCTIONS 599 #endif 600 601 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 602 603 #define CONFIG_SYS_BAUDRATE_TABLE \ 604 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 605 606 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 607 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 608 609 /* I2C */ 610 #define CONFIG_SYS_I2C 611 #define CONFIG_SYS_I2C_FSL 612 #define CONFIG_SYS_FSL_I2C_SPEED 400000 613 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 614 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 615 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 616 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 617 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 618 #define I2C_PCA9557_ADDR1 0x18 619 #define I2C_PCA9557_ADDR2 0x19 620 #define I2C_PCA9557_BUS_NUM 0 621 622 /* I2C EEPROM */ 623 #if defined(CONFIG_P1010RDB_PB) 624 #define CONFIG_ID_EEPROM 625 #ifdef CONFIG_ID_EEPROM 626 #define CONFIG_SYS_I2C_EEPROM_NXID 627 #endif 628 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 629 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 630 #define CONFIG_SYS_EEPROM_BUS_NUM 0 631 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 632 #endif 633 /* enable read and write access to EEPROM */ 634 #define CONFIG_CMD_EEPROM 635 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 636 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 637 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 638 639 /* RTC */ 640 #define CONFIG_RTC_PT7C4338 641 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 642 643 /* 644 * SPI interface will not be available in case of NAND boot SPI CS0 will be 645 * used for SLIC 646 */ 647 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 648 /* eSPI - Enhanced SPI */ 649 #define CONFIG_SF_DEFAULT_SPEED 10000000 650 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 651 #endif 652 653 #if defined(CONFIG_TSEC_ENET) 654 #define CONFIG_MII /* MII PHY management */ 655 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 656 #define CONFIG_TSEC1 1 657 #define CONFIG_TSEC1_NAME "eTSEC1" 658 #define CONFIG_TSEC2 1 659 #define CONFIG_TSEC2_NAME "eTSEC2" 660 #define CONFIG_TSEC3 1 661 #define CONFIG_TSEC3_NAME "eTSEC3" 662 663 #define TSEC1_PHY_ADDR 1 664 #define TSEC2_PHY_ADDR 0 665 #define TSEC3_PHY_ADDR 2 666 667 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 668 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 669 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 670 671 #define TSEC1_PHYIDX 0 672 #define TSEC2_PHYIDX 0 673 #define TSEC3_PHYIDX 0 674 675 #define CONFIG_ETHPRIME "eTSEC1" 676 677 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 678 679 /* TBI PHY configuration for SGMII mode */ 680 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 681 TBICR_PHY_RESET \ 682 | TBICR_ANEG_ENABLE \ 683 | TBICR_FULL_DUPLEX \ 684 | TBICR_SPEED1_SET \ 685 ) 686 687 #endif /* CONFIG_TSEC_ENET */ 688 689 /* SATA */ 690 #define CONFIG_FSL_SATA 691 #define CONFIG_FSL_SATA_V2 692 #define CONFIG_LIBATA 693 694 #ifdef CONFIG_FSL_SATA 695 #define CONFIG_SYS_SATA_MAX_DEVICE 2 696 #define CONFIG_SATA1 697 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 698 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 699 #define CONFIG_SATA2 700 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 701 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 702 703 #define CONFIG_CMD_SATA 704 #define CONFIG_LBA48 705 #endif /* #ifdef CONFIG_FSL_SATA */ 706 707 #define CONFIG_MMC 708 #ifdef CONFIG_MMC 709 #define CONFIG_DOS_PARTITION 710 #define CONFIG_FSL_ESDHC 711 #define CONFIG_GENERIC_MMC 712 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 713 #endif 714 715 #define CONFIG_HAS_FSL_DR_USB 716 717 #if defined(CONFIG_HAS_FSL_DR_USB) 718 #define CONFIG_USB_EHCI 719 720 #ifdef CONFIG_USB_EHCI 721 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 722 #define CONFIG_USB_EHCI_FSL 723 #endif 724 #endif 725 726 /* 727 * Environment 728 */ 729 #if defined(CONFIG_SDCARD) 730 #define CONFIG_ENV_IS_IN_MMC 731 #define CONFIG_FSL_FIXED_MMC_LOCATION 732 #define CONFIG_SYS_MMC_ENV_DEV 0 733 #define CONFIG_ENV_SIZE 0x2000 734 #elif defined(CONFIG_SPIFLASH) 735 #define CONFIG_ENV_IS_IN_SPI_FLASH 736 #define CONFIG_ENV_SPI_BUS 0 737 #define CONFIG_ENV_SPI_CS 0 738 #define CONFIG_ENV_SPI_MAX_HZ 10000000 739 #define CONFIG_ENV_SPI_MODE 0 740 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 741 #define CONFIG_ENV_SECT_SIZE 0x10000 742 #define CONFIG_ENV_SIZE 0x2000 743 #elif defined(CONFIG_NAND) 744 #define CONFIG_ENV_IS_IN_NAND 745 #ifdef CONFIG_TPL_BUILD 746 #define CONFIG_ENV_SIZE 0x2000 747 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 748 #else 749 #if defined(CONFIG_P1010RDB_PA) 750 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 751 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 752 #elif defined(CONFIG_P1010RDB_PB) 753 #define CONFIG_ENV_SIZE (16 * 1024) 754 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 755 #endif 756 #endif 757 #define CONFIG_ENV_OFFSET (1024 * 1024) 758 #elif defined(CONFIG_SYS_RAMBOOT) 759 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 760 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 761 #define CONFIG_ENV_SIZE 0x2000 762 #else 763 #define CONFIG_ENV_IS_IN_FLASH 764 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 765 #define CONFIG_ENV_SIZE 0x2000 766 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 767 #endif 768 769 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 770 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 771 772 /* 773 * Command line configuration. 774 */ 775 #define CONFIG_CMD_DATE 776 #define CONFIG_CMD_ERRATA 777 #define CONFIG_CMD_IRQ 778 #define CONFIG_CMD_REGINFO 779 780 #undef CONFIG_WATCHDOG /* watchdog disabled */ 781 782 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 783 || defined(CONFIG_FSL_SATA) 784 #define CONFIG_DOS_PARTITION 785 #endif 786 787 /* Hash command with SHA acceleration supported in hardware */ 788 #ifdef CONFIG_FSL_CAAM 789 #define CONFIG_CMD_HASH 790 #define CONFIG_SHA_HW_ACCEL 791 #endif 792 793 /* 794 * Miscellaneous configurable options 795 */ 796 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 797 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 798 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 799 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 800 801 #if defined(CONFIG_CMD_KGDB) 802 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 803 #else 804 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 805 #endif 806 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 807 /* Print Buffer Size */ 808 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 809 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 810 811 /* 812 * For booting Linux, the board info and command line data 813 * have to be in the first 64 MB of memory, since this is 814 * the maximum mapped by the Linux kernel during initialization. 815 */ 816 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 817 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 818 819 #if defined(CONFIG_CMD_KGDB) 820 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 821 #endif 822 823 /* 824 * Environment Configuration 825 */ 826 827 #if defined(CONFIG_TSEC_ENET) 828 #define CONFIG_HAS_ETH0 829 #define CONFIG_HAS_ETH1 830 #define CONFIG_HAS_ETH2 831 #endif 832 833 #define CONFIG_ROOTPATH "/opt/nfsroot" 834 #define CONFIG_BOOTFILE "uImage" 835 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 836 837 /* default location for tftp and bootm */ 838 #define CONFIG_LOADADDR 1000000 839 840 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 841 842 #define CONFIG_BAUDRATE 115200 843 844 #define CONFIG_EXTRA_ENV_SETTINGS \ 845 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 846 "netdev=eth0\0" \ 847 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 848 "loadaddr=1000000\0" \ 849 "consoledev=ttyS0\0" \ 850 "ramdiskaddr=2000000\0" \ 851 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 852 "fdtaddr=1e00000\0" \ 853 "fdtfile=p1010rdb.dtb\0" \ 854 "bdev=sda1\0" \ 855 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 856 "othbootargs=ramdisk_size=600000\0" \ 857 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 858 "console=$consoledev,$baudrate $othbootargs; " \ 859 "usb start;" \ 860 "fatload usb 0:2 $loadaddr $bootfile;" \ 861 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 862 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 863 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 864 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 865 "console=$consoledev,$baudrate $othbootargs; " \ 866 "usb start;" \ 867 "ext2load usb 0:4 $loadaddr $bootfile;" \ 868 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 869 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 870 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 871 CONFIG_BOOTMODE 872 873 #if defined(CONFIG_P1010RDB_PA) 874 #define CONFIG_BOOTMODE \ 875 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 876 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 877 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 878 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 879 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 880 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 881 882 #elif defined(CONFIG_P1010RDB_PB) 883 #define CONFIG_BOOTMODE \ 884 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 885 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 886 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 887 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 888 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 889 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 890 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 891 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 892 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 893 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 894 #endif 895 896 #define CONFIG_RAMBOOTCOMMAND \ 897 "setenv bootargs root=/dev/ram rw " \ 898 "console=$consoledev,$baudrate $othbootargs; " \ 899 "tftp $ramdiskaddr $ramdiskfile;" \ 900 "tftp $loadaddr $bootfile;" \ 901 "tftp $fdtaddr $fdtfile;" \ 902 "bootm $loadaddr $ramdiskaddr $fdtaddr" 903 904 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 905 906 #include <asm/fsl_secure_boot.h> 907 908 #endif /* __CONFIG_H */ 909