1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * P010 RDB board configuration file 25 */ 26 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #ifdef CONFIG_36BIT 31 #define CONFIG_PHYS_64BIT 32 #endif 33 34 #define CONFIG_P1010 35 #define CONFIG_E500 /* BOOKE e500 family */ 36 #include <asm/config_mpc85xx.h> 37 #define CONFIG_NAND_FSL_IFC 38 39 #ifdef CONFIG_SDCARD 40 #define CONFIG_RAMBOOT_SDCARD 41 #define CONFIG_SYS_TEXT_BASE 0x11000000 42 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 43 #endif 44 45 #ifdef CONFIG_SPIFLASH 46 #define CONFIG_RAMBOOT_SPIFLASH 47 #define CONFIG_SYS_TEXT_BASE 0x11000000 48 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 49 #endif 50 51 #ifdef CONFIG_NAND /* NAND Boot */ 52 #define CONFIG_RAMBOOT_NAND 53 #define CONFIG_NAND_U_BOOT 54 #define CONFIG_SYS_TEXT_BASE_SPL 0xff800000 55 #ifdef CONFIG_NAND_SPL 56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL 57 #else 58 #define CONFIG_SYS_TEXT_BASE 0x11001000 59 #endif /* CONFIG_NAND_SPL */ 60 #endif 61 62 63 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 64 #define CONFIG_RAMBOOT_NAND 65 #define CONFIG_SYS_TEXT_BASE 0x11000000 66 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 67 #endif 68 69 #ifndef CONFIG_SYS_TEXT_BASE 70 #define CONFIG_SYS_TEXT_BASE 0xeff80000 71 #endif 72 73 #ifndef CONFIG_RESET_VECTOR_ADDRESS 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 75 #endif 76 77 #ifndef CONFIG_SYS_MONITOR_BASE 78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 79 #endif 80 81 /* High Level Configuration Options */ 82 #define CONFIG_BOOKE /* BOOKE */ 83 #define CONFIG_E500 /* BOOKE e500 family */ 84 #define CONFIG_MPC85xx 85 #define CONFIG_FSL_IFC /* Enable IFC Support */ 86 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 87 88 #define CONFIG_PCI /* Enable PCI/PCIE */ 89 #if defined(CONFIG_PCI) 90 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 91 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 92 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 93 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 94 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 95 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 96 97 #define CONFIG_CMD_NET 98 #define CONFIG_CMD_PCI 99 100 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 101 102 /* 103 * PCI Windows 104 * Memory space is mapped 1-1, but I/O space must start from 0. 105 */ 106 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 107 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 108 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 109 #ifdef CONFIG_PHYS_64BIT 110 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 111 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 112 #else 113 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 114 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 115 #endif 116 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 117 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 118 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 119 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 120 #ifdef CONFIG_PHYS_64BIT 121 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 122 #else 123 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 124 #endif 125 126 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 127 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 128 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 131 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 132 #else 133 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 134 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 135 #endif 136 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 137 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 138 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 139 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 142 #else 143 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 144 #endif 145 146 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 147 148 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 149 #define CONFIG_DOS_PARTITION 150 #endif 151 152 #define CONFIG_FSL_LAW /* Use common FSL init code */ 153 #define CONFIG_TSEC_ENET 154 #define CONFIG_ENV_OVERWRITE 155 156 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 157 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 158 159 #ifndef CONFIG_SDCARD 160 #define CONFIG_MISC_INIT_R 161 #endif 162 163 #define CONFIG_HWCONFIG 164 /* 165 * These can be toggled for performance analysis, otherwise use default. 166 */ 167 #define CONFIG_L2_CACHE /* toggle L2 cache */ 168 #define CONFIG_BTB /* toggle branch predition */ 169 170 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 171 172 #define CONFIG_ENABLE_36BIT_PHYS 173 174 #ifdef CONFIG_PHYS_64BIT 175 #define CONFIG_ADDR_MAP 1 176 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 177 #endif 178 179 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 180 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 181 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 182 183 /* DDR Setup */ 184 #define CONFIG_FSL_DDR3 185 #define CONFIG_SYS_DDR_RAW_TIMING 186 #define CONFIG_DDR_SPD 187 #define CONFIG_SYS_SPD_BUS_NUM 1 188 #define SPD_EEPROM_ADDRESS 0x52 189 190 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 191 192 #ifndef __ASSEMBLY__ 193 extern unsigned long get_sdram_size(void); 194 #endif 195 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 196 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 197 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 198 199 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 200 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 201 202 /* DDR3 Controller Settings */ 203 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 204 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 205 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 206 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 207 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 208 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 209 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 210 211 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 212 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 213 #define CONFIG_SYS_DDR_RCW_1 0x00000000 214 #define CONFIG_SYS_DDR_RCW_2 0x00000000 215 #define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */ 216 #define CONFIG_SYS_DDR_CONTROL_2 0x04401010 217 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 218 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 219 220 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 221 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 222 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644 223 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 224 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 225 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 226 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 227 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 228 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 229 230 /* settings for DDR3 at 667MT/s */ 231 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 232 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 233 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 234 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 235 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 236 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 237 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 238 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 239 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 240 241 #define CONFIG_SYS_CCSRBAR 0xffe00000 242 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 243 244 /* Don't relocate CCSRBAR while in NAND_SPL */ 245 #ifdef CONFIG_NAND_SPL 246 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 247 #endif 248 249 /* 250 * Memory map 251 * 252 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 253 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 254 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 255 * 256 * Localbus non-cacheable 257 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 258 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 259 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 260 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 261 */ 262 263 /* In case of SD card boot, IFC interface is not available because of muxing */ 264 #ifdef CONFIG_SDCARD 265 #define CONFIG_SYS_NO_FLASH 266 #else 267 /* 268 * IFC Definitions 269 */ 270 /* NOR Flash on IFC */ 271 #define CONFIG_SYS_FLASH_BASE 0xee000000 272 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 273 274 #ifdef CONFIG_PHYS_64BIT 275 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 276 #else 277 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 278 #endif 279 280 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 281 CSPR_PORT_SIZE_16 | \ 282 CSPR_MSEL_NOR | \ 283 CSPR_V) 284 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 285 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 286 /* NOR Flash Timing Params */ 287 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 288 FTIM0_NOR_TEADC(0x5) | \ 289 FTIM0_NOR_TEAHC(0x5) 290 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 291 FTIM1_NOR_TRAD_NOR(0x0f) 292 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 293 FTIM2_NOR_TCH(0x4) | \ 294 FTIM2_NOR_TWP(0x1c) 295 #define CONFIG_SYS_NOR_FTIM3 0x0 296 297 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 298 #define CONFIG_SYS_FLASH_QUIET_TEST 299 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 300 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 301 302 #undef CONFIG_SYS_FLASH_CHECKSUM 303 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 304 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 305 306 /* CFI for NOR Flash */ 307 #define CONFIG_FLASH_CFI_DRIVER 308 #define CONFIG_SYS_FLASH_CFI 309 #define CONFIG_SYS_FLASH_EMPTY_INFO 310 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 311 312 /* NAND Flash on IFC */ 313 #define CONFIG_SYS_NAND_BASE 0xff800000 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 316 #else 317 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 318 #endif 319 320 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 321 | CSPR_PORT_SIZE_8 \ 322 | CSPR_MSEL_NAND \ 323 | CSPR_V) 324 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 325 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 326 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 327 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 328 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 329 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 330 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 331 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 332 333 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 334 #define CONFIG_SYS_MAX_NAND_DEVICE 1 335 #define CONFIG_MTD_NAND_VERIFY_WRITE 336 #define CONFIG_CMD_NAND 337 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 338 339 /* NAND Flash Timing Params */ 340 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 341 FTIM0_NAND_TWP(0x0C) | \ 342 FTIM0_NAND_TWCHT(0x04) | \ 343 FTIM0_NAND_TWH(0x05) 344 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 345 FTIM1_NAND_TWBE(0x1d) | \ 346 FTIM1_NAND_TRR(0x07) | \ 347 FTIM1_NAND_TRP(0x0c) 348 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 349 FTIM2_NAND_TREH(0x05) | \ 350 FTIM2_NAND_TWHRE(0x0f) 351 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 352 353 #define CONFIG_SYS_NAND_DDR_LAW 11 354 355 /* Set up IFC registers for boot location NOR/NAND */ 356 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT) 357 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 358 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 359 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 360 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 361 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 362 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 363 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 364 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 365 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 366 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 367 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 368 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 369 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 370 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 371 #else 372 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 373 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 374 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 375 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 376 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 377 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 378 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 379 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 380 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 381 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 382 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 383 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 384 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 385 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 386 #endif 387 388 /* NAND boot: 8K NAND loader config */ 389 #define CONFIG_SYS_NAND_SPL_SIZE 0x2000 390 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 391 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) 392 #define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 393 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 394 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000 395 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 396 397 /* CPLD on IFC */ 398 #define CONFIG_SYS_CPLD_BASE 0xffb00000 399 400 #ifdef CONFIG_PHYS_64BIT 401 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 402 #else 403 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 404 #endif 405 406 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 407 | CSPR_PORT_SIZE_8 \ 408 | CSPR_MSEL_GPCM \ 409 | CSPR_V) 410 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 411 #define CONFIG_SYS_CSOR3 0x0 412 /* CPLD Timing parameters for IFC CS3 */ 413 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 414 FTIM0_GPCM_TEADC(0x0e) | \ 415 FTIM0_GPCM_TEAHC(0x0e)) 416 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 417 FTIM1_GPCM_TRAD(0x1f)) 418 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 419 FTIM2_GPCM_TCH(0x0) | \ 420 FTIM2_GPCM_TWP(0x1f)) 421 #define CONFIG_SYS_CS3_FTIM3 0x0 422 #endif /* CONFIG_SDCARD */ 423 424 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 425 defined(CONFIG_RAMBOOT_NAND) 426 #define CONFIG_SYS_RAMBOOT 427 #define CONFIG_SYS_EXTRA_ENV_RELOC 428 #else 429 #undef CONFIG_SYS_RAMBOOT 430 #endif 431 432 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 433 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ 434 && !defined(CONFIG_SECURE_BOOT) 435 #define CONFIG_A003399_NOR_WORKAROUND 436 #endif 437 #endif 438 439 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 440 #define CONFIG_BOARD_EARLY_INIT_R 441 442 #define CONFIG_SYS_INIT_RAM_LOCK 443 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 444 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 445 446 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 447 - GENERATED_GBL_DATA_SIZE) 448 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 449 450 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 451 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 452 453 /* Serial Port */ 454 #define CONFIG_CONS_INDEX 1 455 #undef CONFIG_SERIAL_SOFTWARE_FIFO 456 #define CONFIG_SYS_NS16550 457 #define CONFIG_SYS_NS16550_SERIAL 458 #define CONFIG_SYS_NS16550_REG_SIZE 1 459 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 460 #ifdef CONFIG_NAND_SPL 461 #define CONFIG_NS16550_MIN_FUNCTIONS 462 #endif 463 464 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 465 466 #define CONFIG_SYS_BAUDRATE_TABLE \ 467 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 468 469 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 470 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 471 472 /* Use the HUSH parser */ 473 #define CONFIG_SYS_HUSH_PARSER 474 475 /* 476 * Pass open firmware flat tree 477 */ 478 #define CONFIG_OF_LIBFDT 479 #define CONFIG_OF_BOARD_SETUP 480 #define CONFIG_OF_STDOUT_VIA_ALIAS 481 482 /* new uImage format support */ 483 #define CONFIG_FIT 484 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 485 486 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 487 #define CONFIG_HARD_I2C /* I2C with hardware support */ 488 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 489 #define CONFIG_I2C_MULTI_BUS 490 #define CONFIG_I2C_CMD_TREE 491 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ 492 #define CONFIG_SYS_I2C_SLAVE 0x7F 493 #define CONFIG_SYS_I2C_OFFSET 0x3000 494 #define CONFIG_SYS_I2C2_OFFSET 0x3100 495 496 /* I2C EEPROM */ 497 #undef CONFIG_ID_EEPROM 498 /* enable read and write access to EEPROM */ 499 #define CONFIG_CMD_EEPROM 500 #define CONFIG_SYS_I2C_MULTI_EEPROMS 501 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 502 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 503 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 504 505 /* RTC */ 506 #define CONFIG_RTC_PT7C4338 507 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 508 509 #define CONFIG_CMD_I2C 510 511 /* 512 * SPI interface will not be available in case of NAND boot SPI CS0 will be 513 * used for SLIC 514 */ 515 #if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT) 516 /* eSPI - Enhanced SPI */ 517 #define CONFIG_FSL_ESPI 518 #define CONFIG_SPI_FLASH 519 #define CONFIG_SPI_FLASH_SPANSION 520 #define CONFIG_CMD_SF 521 #define CONFIG_SF_DEFAULT_SPEED 10000000 522 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 523 #endif 524 525 #if defined(CONFIG_TSEC_ENET) 526 #define CONFIG_MII /* MII PHY management */ 527 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 528 #define CONFIG_TSEC1 1 529 #define CONFIG_TSEC1_NAME "eTSEC1" 530 #define CONFIG_TSEC2 1 531 #define CONFIG_TSEC2_NAME "eTSEC2" 532 #define CONFIG_TSEC3 1 533 #define CONFIG_TSEC3_NAME "eTSEC3" 534 535 #define TSEC1_PHY_ADDR 1 536 #define TSEC2_PHY_ADDR 0 537 #define TSEC3_PHY_ADDR 2 538 539 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 540 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 541 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 542 543 #define TSEC1_PHYIDX 0 544 #define TSEC2_PHYIDX 0 545 #define TSEC3_PHYIDX 0 546 547 #define CONFIG_ETHPRIME "eTSEC1" 548 549 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 550 551 /* TBI PHY configuration for SGMII mode */ 552 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 553 TBICR_PHY_RESET \ 554 | TBICR_ANEG_ENABLE \ 555 | TBICR_FULL_DUPLEX \ 556 | TBICR_SPEED1_SET \ 557 ) 558 559 #endif /* CONFIG_TSEC_ENET */ 560 561 562 /* SATA */ 563 #define CONFIG_FSL_SATA 564 #define CONFIG_FSL_SATA_V2 565 #define CONFIG_LIBATA 566 567 #ifdef CONFIG_FSL_SATA 568 #define CONFIG_SYS_SATA_MAX_DEVICE 2 569 #define CONFIG_SATA1 570 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 571 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 572 #define CONFIG_SATA2 573 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 574 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 575 576 #define CONFIG_CMD_SATA 577 #define CONFIG_LBA48 578 #endif /* #ifdef CONFIG_FSL_SATA */ 579 580 /* SD interface will only be available in case of SD boot */ 581 #ifdef CONFIG_SDCARD 582 #define CONFIG_MMC 583 #define CONFIG_DEF_HWCONFIG esdhc 584 #endif 585 586 #ifdef CONFIG_MMC 587 #define CONFIG_CMD_MMC 588 #define CONFIG_DOS_PARTITION 589 #define CONFIG_FSL_ESDHC 590 #define CONFIG_GENERIC_MMC 591 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 592 #endif 593 594 #define CONFIG_HAS_FSL_DR_USB 595 596 #if defined(CONFIG_HAS_FSL_DR_USB) 597 #define CONFIG_USB_EHCI 598 599 #ifdef CONFIG_USB_EHCI 600 #define CONFIG_CMD_USB 601 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 602 #define CONFIG_USB_EHCI_FSL 603 #define CONFIG_USB_STORAGE 604 #endif 605 #endif 606 607 /* 608 * Environment 609 */ 610 #if defined(CONFIG_SYS_RAMBOOT) 611 #if defined(CONFIG_RAMBOOT_SDCARD) 612 #define CONFIG_ENV_IS_IN_MMC 613 #define CONFIG_FSL_FIXED_MMC_LOCATION 614 #define CONFIG_SYS_MMC_ENV_DEV 0 615 #define CONFIG_ENV_SIZE 0x2000 616 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 617 #define CONFIG_ENV_IS_IN_SPI_FLASH 618 #define CONFIG_ENV_SPI_BUS 0 619 #define CONFIG_ENV_SPI_CS 0 620 #define CONFIG_ENV_SPI_MAX_HZ 10000000 621 #define CONFIG_ENV_SPI_MODE 0 622 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 623 #define CONFIG_ENV_SECT_SIZE 0x10000 624 #define CONFIG_ENV_SIZE 0x2000 625 #elif defined(CONFIG_NAND_U_BOOT) 626 #define CONFIG_ENV_IS_IN_NAND 627 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 628 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE 629 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 630 #else 631 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 632 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 633 #define CONFIG_ENV_SIZE 0x2000 634 #endif 635 #else 636 #define CONFIG_ENV_IS_IN_FLASH 637 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 638 #define CONFIG_ENV_ADDR 0xfff80000 639 #else 640 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 641 #endif 642 #define CONFIG_ENV_SIZE 0x2000 643 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 644 #endif 645 646 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 647 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 648 649 /* 650 * Command line configuration. 651 */ 652 #include <config_cmd_default.h> 653 654 #define CONFIG_CMD_DATE 655 #define CONFIG_CMD_ERRATA 656 #define CONFIG_CMD_ELF 657 #define CONFIG_CMD_IRQ 658 #define CONFIG_CMD_MII 659 #define CONFIG_CMD_PING 660 #define CONFIG_CMD_SETEXPR 661 #define CONFIG_CMD_REGINFO 662 663 #undef CONFIG_WATCHDOG /* watchdog disabled */ 664 665 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 666 || defined(CONFIG_FSL_SATA) 667 #define CONFIG_CMD_EXT2 668 #define CONFIG_CMD_FAT 669 #define CONFIG_DOS_PARTITION 670 #endif 671 672 /* 673 * Miscellaneous configurable options 674 */ 675 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 676 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 677 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 678 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 679 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 680 681 #if defined(CONFIG_CMD_KGDB) 682 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 683 #else 684 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 685 #endif 686 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 687 /* Print Buffer Size */ 688 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 689 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 690 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ 691 692 /* 693 * Internal Definitions 694 * 695 * Boot Flags 696 */ 697 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 698 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 699 700 /* 701 * For booting Linux, the board info and command line data 702 * have to be in the first 64 MB of memory, since this is 703 * the maximum mapped by the Linux kernel during initialization. 704 */ 705 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 706 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 707 708 #if defined(CONFIG_CMD_KGDB) 709 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 710 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 711 #endif 712 713 /* 714 * Environment Configuration 715 */ 716 717 #if defined(CONFIG_TSEC_ENET) 718 #define CONFIG_HAS_ETH0 719 #define CONFIG_HAS_ETH1 720 #define CONFIG_HAS_ETH2 721 #endif 722 723 #define CONFIG_HOSTNAME P1010RDB 724 #define CONFIG_ROOTPATH "/opt/nfsroot" 725 #define CONFIG_BOOTFILE "uImage" 726 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 727 728 /* default location for tftp and bootm */ 729 #define CONFIG_LOADADDR 1000000 730 731 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 732 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 733 734 #define CONFIG_BAUDRATE 115200 735 736 #define CONFIG_EXTRA_ENV_SETTINGS \ 737 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 738 "netdev=eth0\0" \ 739 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 740 "loadaddr=1000000\0" \ 741 "consoledev=ttyS0\0" \ 742 "ramdiskaddr=2000000\0" \ 743 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 744 "fdtaddr=c00000\0" \ 745 "fdtfile=p1010rdb.dtb\0" \ 746 "bdev=sda1\0" \ 747 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 748 "othbootargs=ramdisk_size=600000\0" \ 749 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 750 "console=$consoledev,$baudrate $othbootargs; " \ 751 "usb start;" \ 752 "fatload usb 0:2 $loadaddr $bootfile;" \ 753 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 754 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 755 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 756 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 757 "console=$consoledev,$baudrate $othbootargs; " \ 758 "usb start;" \ 759 "ext2load usb 0:4 $loadaddr $bootfile;" \ 760 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 761 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 762 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 763 764 #define CONFIG_RAMBOOTCOMMAND \ 765 "setenv bootargs root=/dev/ram rw " \ 766 "console=$consoledev,$baudrate $othbootargs; " \ 767 "tftp $ramdiskaddr $ramdiskfile;" \ 768 "tftp $loadaddr $bootfile;" \ 769 "tftp $fdtaddr $fdtfile;" \ 770 "bootm $loadaddr $ramdiskaddr $fdtaddr" 771 772 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 773 774 #ifdef CONFIG_SECURE_BOOT 775 #include <asm/fsl_secure_boot.h> 776 #endif 777 778 #endif /* __CONFIG_H */ 779