1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * P010 RDB board configuration file 25 */ 26 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #ifdef CONFIG_36BIT 31 #define CONFIG_PHYS_64BIT 32 #endif 33 34 #ifdef CONFIG_P1010RDB 35 #define CONFIG_P1010 36 #endif 37 38 #ifdef CONFIG_SDCARD 39 #define CONFIG_RAMBOOT_SDCARD 40 #define CONFIG_SYS_TEXT_BASE 0x11000000 41 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 42 #endif 43 44 #ifdef CONFIG_SPIFLASH 45 #define CONFIG_RAMBOOT_SPIFLASH 46 #define CONFIG_SYS_TEXT_BASE 0x11000000 47 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 48 #endif 49 50 #ifndef CONFIG_SYS_TEXT_BASE 51 #define CONFIG_SYS_TEXT_BASE 0xeff80000 52 #endif 53 54 #ifndef CONFIG_RESET_VECTOR_ADDRESS 55 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 56 #endif 57 58 #ifndef CONFIG_SYS_MONITOR_BASE 59 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 60 #endif 61 62 /* High Level Configuration Options */ 63 #define CONFIG_BOOKE /* BOOKE */ 64 #define CONFIG_E500 /* BOOKE e500 family */ 65 #define CONFIG_MPC85xx 66 #define CONFIG_FSL_IFC /* Enable IFC Support */ 67 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 68 69 #define CONFIG_PCI /* Enable PCI/PCIE */ 70 #if defined(CONFIG_PCI) 71 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 72 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 73 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 74 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 75 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 76 77 #define CONFIG_CMD_NET 78 #define CONFIG_CMD_PCI 79 80 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 81 82 /* 83 * PCI Windows 84 * Memory space is mapped 1-1, but I/O space must start from 0. 85 */ 86 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 87 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 88 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 89 #ifdef CONFIG_PHYS_64BIT 90 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 91 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 92 #else 93 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 94 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 95 #endif 96 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 97 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 98 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 99 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 100 #ifdef CONFIG_PHYS_64BIT 101 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 102 #else 103 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 104 #endif 105 106 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 107 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 108 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 109 #ifdef CONFIG_PHYS_64BIT 110 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 111 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 112 #else 113 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 114 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 115 #endif 116 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 117 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 118 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 119 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 120 #ifdef CONFIG_PHYS_64BIT 121 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 122 #else 123 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 124 #endif 125 126 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 127 128 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 129 #define CONFIG_DOS_PARTITION 130 #endif 131 132 #define CONFIG_FSL_LAW /* Use common FSL init code */ 133 #define CONFIG_TSEC_ENET 134 #define CONFIG_ENV_OVERWRITE 135 136 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 137 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 138 139 #ifndef CONFIG_SDCARD 140 #define CONFIG_MISC_INIT_R 141 #endif 142 143 #define CONFIG_HWCONFIG 144 /* 145 * These can be toggled for performance analysis, otherwise use default. 146 */ 147 #define CONFIG_L2_CACHE /* toggle L2 cache */ 148 #define CONFIG_BTB /* toggle branch predition */ 149 150 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 151 152 #define CONFIG_ENABLE_36BIT_PHYS 153 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_ADDR_MAP 1 156 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 157 #endif 158 159 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 160 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 161 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 162 163 /* DDR Setup */ 164 #define CONFIG_FSL_DDR3 165 #define CONFIG_DDR_RAW_TIMING 166 #define CONFIG_DDR_SPD 167 #define CONFIG_SYS_SPD_BUS_NUM 1 168 #define SPD_EEPROM_ADDRESS 0x52 169 170 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 171 172 #ifndef __ASSEMBLY__ 173 extern unsigned long get_sdram_size(void); 174 #endif 175 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 176 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 177 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 178 179 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 180 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 181 182 /* DDR3 Controller Settings */ 183 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 184 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 185 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 186 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 187 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 188 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 189 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 190 191 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 192 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 193 #define CONFIG_SYS_DDR_RCW_1 0x00000000 194 #define CONFIG_SYS_DDR_RCW_2 0x00000000 195 #define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */ 196 #define CONFIG_SYS_DDR_CONTROL_2 0x04401010 197 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 198 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 199 200 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 201 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 202 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644 203 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 204 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 205 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 206 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 207 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 208 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 209 210 /* settings for DDR3 at 667MT/s */ 211 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 212 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 213 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 214 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 215 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 216 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 217 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 218 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 219 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 220 221 #define CONFIG_SYS_CCSRBAR 0xffe00000 222 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 223 224 /* 225 * Memory map 226 * 227 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 228 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 229 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 230 * 231 * Localbus non-cacheable 232 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 233 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 234 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 235 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 236 */ 237 238 /* In case of SD card boot, IFC interface is not available because of muxing */ 239 #ifdef CONFIG_SDCARD 240 #define CONFIG_SYS_NO_FLASH 241 #else 242 /* 243 * IFC Definitions 244 */ 245 /* NOR Flash on IFC */ 246 #define CONFIG_SYS_FLASH_BASE 0xee000000 247 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 248 249 #ifdef CONFIG_PHYS_64BIT 250 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 251 #else 252 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 253 #endif 254 255 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 256 CSPR_PORT_SIZE_16 | \ 257 CSPR_MSEL_NOR | \ 258 CSPR_V) 259 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 260 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 261 /* NOR Flash Timing Params */ 262 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 263 FTIM0_NOR_TEADC(0x5) | \ 264 FTIM0_NOR_TEAHC(0x5) 265 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 266 FTIM1_NOR_TRAD_NOR(0x0f) 267 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 268 FTIM2_NOR_TCH(0x4) | \ 269 FTIM2_NOR_TWP(0x1c) 270 #define CONFIG_SYS_NOR_FTIM3 0x0 271 272 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 273 #define CONFIG_SYS_FLASH_QUIET_TEST 274 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 275 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 276 277 #undef CONFIG_SYS_FLASH_CHECKSUM 278 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 279 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 280 281 /* CFI for NOR Flash */ 282 #define CONFIG_FLASH_CFI_DRIVER 283 #define CONFIG_SYS_FLASH_CFI 284 #define CONFIG_SYS_FLASH_EMPTY_INFO 285 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 286 287 /* NAND Flash on IFC */ 288 #define CONFIG_SYS_NAND_BASE 0xff800000 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 291 #else 292 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 293 #endif 294 295 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 296 | CSPR_PORT_SIZE_8 \ 297 | CSPR_MSEL_NAND \ 298 | CSPR_V) 299 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 300 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 301 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 302 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 303 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 304 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 305 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 306 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 307 308 /* NAND Flash Timing Params */ 309 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 310 FTIM0_NAND_TWP(0x0C) | \ 311 FTIM0_NAND_TWCHT(0x04) | \ 312 FTIM0_NAND_TWH(0x05) 313 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 314 FTIM1_NAND_TWBE(0x1d) | \ 315 FTIM1_NAND_TRR(0x07) | \ 316 FTIM1_NAND_TRP(0x0c) 317 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 318 FTIM2_NAND_TREH(0x05) | \ 319 FTIM2_NAND_TWHRE(0x0f) 320 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 321 322 #define CONFIG_SYS_NAND_DDR_LAW 11 323 324 /* Set up IFC registers for boot location NOR/NAND */ 325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 332 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 333 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 334 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 335 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 336 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 337 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 338 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 339 340 /* CPLD on IFC */ 341 #define CONFIG_SYS_CPLD_BASE 0xffb00000 342 343 #ifdef CONFIG_PHYS_64BIT 344 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 345 #else 346 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 347 #endif 348 349 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 350 | CSPR_PORT_SIZE_8 \ 351 | CSPR_MSEL_GPCM \ 352 | CSPR_V) 353 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 354 #define CONFIG_SYS_CSOR3 0x0 355 /* CPLD Timing parameters for IFC CS3 */ 356 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 357 FTIM0_GPCM_TEADC(0x0e) | \ 358 FTIM0_GPCM_TEAHC(0x0e)) 359 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 360 FTIM1_GPCM_TRAD(0x1f)) 361 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 362 FTIM2_GPCM_TCH(0x0) | \ 363 FTIM2_GPCM_TWP(0x1f)) 364 #define CONFIG_SYS_CS3_FTIM3 0x0 365 #endif /* CONFIG_SDCARD */ 366 367 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 368 defined(CONFIG_RAMBOOT_NAND) 369 #define CONFIG_SYS_RAMBOOT 370 #define CONFIG_SYS_EXTRA_ENV_RELOC 371 #else 372 #undef CONFIG_SYS_RAMBOOT 373 #endif 374 375 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 376 #define CONFIG_BOARD_EARLY_INIT_R 377 378 #define CONFIG_SYS_INIT_RAM_LOCK 379 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 380 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 381 382 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 383 - GENERATED_GBL_DATA_SIZE) 384 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 385 386 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 387 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 388 389 /* Serial Port */ 390 #define CONFIG_CONS_INDEX 1 391 #undef CONFIG_SERIAL_SOFTWARE_FIFO 392 #define CONFIG_SYS_NS16550 393 #define CONFIG_SYS_NS16550_SERIAL 394 #define CONFIG_SYS_NS16550_REG_SIZE 1 395 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 396 397 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 398 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 399 400 #define CONFIG_SYS_BAUDRATE_TABLE \ 401 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 402 403 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 404 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 405 406 /* Use the HUSH parser */ 407 #define CONFIG_SYS_HUSH_PARSER 408 #ifdef CONFIG_SYS_HUSH_PARSER 409 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 410 #endif 411 412 /* 413 * Pass open firmware flat tree 414 */ 415 #define CONFIG_OF_LIBFDT 416 #define CONFIG_OF_BOARD_SETUP 417 #define CONFIG_OF_STDOUT_VIA_ALIAS 418 419 /* new uImage format support */ 420 #define CONFIG_FIT 421 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 422 423 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 424 #define CONFIG_HARD_I2C /* I2C with hardware support */ 425 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 426 #define CONFIG_I2C_MULTI_BUS 427 #define CONFIG_I2C_CMD_TREE 428 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ 429 #define CONFIG_SYS_I2C_SLAVE 0x7F 430 #define CONFIG_SYS_I2C_OFFSET 0x3000 431 #define CONFIG_SYS_I2C2_OFFSET 0x3100 432 433 /* I2C EEPROM */ 434 #undef CONFIG_ID_EEPROM 435 /* enable read and write access to EEPROM */ 436 #define CONFIG_CMD_EEPROM 437 #define CONFIG_SYS_I2C_MULTI_EEPROMS 438 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 439 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 440 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 441 442 /* RTC */ 443 #define CONFIG_RTC_PT7C4338 444 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 445 446 #define CONFIG_CMD_I2C 447 448 /* 449 * SPI interface will not be available in case of NAND boot SPI CS0 will be 450 * used for SLIC 451 */ 452 /* eSPI - Enhanced SPI */ 453 #define CONFIG_FSL_ESPI 454 #define CONFIG_SPI_FLASH 455 #define CONFIG_SPI_FLASH_SPANSION 456 #define CONFIG_CMD_SF 457 #define CONFIG_SF_DEFAULT_SPEED 10000000 458 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 459 460 #if defined(CONFIG_TSEC_ENET) 461 #ifndef CONFIG_NET_MULTI 462 #define CONFIG_NET_MULTI 463 #endif 464 465 #define CONFIG_MII /* MII PHY management */ 466 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 467 #define CONFIG_TSEC1 1 468 #define CONFIG_TSEC1_NAME "eTSEC1" 469 #define CONFIG_TSEC2 1 470 #define CONFIG_TSEC2_NAME "eTSEC2" 471 #define CONFIG_TSEC3 1 472 #define CONFIG_TSEC3_NAME "eTSEC3" 473 474 #define TSEC1_PHY_ADDR 1 475 #define TSEC2_PHY_ADDR 0 476 #define TSEC3_PHY_ADDR 2 477 478 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 479 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 480 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 481 482 #define TSEC1_PHYIDX 0 483 #define TSEC2_PHYIDX 0 484 #define TSEC3_PHYIDX 0 485 486 #define CONFIG_ETHPRIME "eTSEC1" 487 488 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 489 490 /* TBI PHY configuration for SGMII mode */ 491 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 492 TBICR_PHY_RESET \ 493 | TBICR_ANEG_ENABLE \ 494 | TBICR_FULL_DUPLEX \ 495 | TBICR_SPEED1_SET \ 496 ) 497 498 #endif /* CONFIG_TSEC_ENET */ 499 500 501 /* SATA */ 502 #define CONFIG_FSL_SATA 503 #define CONFIG_LIBATA 504 505 #ifdef CONFIG_FSL_SATA 506 #define CONFIG_SYS_SATA_MAX_DEVICE 2 507 #define CONFIG_SATA1 508 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 509 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 510 #define CONFIG_SATA2 511 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 512 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 513 514 #define CONFIG_CMD_SATA 515 #define CONFIG_LBA48 516 #endif /* #ifdef CONFIG_FSL_SATA */ 517 518 /* SD interface will only be available in case of SD boot */ 519 #ifdef CONFIG_SDCARD 520 #define CONFIG_MMC 521 #define CONFIG_DEF_HWCONFIG esdhc 522 #endif 523 524 #ifdef CONFIG_MMC 525 #define CONFIG_CMD_MMC 526 #define CONFIG_DOS_PARTITION 527 #define CONFIG_FSL_ESDHC 528 #define CONFIG_GENERIC_MMC 529 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 530 #endif 531 532 #define CONFIG_HAS_FSL_DR_USB 533 534 #if defined(CONFIG_HAS_FSL_DR_USB) 535 #define CONFIG_USB_EHCI 536 537 #ifdef CONFIG_USB_EHCI 538 #define CONFIG_CMD_USB 539 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 540 #define CONFIG_USB_EHCI_FSL 541 #define CONFIG_USB_STORAGE 542 #endif 543 #endif 544 545 /* 546 * Environment 547 */ 548 #if defined(CONFIG_SYS_RAMBOOT) 549 #if defined(CONFIG_RAMBOOT_SDCARD) 550 #define CONFIG_ENV_IS_IN_MMC 551 #define CONFIG_SYS_MMC_ENV_DEV 0 552 #define CONFIG_ENV_SIZE 0x2000 553 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 554 #define CONFIG_ENV_IS_IN_SPI_FLASH 555 #define CONFIG_ENV_SPI_BUS 0 556 #define CONFIG_ENV_SPI_CS 0 557 #define CONFIG_ENV_SPI_MAX_HZ 10000000 558 #define CONFIG_ENV_SPI_MODE 0 559 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 560 #define CONFIG_ENV_SECT_SIZE 0x10000 561 #define CONFIG_ENV_SIZE 0x2000 562 #else 563 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 564 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 565 #define CONFIG_ENV_SIZE 0x2000 566 #endif 567 #else 568 #define CONFIG_ENV_IS_IN_FLASH 569 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 570 #define CONFIG_ENV_ADDR 0xfff80000 571 #else 572 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 573 #endif 574 #define CONFIG_ENV_SIZE 0x2000 575 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 576 #endif 577 578 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 579 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 580 581 /* 582 * Command line configuration. 583 */ 584 #include <config_cmd_default.h> 585 586 #define CONFIG_CMD_DATE 587 #define CONFIG_CMD_ERRATA 588 #define CONFIG_CMD_ELF 589 #define CONFIG_CMD_IRQ 590 #define CONFIG_CMD_MII 591 #define CONFIG_CMD_PING 592 #define CONFIG_CMD_SETEXPR 593 #define CONFIG_CMD_REGINFO 594 595 #undef CONFIG_WATCHDOG /* watchdog disabled */ 596 597 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 598 || defined(CONFIG_FSL_SATA) 599 #define CONFIG_CMD_EXT2 600 #define CONFIG_CMD_FAT 601 #define CONFIG_DOS_PARTITION 602 #endif 603 604 /* 605 * Miscellaneous configurable options 606 */ 607 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 608 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 609 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 610 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 611 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 612 613 #if defined(CONFIG_CMD_KGDB) 614 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 615 #else 616 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 617 #endif 618 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 619 /* Print Buffer Size */ 620 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 621 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 622 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ 623 624 /* 625 * Internal Definitions 626 * 627 * Boot Flags 628 */ 629 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 630 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 631 632 /* 633 * For booting Linux, the board info and command line data 634 * have to be in the first 64 MB of memory, since this is 635 * the maximum mapped by the Linux kernel during initialization. 636 */ 637 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 638 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 639 640 #if defined(CONFIG_CMD_KGDB) 641 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 642 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 643 #endif 644 645 /* 646 * Environment Configuration 647 */ 648 649 #if defined(CONFIG_TSEC_ENET) 650 #define CONFIG_HAS_ETH0 651 #define CONFIG_HAS_ETH1 652 #define CONFIG_HAS_ETH2 653 #endif 654 655 #define CONFIG_HOSTNAME P1010RDB 656 #define CONFIG_ROOTPATH /opt/nfsroot 657 #define CONFIG_BOOTFILE uImage 658 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 659 660 /* default location for tftp and bootm */ 661 #define CONFIG_LOADADDR 1000000 662 663 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 664 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 665 666 #define CONFIG_BAUDRATE 115200 667 668 #define CONFIG_EXTRA_ENV_SETTINGS \ 669 "hwconfig=" MK_STR(CONFIG_DEF_HWCONFIG) "\0" \ 670 "netdev=eth0\0" \ 671 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 672 "loadaddr=1000000\0" \ 673 "consoledev=ttyS0\0" \ 674 "ramdiskaddr=2000000\0" \ 675 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 676 "fdtaddr=c00000\0" \ 677 "fdtfile=p1010rdb.dtb\0" \ 678 "bdev=sda1\0" \ 679 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 680 "othbootargs=ramdisk_size=600000\0" \ 681 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 682 "console=$consoledev,$baudrate $othbootargs; " \ 683 "usb start;" \ 684 "fatload usb 0:2 $loadaddr $bootfile;" \ 685 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 686 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 687 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 688 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 689 "console=$consoledev,$baudrate $othbootargs; " \ 690 "usb start;" \ 691 "ext2load usb 0:4 $loadaddr $bootfile;" \ 692 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 693 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 694 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 695 696 #define CONFIG_RAMBOOTCOMMAND \ 697 "setenv bootargs root=/dev/ram rw " \ 698 "console=$consoledev,$baudrate $othbootargs; " \ 699 "tftp $ramdiskaddr $ramdiskfile;" \ 700 "tftp $loadaddr $bootfile;" \ 701 "tftp $fdtaddr $fdtfile;" \ 702 "bootm $loadaddr $ramdiskaddr $fdtaddr" 703 704 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 705 706 #endif /* __CONFIG_H */ 707