1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <asm/config_mpc85xx.h> 15 #define CONFIG_NAND_FSL_IFC 16 17 #ifdef CONFIG_SDCARD 18 #define CONFIG_SPL_MMC_MINIMAL 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 21 #define CONFIG_SYS_TEXT_BASE 0x11001000 22 #define CONFIG_SPL_TEXT_BASE 0xD0001000 23 #define CONFIG_SPL_PAD_TO 0x18000 24 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 25 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 28 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 31 #define CONFIG_SPL_MMC_BOOT 32 #ifdef CONFIG_SPL_BUILD 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #endif 35 #endif 36 37 #ifdef CONFIG_SPIFLASH 38 #ifdef CONFIG_SECURE_BOOT 39 #define CONFIG_RAMBOOT_SPIFLASH 40 #define CONFIG_SYS_TEXT_BASE 0x11000000 41 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 42 #else 43 #define CONFIG_SPL_SPI_FLASH_MINIMAL 44 #define CONFIG_SPL_FLUSH_IMAGE 45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 46 #define CONFIG_SYS_TEXT_BASE 0x11001000 47 #define CONFIG_SPL_TEXT_BASE 0xD0001000 48 #define CONFIG_SPL_PAD_TO 0x18000 49 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 56 #define CONFIG_SPL_SPI_BOOT 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #endif 60 #endif 61 #endif 62 63 #ifdef CONFIG_NAND 64 #ifdef CONFIG_SECURE_BOOT 65 #define CONFIG_SPL_INIT_MINIMAL 66 #define CONFIG_SPL_NAND_BOOT 67 #define CONFIG_SPL_FLUSH_IMAGE 68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 69 70 #define CONFIG_SYS_TEXT_BASE 0x00201000 71 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 72 #define CONFIG_SPL_MAX_SIZE 8192 73 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 74 #define CONFIG_SPL_RELOC_STACK 0x00100000 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 76 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 77 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 78 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 80 #else 81 #ifdef CONFIG_TPL_BUILD 82 #define CONFIG_SPL_NAND_BOOT 83 #define CONFIG_SPL_FLUSH_IMAGE 84 #define CONFIG_SPL_NAND_INIT 85 #define CONFIG_SPL_COMMON_INIT_DDR 86 #define CONFIG_SPL_MAX_SIZE (128 << 10) 87 #define CONFIG_SPL_TEXT_BASE 0xD0001000 88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 89 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 90 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 91 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 92 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 93 #elif defined(CONFIG_SPL_BUILD) 94 #define CONFIG_SPL_INIT_MINIMAL 95 #define CONFIG_SPL_NAND_MINIMAL 96 #define CONFIG_SPL_FLUSH_IMAGE 97 #define CONFIG_SPL_TEXT_BASE 0xff800000 98 #define CONFIG_SPL_MAX_SIZE 8192 99 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 100 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 101 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 102 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 103 #endif 104 #define CONFIG_SPL_PAD_TO 0x20000 105 #define CONFIG_TPL_PAD_TO 0x20000 106 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 107 #define CONFIG_SYS_TEXT_BASE 0x11001000 108 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 109 #endif 110 #endif 111 112 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 113 #define CONFIG_RAMBOOT_NAND 114 #define CONFIG_SYS_TEXT_BASE 0x11000000 115 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 116 #endif 117 118 #ifndef CONFIG_SYS_TEXT_BASE 119 #define CONFIG_SYS_TEXT_BASE 0xeff40000 120 #endif 121 122 #ifndef CONFIG_RESET_VECTOR_ADDRESS 123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 124 #endif 125 126 #ifdef CONFIG_SPL_BUILD 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 128 #else 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 #endif 131 132 /* High Level Configuration Options */ 133 #define CONFIG_FSL_IFC /* Enable IFC Support */ 134 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 135 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 136 137 #if defined(CONFIG_PCI) 138 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 139 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 140 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 141 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 142 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 143 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 144 145 #define CONFIG_CMD_PCI 146 147 /* 148 * PCI Windows 149 * Memory space is mapped 1-1, but I/O space must start from 0. 150 */ 151 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 152 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 153 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 156 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 157 #else 158 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 159 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 160 #endif 161 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 162 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 163 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 164 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 167 #else 168 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 169 #endif 170 171 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 172 #if defined(CONFIG_TARGET_P1010RDB_PA) 173 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 174 #elif defined(CONFIG_TARGET_P1010RDB_PB) 175 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 176 #endif 177 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 178 #ifdef CONFIG_PHYS_64BIT 179 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 180 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 181 #else 182 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 183 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 184 #endif 185 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 186 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 187 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 188 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 189 #ifdef CONFIG_PHYS_64BIT 190 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 191 #else 192 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 193 #endif 194 195 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 196 #define CONFIG_DOS_PARTITION 197 #endif 198 199 #define CONFIG_TSEC_ENET 200 #define CONFIG_ENV_OVERWRITE 201 202 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 203 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 204 205 #define CONFIG_MISC_INIT_R 206 #define CONFIG_HWCONFIG 207 /* 208 * These can be toggled for performance analysis, otherwise use default. 209 */ 210 #define CONFIG_L2_CACHE /* toggle L2 cache */ 211 #define CONFIG_BTB /* toggle branch predition */ 212 213 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 214 215 #define CONFIG_ENABLE_36BIT_PHYS 216 217 #ifdef CONFIG_PHYS_64BIT 218 #define CONFIG_ADDR_MAP 1 219 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 220 #endif 221 222 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 223 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 224 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 225 226 /* DDR Setup */ 227 #define CONFIG_SYS_FSL_DDR3 228 #define CONFIG_SYS_DDR_RAW_TIMING 229 #define CONFIG_DDR_SPD 230 #define CONFIG_SYS_SPD_BUS_NUM 1 231 #define SPD_EEPROM_ADDRESS 0x52 232 233 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 234 235 #ifndef __ASSEMBLY__ 236 extern unsigned long get_sdram_size(void); 237 #endif 238 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 239 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 240 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 241 242 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 243 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 244 245 /* DDR3 Controller Settings */ 246 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 247 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 248 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 249 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 250 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 251 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 252 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 253 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 254 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 255 #define CONFIG_SYS_DDR_RCW_1 0x00000000 256 #define CONFIG_SYS_DDR_RCW_2 0x00000000 257 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 258 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 259 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 260 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 261 262 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 263 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 264 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 265 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 266 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 267 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 268 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 269 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 270 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 271 272 /* settings for DDR3 at 667MT/s */ 273 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 274 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 275 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 276 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 277 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 278 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 279 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 280 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 281 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 282 283 #define CONFIG_SYS_CCSRBAR 0xffe00000 284 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 285 286 /* Don't relocate CCSRBAR while in NAND_SPL */ 287 #ifdef CONFIG_SPL_BUILD 288 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 289 #endif 290 291 /* 292 * Memory map 293 * 294 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 295 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 296 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 297 * 298 * Localbus non-cacheable 299 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 300 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 301 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 302 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 303 */ 304 305 /* 306 * IFC Definitions 307 */ 308 /* NOR Flash on IFC */ 309 #ifdef CONFIG_SPL_BUILD 310 #define CONFIG_SYS_NO_FLASH 311 #endif 312 313 #define CONFIG_SYS_FLASH_BASE 0xee000000 314 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 315 316 #ifdef CONFIG_PHYS_64BIT 317 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 318 #else 319 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 320 #endif 321 322 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 323 CSPR_PORT_SIZE_16 | \ 324 CSPR_MSEL_NOR | \ 325 CSPR_V) 326 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 327 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 328 /* NOR Flash Timing Params */ 329 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 330 FTIM0_NOR_TEADC(0x5) | \ 331 FTIM0_NOR_TEAHC(0x5) 332 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 333 FTIM1_NOR_TRAD_NOR(0x0f) 334 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 335 FTIM2_NOR_TCH(0x4) | \ 336 FTIM2_NOR_TWP(0x1c) 337 #define CONFIG_SYS_NOR_FTIM3 0x0 338 339 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 340 #define CONFIG_SYS_FLASH_QUIET_TEST 341 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 342 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 343 344 #undef CONFIG_SYS_FLASH_CHECKSUM 345 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 346 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 347 348 /* CFI for NOR Flash */ 349 #define CONFIG_FLASH_CFI_DRIVER 350 #define CONFIG_SYS_FLASH_CFI 351 #define CONFIG_SYS_FLASH_EMPTY_INFO 352 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 353 354 /* NAND Flash on IFC */ 355 #define CONFIG_SYS_NAND_BASE 0xff800000 356 #ifdef CONFIG_PHYS_64BIT 357 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 358 #else 359 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 360 #endif 361 362 #define CONFIG_MTD_DEVICE 363 #define CONFIG_MTD_PARTITION 364 #define CONFIG_CMD_MTDPARTS 365 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 366 #define MTDPARTS_DEFAULT \ 367 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 368 369 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 370 | CSPR_PORT_SIZE_8 \ 371 | CSPR_MSEL_NAND \ 372 | CSPR_V) 373 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 374 375 #if defined(CONFIG_TARGET_P1010RDB_PA) 376 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 377 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 378 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 379 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 380 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 381 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 382 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 383 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 384 385 #elif defined(CONFIG_TARGET_P1010RDB_PB) 386 #define CONFIG_SYS_NAND_ONFI_DETECTION 387 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 388 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 389 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 390 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 391 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 392 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 393 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 394 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 395 #endif 396 397 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 398 #define CONFIG_SYS_MAX_NAND_DEVICE 1 399 #define CONFIG_CMD_NAND 400 401 #if defined(CONFIG_TARGET_P1010RDB_PA) 402 /* NAND Flash Timing Params */ 403 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 404 FTIM0_NAND_TWP(0x0C) | \ 405 FTIM0_NAND_TWCHT(0x04) | \ 406 FTIM0_NAND_TWH(0x05) 407 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 408 FTIM1_NAND_TWBE(0x1d) | \ 409 FTIM1_NAND_TRR(0x07) | \ 410 FTIM1_NAND_TRP(0x0c) 411 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 412 FTIM2_NAND_TREH(0x05) | \ 413 FTIM2_NAND_TWHRE(0x0f) 414 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 415 416 #elif defined(CONFIG_TARGET_P1010RDB_PB) 417 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 418 /* ONFI NAND Flash mode0 Timing Params */ 419 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 420 FTIM0_NAND_TWP(0x18) | \ 421 FTIM0_NAND_TWCHT(0x07) | \ 422 FTIM0_NAND_TWH(0x0a)) 423 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 424 FTIM1_NAND_TWBE(0x39) | \ 425 FTIM1_NAND_TRR(0x0e) | \ 426 FTIM1_NAND_TRP(0x18)) 427 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 428 FTIM2_NAND_TREH(0x0a) | \ 429 FTIM2_NAND_TWHRE(0x1e)) 430 #define CONFIG_SYS_NAND_FTIM3 0x0 431 #endif 432 433 #define CONFIG_SYS_NAND_DDR_LAW 11 434 435 /* Set up IFC registers for boot location NOR/NAND */ 436 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 437 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 438 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 439 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 440 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 441 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 442 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 443 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 444 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 445 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 446 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 447 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 448 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 449 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 450 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 451 #else 452 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 453 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 454 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 455 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 456 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 457 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 458 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 459 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 460 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 461 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 462 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 463 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 464 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 465 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 466 #endif 467 468 /* CPLD on IFC */ 469 #define CONFIG_SYS_CPLD_BASE 0xffb00000 470 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 473 #else 474 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 475 #endif 476 477 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 478 | CSPR_PORT_SIZE_8 \ 479 | CSPR_MSEL_GPCM \ 480 | CSPR_V) 481 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 482 #define CONFIG_SYS_CSOR3 0x0 483 /* CPLD Timing parameters for IFC CS3 */ 484 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 485 FTIM0_GPCM_TEADC(0x0e) | \ 486 FTIM0_GPCM_TEAHC(0x0e)) 487 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 488 FTIM1_GPCM_TRAD(0x1f)) 489 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 490 FTIM2_GPCM_TCH(0x8) | \ 491 FTIM2_GPCM_TWP(0x1f)) 492 #define CONFIG_SYS_CS3_FTIM3 0x0 493 494 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 495 defined(CONFIG_RAMBOOT_NAND) 496 #define CONFIG_SYS_RAMBOOT 497 #define CONFIG_SYS_EXTRA_ENV_RELOC 498 #else 499 #undef CONFIG_SYS_RAMBOOT 500 #endif 501 502 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 503 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 504 #define CONFIG_A003399_NOR_WORKAROUND 505 #endif 506 #endif 507 508 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 509 #define CONFIG_BOARD_EARLY_INIT_R 510 511 #define CONFIG_SYS_INIT_RAM_LOCK 512 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 513 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 514 515 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 516 - GENERATED_GBL_DATA_SIZE) 517 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 518 519 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 520 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 521 522 /* 523 * Config the L2 Cache as L2 SRAM 524 */ 525 #if defined(CONFIG_SPL_BUILD) 526 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 527 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 528 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 529 #define CONFIG_SYS_L2_SIZE (256 << 10) 530 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 531 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 532 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 533 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 534 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 535 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 536 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 537 #elif defined(CONFIG_NAND) 538 #ifdef CONFIG_TPL_BUILD 539 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 540 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 541 #define CONFIG_SYS_L2_SIZE (256 << 10) 542 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 543 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 544 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 545 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 546 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 547 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 548 #else 549 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 550 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 551 #define CONFIG_SYS_L2_SIZE (256 << 10) 552 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 553 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 554 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 555 #endif 556 #endif 557 #endif 558 559 /* Serial Port */ 560 #define CONFIG_CONS_INDEX 1 561 #undef CONFIG_SERIAL_SOFTWARE_FIFO 562 #define CONFIG_SYS_NS16550_SERIAL 563 #define CONFIG_SYS_NS16550_REG_SIZE 1 564 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 565 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 566 #define CONFIG_NS16550_MIN_FUNCTIONS 567 #endif 568 569 #define CONFIG_SYS_BAUDRATE_TABLE \ 570 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 571 572 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 573 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 574 575 /* I2C */ 576 #define CONFIG_SYS_I2C 577 #define CONFIG_SYS_I2C_FSL 578 #define CONFIG_SYS_FSL_I2C_SPEED 400000 579 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 580 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 581 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 582 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 583 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 584 #define I2C_PCA9557_ADDR1 0x18 585 #define I2C_PCA9557_ADDR2 0x19 586 #define I2C_PCA9557_BUS_NUM 0 587 588 /* I2C EEPROM */ 589 #if defined(CONFIG_TARGET_P1010RDB_PB) 590 #define CONFIG_ID_EEPROM 591 #ifdef CONFIG_ID_EEPROM 592 #define CONFIG_SYS_I2C_EEPROM_NXID 593 #endif 594 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 595 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 596 #define CONFIG_SYS_EEPROM_BUS_NUM 0 597 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 598 #endif 599 /* enable read and write access to EEPROM */ 600 #define CONFIG_CMD_EEPROM 601 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 602 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 603 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 604 605 /* RTC */ 606 #define CONFIG_RTC_PT7C4338 607 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 608 609 /* 610 * SPI interface will not be available in case of NAND boot SPI CS0 will be 611 * used for SLIC 612 */ 613 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 614 /* eSPI - Enhanced SPI */ 615 #define CONFIG_SF_DEFAULT_SPEED 10000000 616 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 617 #endif 618 619 #if defined(CONFIG_TSEC_ENET) 620 #define CONFIG_MII /* MII PHY management */ 621 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 622 #define CONFIG_TSEC1 1 623 #define CONFIG_TSEC1_NAME "eTSEC1" 624 #define CONFIG_TSEC2 1 625 #define CONFIG_TSEC2_NAME "eTSEC2" 626 #define CONFIG_TSEC3 1 627 #define CONFIG_TSEC3_NAME "eTSEC3" 628 629 #define TSEC1_PHY_ADDR 1 630 #define TSEC2_PHY_ADDR 0 631 #define TSEC3_PHY_ADDR 2 632 633 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 634 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 635 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 636 637 #define TSEC1_PHYIDX 0 638 #define TSEC2_PHYIDX 0 639 #define TSEC3_PHYIDX 0 640 641 #define CONFIG_ETHPRIME "eTSEC1" 642 643 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 644 645 /* TBI PHY configuration for SGMII mode */ 646 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 647 TBICR_PHY_RESET \ 648 | TBICR_ANEG_ENABLE \ 649 | TBICR_FULL_DUPLEX \ 650 | TBICR_SPEED1_SET \ 651 ) 652 653 #endif /* CONFIG_TSEC_ENET */ 654 655 /* SATA */ 656 #define CONFIG_FSL_SATA 657 #define CONFIG_FSL_SATA_V2 658 #define CONFIG_LIBATA 659 660 #ifdef CONFIG_FSL_SATA 661 #define CONFIG_SYS_SATA_MAX_DEVICE 2 662 #define CONFIG_SATA1 663 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 664 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 665 #define CONFIG_SATA2 666 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 667 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 668 669 #define CONFIG_CMD_SATA 670 #define CONFIG_LBA48 671 #endif /* #ifdef CONFIG_FSL_SATA */ 672 673 #ifdef CONFIG_MMC 674 #define CONFIG_DOS_PARTITION 675 #define CONFIG_FSL_ESDHC 676 #define CONFIG_GENERIC_MMC 677 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 678 #endif 679 680 #define CONFIG_HAS_FSL_DR_USB 681 682 #if defined(CONFIG_HAS_FSL_DR_USB) 683 #define CONFIG_USB_EHCI 684 685 #ifdef CONFIG_USB_EHCI 686 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 687 #define CONFIG_USB_EHCI_FSL 688 #endif 689 #endif 690 691 /* 692 * Environment 693 */ 694 #if defined(CONFIG_SDCARD) 695 #define CONFIG_ENV_IS_IN_MMC 696 #define CONFIG_FSL_FIXED_MMC_LOCATION 697 #define CONFIG_SYS_MMC_ENV_DEV 0 698 #define CONFIG_ENV_SIZE 0x2000 699 #elif defined(CONFIG_SPIFLASH) 700 #define CONFIG_ENV_IS_IN_SPI_FLASH 701 #define CONFIG_ENV_SPI_BUS 0 702 #define CONFIG_ENV_SPI_CS 0 703 #define CONFIG_ENV_SPI_MAX_HZ 10000000 704 #define CONFIG_ENV_SPI_MODE 0 705 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 706 #define CONFIG_ENV_SECT_SIZE 0x10000 707 #define CONFIG_ENV_SIZE 0x2000 708 #elif defined(CONFIG_NAND) 709 #define CONFIG_ENV_IS_IN_NAND 710 #ifdef CONFIG_TPL_BUILD 711 #define CONFIG_ENV_SIZE 0x2000 712 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 713 #else 714 #if defined(CONFIG_TARGET_P1010RDB_PA) 715 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 716 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 717 #elif defined(CONFIG_TARGET_P1010RDB_PB) 718 #define CONFIG_ENV_SIZE (16 * 1024) 719 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 720 #endif 721 #endif 722 #define CONFIG_ENV_OFFSET (1024 * 1024) 723 #elif defined(CONFIG_SYS_RAMBOOT) 724 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 725 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 726 #define CONFIG_ENV_SIZE 0x2000 727 #else 728 #define CONFIG_ENV_IS_IN_FLASH 729 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 730 #define CONFIG_ENV_SIZE 0x2000 731 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 732 #endif 733 734 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 735 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 736 737 /* 738 * Command line configuration. 739 */ 740 #define CONFIG_CMD_DATE 741 #define CONFIG_CMD_ERRATA 742 #define CONFIG_CMD_IRQ 743 #define CONFIG_CMD_REGINFO 744 745 #undef CONFIG_WATCHDOG /* watchdog disabled */ 746 747 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 748 || defined(CONFIG_FSL_SATA) 749 #define CONFIG_DOS_PARTITION 750 #endif 751 752 /* Hash command with SHA acceleration supported in hardware */ 753 #ifdef CONFIG_FSL_CAAM 754 #define CONFIG_CMD_HASH 755 #define CONFIG_SHA_HW_ACCEL 756 #endif 757 758 /* 759 * Miscellaneous configurable options 760 */ 761 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 762 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 763 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 764 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 765 766 #if defined(CONFIG_CMD_KGDB) 767 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 768 #else 769 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 770 #endif 771 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 772 /* Print Buffer Size */ 773 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 774 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 775 776 /* 777 * For booting Linux, the board info and command line data 778 * have to be in the first 64 MB of memory, since this is 779 * the maximum mapped by the Linux kernel during initialization. 780 */ 781 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 782 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 783 784 #if defined(CONFIG_CMD_KGDB) 785 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 786 #endif 787 788 /* 789 * Environment Configuration 790 */ 791 792 #if defined(CONFIG_TSEC_ENET) 793 #define CONFIG_HAS_ETH0 794 #define CONFIG_HAS_ETH1 795 #define CONFIG_HAS_ETH2 796 #endif 797 798 #define CONFIG_ROOTPATH "/opt/nfsroot" 799 #define CONFIG_BOOTFILE "uImage" 800 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 801 802 /* default location for tftp and bootm */ 803 #define CONFIG_LOADADDR 1000000 804 805 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 806 807 #define CONFIG_BAUDRATE 115200 808 809 #define CONFIG_EXTRA_ENV_SETTINGS \ 810 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 811 "netdev=eth0\0" \ 812 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 813 "loadaddr=1000000\0" \ 814 "consoledev=ttyS0\0" \ 815 "ramdiskaddr=2000000\0" \ 816 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 817 "fdtaddr=1e00000\0" \ 818 "fdtfile=p1010rdb.dtb\0" \ 819 "bdev=sda1\0" \ 820 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 821 "othbootargs=ramdisk_size=600000\0" \ 822 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 823 "console=$consoledev,$baudrate $othbootargs; " \ 824 "usb start;" \ 825 "fatload usb 0:2 $loadaddr $bootfile;" \ 826 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 827 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 828 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 829 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 830 "console=$consoledev,$baudrate $othbootargs; " \ 831 "usb start;" \ 832 "ext2load usb 0:4 $loadaddr $bootfile;" \ 833 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 834 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 835 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 836 CONFIG_BOOTMODE 837 838 #if defined(CONFIG_TARGET_P1010RDB_PA) 839 #define CONFIG_BOOTMODE \ 840 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 841 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 842 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 843 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 844 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 845 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 846 847 #elif defined(CONFIG_TARGET_P1010RDB_PB) 848 #define CONFIG_BOOTMODE \ 849 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 850 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 851 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 852 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 853 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 854 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 855 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 856 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 857 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 858 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 859 #endif 860 861 #define CONFIG_RAMBOOTCOMMAND \ 862 "setenv bootargs root=/dev/ram rw " \ 863 "console=$consoledev,$baudrate $othbootargs; " \ 864 "tftp $ramdiskaddr $ramdiskfile;" \ 865 "tftp $loadaddr $bootfile;" \ 866 "tftp $fdtaddr $fdtfile;" \ 867 "bootm $loadaddr $ramdiskaddr $fdtaddr" 868 869 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 870 871 #include <asm/fsl_secure_boot.h> 872 873 #endif /* __CONFIG_H */ 874