xref: /rk3399_rockchip-uboot/include/configs/MigoR.h (revision 684a501e8e94115b591bfb3c8f047ccaada4ac26)
1c2042f59Sgoda.yusuke /*
2c2042f59Sgoda.yusuke  * Configuation settings for the Renesas Solutions Migo-R board
3c2042f59Sgoda.yusuke  *
4c2042f59Sgoda.yusuke  * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5c2042f59Sgoda.yusuke  *
61a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
7c2042f59Sgoda.yusuke  */
8c2042f59Sgoda.yusuke 
9c2042f59Sgoda.yusuke #ifndef __MIGO_R_H
10c2042f59Sgoda.yusuke #define __MIGO_R_H
11c2042f59Sgoda.yusuke 
12c2042f59Sgoda.yusuke #undef DEBUG
13c2042f59Sgoda.yusuke #define CONFIG_SH		1
14c2042f59Sgoda.yusuke #define CONFIG_SH4		1
15c2042f59Sgoda.yusuke #define CONFIG_CPU_SH7722	1
16c2042f59Sgoda.yusuke #define CONFIG_MIGO_R		1
17c2042f59Sgoda.yusuke 
18c2042f59Sgoda.yusuke #define CONFIG_CMD_LOADB
19c2042f59Sgoda.yusuke #define CONFIG_CMD_LOADS
20c2042f59Sgoda.yusuke #define CONFIG_CMD_FLASH
21c2042f59Sgoda.yusuke #define CONFIG_CMD_MEMORY
22c2042f59Sgoda.yusuke #define CONFIG_CMD_NET
23c2042f59Sgoda.yusuke #define CONFIG_CMD_PING
24c2042f59Sgoda.yusuke #define CONFIG_CMD_NFS
25c2042f59Sgoda.yusuke #define CONFIG_CMD_SDRAM
26bdab39d3SMike Frysinger #define CONFIG_CMD_SAVEENV
27c2042f59Sgoda.yusuke 
28c2042f59Sgoda.yusuke #define CONFIG_BAUDRATE		115200
29c2042f59Sgoda.yusuke #define CONFIG_BOOTDELAY	3
30c2042f59Sgoda.yusuke #define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"
31c2042f59Sgoda.yusuke 
32c2042f59Sgoda.yusuke #define CONFIG_VERSION_VARIABLE
33c2042f59Sgoda.yusuke #undef  CONFIG_SHOW_BOOT_PROGRESS
34c2042f59Sgoda.yusuke 
35c2042f59Sgoda.yusuke /* SMC9111 */
367194ab80SBen Warren #define CONFIG_SMC91111
37c2042f59Sgoda.yusuke #define CONFIG_SMC91111_BASE    (0xB0000000)
38c2042f59Sgoda.yusuke 
39c2042f59Sgoda.yusuke /* MEMORY */
40c2042f59Sgoda.yusuke #define MIGO_R_SDRAM_BASE	(0x8C000000)
41c2042f59Sgoda.yusuke #define MIGO_R_FLASH_BASE_1	(0xA0000000)
42c2042f59Sgoda.yusuke #define MIGO_R_FLASH_BANK_SIZE	(64 * 1024 * 1024)
43c2042f59Sgoda.yusuke 
448cd7379eSNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE	0x8FFC0000
456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE		256		/* Buffer size for input from the Console */
486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS		16		/* max args accepted for monitor commands */
506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE	512		/* Buffer size for Boot Arguments passed to kernel */
516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
52c2042f59Sgoda.yusuke 
53c2042f59Sgoda.yusuke /* SCIF */
546c58a030SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SCIF_CONSOLE	1
55c2042f59Sgoda.yusuke #define CONFIG_CONS_SCIF0	1
566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress display of console
57c2042f59Sgoda.yusuke 								   information at boot */
586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
60c2042f59Sgoda.yusuke 
616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START	(MIGO_R_SDRAM_BASE)
626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
63c2042f59Sgoda.yusuke 
64c2042f59Sgoda.yusuke /* Enable alternate, more extensive, memory test */
656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_ALT_MEMTEST
66c2042f59Sgoda.yusuke /* Scratch address used by the alternate memory test */
676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_MEMTEST_SCRATCH
68c2042f59Sgoda.yusuke 
69c2042f59Sgoda.yusuke /* Enable temporary baudrate change while serial download */
706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
71c2042f59Sgoda.yusuke 
726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE	(MIGO_R_SDRAM_BASE)
73c2042f59Sgoda.yusuke /* maybe more, but if so u-boot doesn't know about it... */
746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)
75c2042f59Sgoda.yusuke /* default load address for scripts ?!? */
766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
77c2042f59Sgoda.yusuke 
78c2042f59Sgoda.yusuke /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE	(MIGO_R_FLASH_BASE_1)
80c2042f59Sgoda.yusuke /* Monitor size */
816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
82c2042f59Sgoda.yusuke /* Size of DRAM reserved for malloc() use */
836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
85c2042f59Sgoda.yusuke 
86c2042f59Sgoda.yusuke /* FLASH */
876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI
8800b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER
896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_FLASH_QUIET_TEST
90c2042f59Sgoda.yusuke /* print 'E' for empty sector on flinfo */
916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO
92c2042f59Sgoda.yusuke /* Physical start address of Flash memory */
936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE	(MIGO_R_FLASH_BASE_1)
94c2042f59Sgoda.yusuke /* Max number of sectors on each Flash chip */
956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT	512
96c2042f59Sgoda.yusuke 
97c2042f59Sgoda.yusuke /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS	1
996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
100c2042f59Sgoda.yusuke 
101c2042f59Sgoda.yusuke /* Timeout for Flash erase operations (in ms) */
1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
103c2042f59Sgoda.yusuke /* Timeout for Flash write operations (in ms) */
1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
105c2042f59Sgoda.yusuke /* Timeout for Flash set sector lock bit operations (in ms) */
1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
107c2042f59Sgoda.yusuke /* Timeout for Flash clear lock bit operations (in ms) */
1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
109c2042f59Sgoda.yusuke 
110c2042f59Sgoda.yusuke /* Use hardware flash sectors protection instead of U-Boot software protection */
1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_FLASH_PROTECTION
1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
113c2042f59Sgoda.yusuke 
114c2042f59Sgoda.yusuke /* ENV setting */
1155a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH
116c2042f59Sgoda.yusuke #define CONFIG_ENV_OVERWRITE	1
1170e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
1180e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
1220e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
123c2042f59Sgoda.yusuke 
124c2042f59Sgoda.yusuke /* Board Clock */
125c2042f59Sgoda.yusuke #define CONFIG_SYS_CLK_FREQ	33333333
126*684a501eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
127*684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
128be45c632SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
1298dd29c87SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ		1000
130c2042f59Sgoda.yusuke 
131c2042f59Sgoda.yusuke #endif	/* __MIGO_R_H */
132