1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 #undef DEBUG 42 43 #ifdef RUN_DIAG 44 #define CFG_DIAG_ADDR 0xff800000 45 #endif 46 47 #define CFG_RESET_ADDRESS 0xfff00100 48 49 /*#undef CONFIG_PCI*/ 50 #define CONFIG_PCI 51 52 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 53 #define CONFIG_ENV_OVERWRITE 54 55 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 56 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 57 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 58 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 59 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 60 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 61 #define CONFIG_NUM_DDR_CONTROLLERS 2 62 /* #define CONFIG_DDR_INTERLEAVE 1 */ 63 #define CACHE_LINE_INTERLEAVING 0x20000000 64 #define PAGE_INTERLEAVING 0x21000000 65 #define BANK_INTERLEAVING 0x22000000 66 #define SUPER_BANK_INTERLEAVING 0x23000000 67 68 69 #define CONFIG_ALTIVEC 1 70 71 /* 72 * L2CR setup -- make sure this is right for your board! 73 */ 74 #define CFG_L2 75 #define L2_INIT 0 76 #define L2_ENABLE (L2CR_L2E) 77 78 #ifndef CONFIG_SYS_CLK_FREQ 79 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 80 #endif 81 82 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 83 84 #undef CFG_DRAM_TEST /* memory test, takes time */ 85 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 86 #define CFG_MEMTEST_END 0x00400000 87 88 89 /* 90 * Base addresses -- Note these are effective addresses where the 91 * actual resources get mapped (not physical addresses) 92 */ 93 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 94 #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 95 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 96 97 98 /* 99 * DDR Setup 100 */ 101 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 102 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 103 #define CONFIG_VERY_BIG_RAM 104 105 #define MPC86xx_DDR_SDRAM_CLK_CNTL 106 107 #if defined(CONFIG_SPD_EEPROM) 108 /* 109 * Determine DDR configuration from I2C interface. 110 */ 111 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 112 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 113 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 114 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 115 116 #else 117 /* 118 * Manually set up DDR1 parameters 119 */ 120 121 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 122 123 #define CFG_DDR_CS0_BNDS 0x0000000F 124 #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 125 #define CFG_DDR_EXT_REFRESH 0x00000000 126 #define CFG_DDR_TIMING_0 0x00260802 127 #define CFG_DDR_TIMING_1 0x39357322 128 #define CFG_DDR_TIMING_2 0x14904cc8 129 #define CFG_DDR_MODE_1 0x00480432 130 #define CFG_DDR_MODE_2 0x00000000 131 #define CFG_DDR_INTERVAL 0x06090100 132 #define CFG_DDR_DATA_INIT 0xdeadbeef 133 #define CFG_DDR_CLK_CTRL 0x03800000 134 #define CFG_DDR_OCD_CTRL 0x00000000 135 #define CFG_DDR_OCD_STATUS 0x00000000 136 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 137 #define CFG_DDR_CONTROL2 0x04400000 138 139 /* Not used in fixed_sdram function */ 140 141 #define CFG_DDR_MODE 0x00000022 142 #define CFG_DDR_CS1_BNDS 0x00000000 143 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 144 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 145 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 146 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 147 #endif 148 149 150 /* 151 * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. 152 * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff 153 * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. 154 * However, when u-boot comes up, the flash_init needs hard start addresses 155 * to build its info table. For user convenience, the flash addresses is 156 * fe800000 and ff800000. That way, u-boot knows where the flash is 157 * and the user can download u-boot code from promjet to fef00000, a 158 * more intuitive location than fe700000. 159 * 160 * Note that, on switching the boot location, fef00000 becomes fff00000. 161 */ 162 #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ 163 #define CFG_FLASH_BASE2 0xff800000 164 165 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 166 167 #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ 168 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ 169 170 #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ 171 #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ 172 173 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 174 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 175 176 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 177 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 178 179 180 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 181 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 182 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 183 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 184 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 185 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 186 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 187 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 188 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 189 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 190 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 191 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 192 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 193 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 194 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 195 196 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 197 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 198 199 #undef CFG_FLASH_CHECKSUM 200 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 201 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 202 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 203 204 #define CFG_FLASH_CFI_DRIVER 205 #define CFG_FLASH_CFI 206 #define CFG_FLASH_EMPTY_INFO 207 208 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 209 #define CFG_RAMBOOT 210 #else 211 #undef CFG_RAMBOOT 212 #endif 213 214 #if defined(CFG_RAMBOOT) 215 #undef CFG_FLASH_CFI_DRIVER 216 #undef CONFIG_SPD_EEPROM 217 #define CFG_SDRAM_SIZE 256 218 #endif 219 220 #undef CONFIG_CLOCKS_IN_MHZ 221 222 #define CONFIG_L1_INIT_RAM 223 #define CFG_INIT_RAM_LOCK 1 224 #ifndef CFG_INIT_RAM_LOCK 225 #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 226 #else 227 #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 228 #endif 229 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 230 231 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 232 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 233 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 234 235 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 236 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 237 238 /* Serial Port */ 239 #define CONFIG_CONS_INDEX 1 240 #undef CONFIG_SERIAL_SOFTWARE_FIFO 241 #define CFG_NS16550 242 #define CFG_NS16550_SERIAL 243 #define CFG_NS16550_REG_SIZE 1 244 #define CFG_NS16550_CLK get_bus_freq(0) 245 246 #define CFG_BAUDRATE_TABLE \ 247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 248 249 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 250 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 251 252 /* Use the HUSH parser */ 253 #define CFG_HUSH_PARSER 254 #ifdef CFG_HUSH_PARSER 255 #define CFG_PROMPT_HUSH_PS2 "> " 256 #endif 257 258 /* 259 * Pass open firmware flat tree to kernel 260 */ 261 #define CONFIG_OF_FLAT_TREE 1 262 #define CONFIG_OF_BOARD_SETUP 1 263 264 /* maximum size of the flat tree (8K) */ 265 #define OF_FLAT_TREE_MAX_SIZE 8192 266 267 #define OF_CPU "PowerPC,8641@0" 268 #define OF_SOC "soc8641@f8000000" 269 #define OF_TBCLK (bd->bi_busfreq / 8) 270 #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" 271 272 #define CFG_64BIT_VSPRINTF 1 273 #define CFG_64BIT_STRTOUL 1 274 275 /* 276 * I2C 277 */ 278 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 279 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 280 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 281 #define CFG_I2C_SLAVE 0x7F 282 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 283 284 /* 285 * RapidIO MMU 286 */ 287 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 288 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 289 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 290 291 /* 292 * General PCI 293 * Addresses are mapped 1-1. 294 */ 295 #define CFG_PCI1_MEM_BASE 0x80000000 296 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 297 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 298 #define CFG_PCI1_IO_BASE 0xe2000000 299 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 300 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 301 302 /* PCI view of System Memory */ 303 #define CFG_PCI_MEMORY_BUS 0x00000000 304 #define CFG_PCI_MEMORY_PHYS 0x00000000 305 #define CFG_PCI_MEMORY_SIZE 0x80000000 306 307 /* For RTL8139 */ 308 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 309 #define _IO_BASE 0x00000000 310 311 #define CFG_PCI2_MEM_BASE 0xa0000000 312 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 313 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 314 #define CFG_PCI2_IO_BASE 0xe3000000 315 #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE 316 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ 317 318 319 #if defined(CONFIG_PCI) 320 321 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 322 323 #undef CFG_SCSI_SCAN_BUS_REVERSE 324 325 #define CONFIG_NET_MULTI 326 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 327 328 #define CONFIG_RTL8139 329 330 #undef CONFIG_EEPRO100 331 #undef CONFIG_TULIP 332 333 #if !defined(CONFIG_PCI_PNP) 334 #define PCI_ENET0_IOADDR 0xe0000000 335 #define PCI_ENET0_MEMADDR 0xe0000000 336 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 337 #endif 338 339 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 340 341 #endif /* CONFIG_PCI */ 342 343 344 #if defined(CONFIG_TSEC_ENET) 345 346 #ifndef CONFIG_NET_MULTI 347 #define CONFIG_NET_MULTI 1 348 #endif 349 350 #define CONFIG_MII 1 /* MII PHY management */ 351 352 #define CONFIG_MPC86XX_TSEC1 1 353 #define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" 354 #define CONFIG_MPC86XX_TSEC2 1 355 #define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" 356 #define CONFIG_MPC86XX_TSEC3 1 357 #define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" 358 #define CONFIG_MPC86XX_TSEC4 1 359 #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" 360 361 #define TSEC1_PHY_ADDR 0 362 #define TSEC2_PHY_ADDR 1 363 #define TSEC3_PHY_ADDR 2 364 #define TSEC4_PHY_ADDR 3 365 #define TSEC1_PHYIDX 0 366 #define TSEC2_PHYIDX 0 367 #define TSEC3_PHYIDX 0 368 #define TSEC4_PHYIDX 0 369 370 #define CONFIG_ETHPRIME "eTSEC1" 371 372 #endif /* CONFIG_TSEC_ENET */ 373 374 375 /* 376 * BAT0 2G Cacheable, non-guarded 377 * 0x0000_0000 2G DDR 378 */ 379 #define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ 380 | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) 381 #define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) 382 #define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) 383 #define CFG_IBAT0U CFG_DBAT0U 384 385 /* 386 * BAT1 1G Cache-inhibited, guarded 387 * 0x8000_0000 512M PCI-Express 1 Memory 388 * 0xa000_0000 512M PCI-Express 2 Memory 389 * Changed it for operating from 0xd0000000 390 */ 391 #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ 392 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 393 #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 394 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 395 #define CFG_IBAT1U CFG_DBAT1U 396 397 /* 398 * BAT2 512M Cache-inhibited, guarded 399 * 0xc000_0000 512M RapidIO Memory 400 */ 401 #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ 402 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 403 #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 404 #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 405 #define CFG_IBAT2U CFG_DBAT2U 406 407 /* 408 * BAT3 4M Cache-inhibited, guarded 409 * 0xf800_0000 4M CCSR 410 */ 411 #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ 412 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 413 #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 414 #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 415 #define CFG_IBAT3U CFG_DBAT3U 416 417 /* 418 * BAT4 32M Cache-inhibited, guarded 419 * 0xe200_0000 16M PCI-Express 1 I/O 420 * 0xe300_0000 16M PCI-Express 2 I/0 421 * Note that this is at 0xe0000000 422 */ 423 #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ 424 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 425 #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 426 #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 427 #define CFG_IBAT4U CFG_DBAT4U 428 429 /* 430 * BAT5 128K Cacheable, non-guarded 431 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 432 */ 433 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 434 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 435 #define CFG_IBAT5L CFG_DBAT5L 436 #define CFG_IBAT5U CFG_DBAT5U 437 438 /* 439 * BAT6 32M Cache-inhibited, guarded 440 * 0xfe00_0000 32M FLASH 441 */ 442 #define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 443 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 444 #define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 445 #define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 446 #define CFG_IBAT6U CFG_DBAT6U 447 448 #define CFG_DBAT7L 0x00000000 449 #define CFG_DBAT7U 0x00000000 450 #define CFG_IBAT7L 0x00000000 451 #define CFG_IBAT7U 0x00000000 452 453 454 455 456 /* 457 * Environment 458 */ 459 #ifndef CFG_RAMBOOT 460 #define CFG_ENV_IS_IN_FLASH 1 461 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 462 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 463 #define CFG_ENV_SIZE 0x2000 464 #else 465 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 466 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 467 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 468 #define CFG_ENV_SIZE 0x2000 469 #endif 470 471 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 472 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 473 474 #if defined(CFG_RAMBOOT) 475 #if defined(CONFIG_PCI) 476 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 477 | CFG_CMD_PING \ 478 | CFG_CMD_PCI \ 479 | CFG_CMD_I2C) \ 480 & \ 481 ~(CFG_CMD_ENV \ 482 | CFG_CMD_IMLS \ 483 | CFG_CMD_FLASH \ 484 | CFG_CMD_LOADS)) 485 #else 486 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 487 | CFG_CMD_PING \ 488 | CFG_CMD_I2C) \ 489 & \ 490 ~(CFG_CMD_ENV \ 491 | CFG_CMD_IMLS \ 492 | CFG_CMD_FLASH \ 493 | CFG_CMD_LOADS)) 494 #endif 495 #else 496 #if defined(CONFIG_PCI) 497 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 498 | CFG_CMD_PCI \ 499 | CFG_CMD_PING \ 500 | CFG_CMD_I2C) 501 #else 502 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 503 | CFG_CMD_PING \ 504 | CFG_CMD_I2C) 505 #endif 506 #endif 507 508 #include <cmd_confdefs.h> 509 510 #undef CONFIG_WATCHDOG /* watchdog disabled */ 511 512 /* 513 * Miscellaneous configurable options 514 */ 515 #define CFG_LONGHELP /* undef to save memory */ 516 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 517 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 518 519 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 520 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 521 #else 522 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 523 #endif 524 525 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 526 #define CFG_MAXARGS 16 /* max number of command args */ 527 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 528 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 529 530 /* 531 * For booting Linux, the board info and command line data 532 * have to be in the first 8 MB of memory, since this is 533 * the maximum mapped by the Linux kernel during initialization. 534 */ 535 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 536 537 /* Cache Configuration */ 538 #define CFG_DCACHE_SIZE 32768 539 #define CFG_CACHELINE_SIZE 32 540 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 541 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 542 #endif 543 544 /* 545 * Internal Definitions 546 * 547 * Boot Flags 548 */ 549 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 550 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 551 552 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 553 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 554 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 555 #endif 556 557 558 /* 559 * Environment Configuration 560 */ 561 562 /* The mac addresses for all ethernet interface */ 563 #if defined(CONFIG_TSEC_ENET) 564 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 565 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 566 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 567 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 568 #endif 569 570 #define CONFIG_HAS_ETH1 1 571 #define CONFIG_HAS_ETH2 1 572 #define CONFIG_HAS_ETH3 1 573 574 #define CONFIG_IPADDR 192.168.1.100 575 576 #define CONFIG_HOSTNAME unknown 577 #define CONFIG_ROOTPATH /opt/nfsroot 578 #define CONFIG_BOOTFILE uImage 579 580 #define CONFIG_SERVERIP 192.168.1.1 581 #define CONFIG_GATEWAYIP 192.168.1.1 582 #define CONFIG_NETMASK 255.255.255.0 583 584 /* default location for tftp and bootm */ 585 #define CONFIG_LOADADDR 1000000 586 587 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 588 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 589 590 #define CONFIG_BAUDRATE 115200 591 592 #define CONFIG_EXTRA_ENV_SETTINGS \ 593 "netdev=eth0\0" \ 594 "consoledev=ttyS0\0" \ 595 "ramdiskaddr=400000\0" \ 596 "ramdiskfile=your.ramdisk.u-boot\0" \ 597 "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ 598 "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ 599 "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ 600 "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ 601 "pex=run pexstat; run pex1; run pexd\0" \ 602 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 603 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 604 "maxcpus=2" 605 606 607 #define CONFIG_NFSBOOTCOMMAND \ 608 "setenv bootargs root=/dev/nfs rw " \ 609 "nfsroot=$serverip:$rootpath " \ 610 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 611 "console=$consoledev,$baudrate $othbootargs;" \ 612 "tftp $loadaddr $bootfile;" \ 613 "bootm $loadaddr" 614 615 #define CONFIG_RAMBOOTCOMMAND \ 616 "setenv bootargs root=/dev/ram rw " \ 617 "console=$consoledev,$baudrate $othbootargs;" \ 618 "tftp $ramdiskaddr $ramdiskfile;" \ 619 "tftp $loadaddr $bootfile;" \ 620 "bootm $loadaddr $ramdiskaddr" 621 622 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 623 624 #endif /* __CONFIG_H */ 625