1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 #undef DEBUG 42 43 #ifdef RUN_DIAG 44 #define CFG_DIAG_ADDR 0xff800000 45 #endif 46 47 #define CFG_RESET_ADDRESS 0xfff00100 48 49 /*#undef CONFIG_PCI*/ 50 #define CONFIG_PCI 51 52 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 53 #define CONFIG_ENV_OVERWRITE 54 55 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 56 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 57 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 58 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 59 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 60 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 61 #define CONFIG_NUM_DDR_CONTROLLERS 2 62 /* #define CONFIG_DDR_INTERLEAVE 1 */ 63 #define CACHE_LINE_INTERLEAVING 0x20000000 64 #define PAGE_INTERLEAVING 0x21000000 65 #define BANK_INTERLEAVING 0x22000000 66 #define SUPER_BANK_INTERLEAVING 0x23000000 67 68 69 #define CONFIG_ALTIVEC 1 70 71 /* 72 * L2CR setup -- make sure this is right for your board! 73 */ 74 #define CFG_L2 75 #define L2_INIT 0 76 #define L2_ENABLE (L2CR_L2E) 77 78 #ifndef CONFIG_SYS_CLK_FREQ 79 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 80 #endif 81 82 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 83 84 #undef CFG_DRAM_TEST /* memory test, takes time */ 85 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 86 #define CFG_MEMTEST_END 0x00400000 87 88 89 /* 90 * Base addresses -- Note these are effective addresses where the 91 * actual resources get mapped (not physical addresses) 92 */ 93 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 94 #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 95 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 96 97 98 /* 99 * DDR Setup 100 */ 101 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 102 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 103 104 #define MPC86xx_DDR_SDRAM_CLK_CNTL 105 106 #if defined(CONFIG_SPD_EEPROM) 107 /* 108 * Determine DDR configuration from I2C interface. 109 */ 110 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 111 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 112 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 113 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 114 115 #else 116 /* 117 * Manually set up DDR1 parameters 118 */ 119 120 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 121 122 #define CFG_DDR_CS0_BNDS 0x0000000F 123 #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 124 #define CFG_DDR_EXT_REFRESH 0x00000000 125 #define CFG_DDR_TIMING_0 0x00260802 126 #define CFG_DDR_TIMING_1 0x39357322 127 #define CFG_DDR_TIMING_2 0x14904cc8 128 #define CFG_DDR_MODE_1 0x00480432 129 #define CFG_DDR_MODE_2 0x00000000 130 #define CFG_DDR_INTERVAL 0x06090100 131 #define CFG_DDR_DATA_INIT 0xdeadbeef 132 #define CFG_DDR_CLK_CTRL 0x03800000 133 #define CFG_DDR_OCD_CTRL 0x00000000 134 #define CFG_DDR_OCD_STATUS 0x00000000 135 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 136 #define CFG_DDR_CONTROL2 0x04400000 137 138 /* Not used in fixed_sdram function */ 139 140 #define CFG_DDR_MODE 0x00000022 141 #define CFG_DDR_CS1_BNDS 0x00000000 142 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 143 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 144 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 145 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 146 #endif 147 148 149 /* 150 * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. 151 * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff 152 * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. 153 * However, when u-boot comes up, the flash_init needs hard start addresses 154 * to build its info table. For user convenience, the flash addresses is 155 * fe800000 and ff800000. That way, u-boot knows where the flash is 156 * and the user can download u-boot code from promjet to fef00000, a 157 * more intuitive location than fe700000. 158 * 159 * Note that, on switching the boot location, fef00000 becomes fff00000. 160 */ 161 #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ 162 #define CFG_FLASH_BASE2 0xff800000 163 164 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 165 166 #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ 167 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ 168 169 #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ 170 #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ 171 172 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 173 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 174 175 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 176 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 177 178 179 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 180 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 181 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 182 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 183 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 184 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 185 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 186 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 187 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 188 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 189 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 190 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 191 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 192 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 193 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 194 195 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 196 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 197 198 #undef CFG_FLASH_CHECKSUM 199 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 200 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 201 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 202 203 #define CFG_FLASH_CFI_DRIVER 204 #define CFG_FLASH_CFI 205 #define CFG_FLASH_EMPTY_INFO 206 207 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 208 #define CFG_RAMBOOT 209 #else 210 #undef CFG_RAMBOOT 211 #endif 212 213 #if defined(CFG_RAMBOOT) 214 #undef CFG_FLASH_CFI_DRIVER 215 #undef CONFIG_SPD_EEPROM 216 #define CFG_SDRAM_SIZE 256 217 #endif 218 219 #undef CONFIG_CLOCKS_IN_MHZ 220 221 #define CONFIG_L1_INIT_RAM 222 #define CFG_INIT_RAM_LOCK 1 223 #ifndef CFG_INIT_RAM_LOCK 224 #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 225 #else 226 #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 227 #endif 228 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 229 230 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 231 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 232 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 233 234 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 235 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 236 237 /* Serial Port */ 238 #define CONFIG_CONS_INDEX 1 239 #undef CONFIG_SERIAL_SOFTWARE_FIFO 240 #define CFG_NS16550 241 #define CFG_NS16550_SERIAL 242 #define CFG_NS16550_REG_SIZE 1 243 #define CFG_NS16550_CLK get_bus_freq(0) 244 245 #define CFG_BAUDRATE_TABLE \ 246 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 247 248 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 249 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 250 251 /* Use the HUSH parser */ 252 #define CFG_HUSH_PARSER 253 #ifdef CFG_HUSH_PARSER 254 #define CFG_PROMPT_HUSH_PS2 "> " 255 #endif 256 257 /* 258 * Pass open firmware flat tree to kernel 259 */ 260 #define CONFIG_OF_FLAT_TREE 1 261 #define CONFIG_OF_BOARD_SETUP 1 262 263 /* maximum size of the flat tree (8K) */ 264 #define OF_FLAT_TREE_MAX_SIZE 8192 265 266 #define OF_CPU "PowerPC,8641@0" 267 #define OF_SOC "soc8641@f8000000" 268 #define OF_TBCLK (bd->bi_busfreq / 8) 269 #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" 270 271 #define CFG_64BIT_VSPRINTF 1 272 #define CFG_64BIT_STRTOUL 1 273 274 /* 275 * I2C 276 */ 277 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 278 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 279 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 280 #define CFG_I2C_SLAVE 0x7F 281 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 282 283 /* 284 * RapidIO MMU 285 */ 286 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 287 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 288 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 289 290 /* 291 * General PCI 292 * Addresses are mapped 1-1. 293 */ 294 #define CFG_PCI1_MEM_BASE 0x80000000 295 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 296 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 297 #define CFG_PCI1_IO_BASE 0xe2000000 298 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 299 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 300 301 /* PCI view of System Memory */ 302 #define CFG_PCI_MEMORY_BUS 0x00000000 303 #define CFG_PCI_MEMORY_PHYS 0x00000000 304 #define CFG_PCI_MEMORY_SIZE 0x80000000 305 306 /* For RTL8139 */ 307 #define _IO_BASE 0x00000000 308 309 #define CFG_PCI2_MEM_BASE 0xa0000000 310 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 311 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 312 #define CFG_PCI2_IO_BASE 0xe3000000 313 #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE 314 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ 315 316 317 #if defined(CONFIG_PCI) 318 319 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 320 321 #undef CFG_SCSI_SCAN_BUS_REVERSE 322 323 #define CONFIG_NET_MULTI 324 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 325 326 #define CONFIG_RTL8139 327 328 #undef CONFIG_EEPRO100 329 #undef CONFIG_TULIP 330 331 #if !defined(CONFIG_PCI_PNP) 332 #define PCI_ENET0_IOADDR 0xe0000000 333 #define PCI_ENET0_MEMADDR 0xe0000000 334 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 335 #endif 336 337 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 338 339 #endif /* CONFIG_PCI */ 340 341 342 #if defined(CONFIG_TSEC_ENET) 343 344 #ifndef CONFIG_NET_MULTI 345 #define CONFIG_NET_MULTI 1 346 #endif 347 348 #define CONFIG_MII 1 /* MII PHY management */ 349 350 #define CONFIG_MPC86XX_TSEC1 1 351 #define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" 352 #define CONFIG_MPC86XX_TSEC2 1 353 #define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" 354 #define CONFIG_MPC86XX_TSEC3 1 355 #define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" 356 #define CONFIG_MPC86XX_TSEC4 1 357 #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" 358 359 #define TSEC1_PHY_ADDR 0 360 #define TSEC2_PHY_ADDR 1 361 #define TSEC3_PHY_ADDR 2 362 #define TSEC4_PHY_ADDR 3 363 #define TSEC1_PHYIDX 0 364 #define TSEC2_PHYIDX 0 365 #define TSEC3_PHYIDX 0 366 #define TSEC4_PHYIDX 0 367 368 #define CONFIG_ETHPRIME "eTSEC1" 369 370 #endif /* CONFIG_TSEC_ENET */ 371 372 373 /* 374 * BAT0 2G Cacheable, non-guarded 375 * 0x0000_0000 2G DDR 376 */ 377 #define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ 378 | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) 379 #define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) 380 #define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) 381 #define CFG_IBAT0U CFG_DBAT0U 382 383 /* 384 * BAT1 1G Cache-inhibited, guarded 385 * 0x8000_0000 512M PCI-Express 1 Memory 386 * 0xa000_0000 512M PCI-Express 2 Memory 387 * Changed it for operating from 0xd0000000 388 */ 389 #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ 390 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 391 #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 392 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 393 #define CFG_IBAT1U CFG_DBAT1U 394 395 /* 396 * BAT2 512M Cache-inhibited, guarded 397 * 0xc000_0000 512M RapidIO Memory 398 */ 399 #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ 400 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 401 #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 402 #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 403 #define CFG_IBAT2U CFG_DBAT2U 404 405 /* 406 * BAT3 4M Cache-inhibited, guarded 407 * 0xf800_0000 4M CCSR 408 */ 409 #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ 410 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 411 #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 412 #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 413 #define CFG_IBAT3U CFG_DBAT3U 414 415 /* 416 * BAT4 32M Cache-inhibited, guarded 417 * 0xe200_0000 16M PCI-Express 1 I/O 418 * 0xe300_0000 16M PCI-Express 2 I/0 419 * Note that this is at 0xe0000000 420 */ 421 #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ 422 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 423 #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 424 #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 425 #define CFG_IBAT4U CFG_DBAT4U 426 427 /* 428 * BAT5 128K Cacheable, non-guarded 429 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 430 */ 431 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 432 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 433 #define CFG_IBAT5L CFG_DBAT5L 434 #define CFG_IBAT5U CFG_DBAT5U 435 436 /* 437 * BAT6 32M Cache-inhibited, guarded 438 * 0xfe00_0000 32M FLASH 439 */ 440 #define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 441 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 442 #define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 443 #define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 444 #define CFG_IBAT6U CFG_DBAT6U 445 446 #define CFG_DBAT7L 0x00000000 447 #define CFG_DBAT7U 0x00000000 448 #define CFG_IBAT7L 0x00000000 449 #define CFG_IBAT7U 0x00000000 450 451 452 453 454 /* 455 * Environment 456 */ 457 #ifndef CFG_RAMBOOT 458 #define CFG_ENV_IS_IN_FLASH 1 459 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 460 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 461 #define CFG_ENV_SIZE 0x2000 462 #else 463 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 464 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 465 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 466 #define CFG_ENV_SIZE 0x2000 467 #endif 468 469 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 470 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 471 472 #if defined(CFG_RAMBOOT) 473 #if defined(CONFIG_PCI) 474 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 475 | CFG_CMD_PING \ 476 | CFG_CMD_PCI \ 477 | CFG_CMD_I2C) \ 478 & \ 479 ~(CFG_CMD_ENV \ 480 | CFG_CMD_IMLS \ 481 | CFG_CMD_FLASH \ 482 | CFG_CMD_LOADS)) 483 #else 484 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 485 | CFG_CMD_PING \ 486 | CFG_CMD_I2C) \ 487 & \ 488 ~(CFG_CMD_ENV \ 489 | CFG_CMD_IMLS \ 490 | CFG_CMD_FLASH \ 491 | CFG_CMD_LOADS)) 492 #endif 493 #else 494 #if defined(CONFIG_PCI) 495 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 496 | CFG_CMD_PCI \ 497 | CFG_CMD_PING \ 498 | CFG_CMD_I2C) 499 #else 500 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 501 | CFG_CMD_PING \ 502 | CFG_CMD_I2C) 503 #endif 504 #endif 505 506 #include <cmd_confdefs.h> 507 508 #undef CONFIG_WATCHDOG /* watchdog disabled */ 509 510 /* 511 * Miscellaneous configurable options 512 */ 513 #define CFG_LONGHELP /* undef to save memory */ 514 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 515 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 516 517 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 518 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 519 #else 520 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 521 #endif 522 523 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 524 #define CFG_MAXARGS 16 /* max number of command args */ 525 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 526 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 527 528 /* 529 * For booting Linux, the board info and command line data 530 * have to be in the first 8 MB of memory, since this is 531 * the maximum mapped by the Linux kernel during initialization. 532 */ 533 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 534 535 /* Cache Configuration */ 536 #define CFG_DCACHE_SIZE 32768 537 #define CFG_CACHELINE_SIZE 32 538 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 539 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 540 #endif 541 542 /* 543 * Internal Definitions 544 * 545 * Boot Flags 546 */ 547 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 548 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 549 550 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 551 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 552 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 553 #endif 554 555 556 /* 557 * Environment Configuration 558 */ 559 560 /* The mac addresses for all ethernet interface */ 561 #if defined(CONFIG_TSEC_ENET) 562 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 563 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 564 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 565 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 566 #endif 567 568 #define CONFIG_HAS_ETH1 1 569 #define CONFIG_HAS_ETH2 1 570 #define CONFIG_HAS_ETH3 1 571 572 #define CONFIG_IPADDR 192.168.1.100 573 574 #define CONFIG_HOSTNAME unknown 575 #define CONFIG_ROOTPATH /opt/nfsroot 576 #define CONFIG_BOOTFILE uImage 577 578 #define CONFIG_SERVERIP 192.168.1.1 579 #define CONFIG_GATEWAYIP 192.168.1.1 580 #define CONFIG_NETMASK 255.255.255.0 581 582 /* default location for tftp and bootm */ 583 #define CONFIG_LOADADDR 1000000 584 585 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 586 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 587 588 #define CONFIG_BAUDRATE 115200 589 590 #define CONFIG_EXTRA_ENV_SETTINGS \ 591 "netdev=eth0\0" \ 592 "consoledev=ttyS0\0" \ 593 "ramdiskaddr=400000\0" \ 594 "ramdiskfile=your.ramdisk.u-boot\0" \ 595 "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ 596 "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ 597 "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ 598 "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ 599 "pex=run pexstat; run pex1; run pexd\0" \ 600 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 601 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 602 "maxcpus=2" 603 604 605 #define CONFIG_NFSBOOTCOMMAND \ 606 "setenv bootargs root=/dev/nfs rw " \ 607 "nfsroot=$serverip:$rootpath " \ 608 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 609 "console=$consoledev,$baudrate $othbootargs;" \ 610 "tftp $loadaddr $bootfile;" \ 611 "bootm $loadaddr" 612 613 #define CONFIG_RAMBOOTCOMMAND \ 614 "setenv bootargs root=/dev/ram rw " \ 615 "console=$consoledev,$baudrate $othbootargs;" \ 616 "tftp $ramdiskaddr $ramdiskfile;" \ 617 "tftp $loadaddr $bootfile;" \ 618 "bootm $loadaddr $ramdiskaddr" 619 620 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 621 622 #endif /* __CONFIG_H */ 623