1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 42 #ifdef RUN_DIAG 43 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 44 #endif 45 46 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 47 48 /* 49 * virtual address to be used for temporary mappings. There 50 * should be 128k free at this VA. 51 */ 52 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 53 54 /* 55 * set this to enable Rapid IO. PCI and RIO are mutually exclusive 56 */ 57 /*#define CONFIG_RIO 1*/ 58 59 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ 60 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 61 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ 62 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ 63 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 65 #endif 66 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 67 68 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 69 #define CONFIG_ENV_OVERWRITE 70 71 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 72 73 #define CONFIG_ALTIVEC 1 74 75 /* 76 * L2CR setup -- make sure this is right for your board! 77 */ 78 #define CONFIG_SYS_L2 79 #define L2_INIT 0 80 #define L2_ENABLE (L2CR_L2E) 81 82 #ifndef CONFIG_SYS_CLK_FREQ 83 #ifndef __ASSEMBLY__ 84 extern unsigned long get_board_sys_clk(unsigned long dummy); 85 #endif 86 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 87 #endif 88 89 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 90 91 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 92 #define CONFIG_SYS_MEMTEST_END 0x00400000 93 94 /* 95 * Base addresses -- Note these are effective addresses where the 96 * actual resources get mapped (not physical addresses) 97 */ 98 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 99 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 100 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 101 102 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 103 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 104 105 /* 106 * DDR Setup 107 */ 108 #define CONFIG_FSL_DDR2 109 #undef CONFIG_FSL_DDR_INTERACTIVE 110 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 111 #define CONFIG_DDR_SPD 112 113 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 114 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 115 116 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 118 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 119 #define CONFIG_VERY_BIG_RAM 120 121 #define MPC86xx_DDR_SDRAM_CLK_CNTL 122 123 #define CONFIG_NUM_DDR_CONTROLLERS 2 124 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 125 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 126 127 /* 128 * I2C addresses of SPD EEPROMs 129 */ 130 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 131 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 132 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 133 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 134 135 136 /* 137 * These are used when DDR doesn't use SPD. 138 */ 139 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 140 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 141 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 142 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 143 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 144 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 145 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 146 #define CONFIG_SYS_DDR_MODE_1 0x00480432 147 #define CONFIG_SYS_DDR_MODE_2 0x00000000 148 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 149 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 150 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 151 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 152 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 153 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 154 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 155 156 #define CONFIG_ID_EEPROM 157 #define CONFIG_SYS_I2C_EEPROM_NXID 158 #define CONFIG_ID_EEPROM 159 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 161 162 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 163 164 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 165 166 /* Convert an address into the right format for the BR registers */ 167 #define BR_PHYS_ADDR(x) (x & 0xffff8000) 168 169 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \ 170 | 0x00001001) /* port size 16bit */ 171 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 172 173 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \ 174 | 0x00001001) /* port size 16bit */ 175 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 176 177 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \ 178 | 0x00000801) /* port size 8bit */ 179 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 180 181 /* 182 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 183 * The PIXIS and CF by themselves aren't large enough to take up the 128k 184 * required for the smallest BAT mapping, so there's a 64k hole. 185 */ 186 #define CONFIG_SYS_LBC_BASE 0xffde0000 187 188 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 189 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 190 #define PIXIS_SIZE 0x00008000 /* 32k */ 191 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 192 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 193 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 194 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 195 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 196 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 197 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 198 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 199 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 200 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 201 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 202 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 203 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 204 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 205 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 206 207 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 208 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 209 210 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 211 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 212 213 #undef CONFIG_SYS_FLASH_CHECKSUM 214 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 215 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 216 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 217 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 218 219 #define CONFIG_FLASH_CFI_DRIVER 220 #define CONFIG_SYS_FLASH_CFI 221 #define CONFIG_SYS_FLASH_EMPTY_INFO 222 223 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 224 #define CONFIG_SYS_RAMBOOT 225 #else 226 #undef CONFIG_SYS_RAMBOOT 227 #endif 228 229 #if defined(CONFIG_SYS_RAMBOOT) 230 #undef CONFIG_SPD_EEPROM 231 #define CONFIG_SYS_SDRAM_SIZE 256 232 #endif 233 234 #undef CONFIG_CLOCKS_IN_MHZ 235 236 #define CONFIG_L1_INIT_RAM 237 #define CONFIG_SYS_INIT_RAM_LOCK 1 238 #ifndef CONFIG_SYS_INIT_RAM_LOCK 239 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 240 #else 241 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 242 #endif 243 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 244 245 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 246 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 247 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 248 249 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 250 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 251 252 /* Serial Port */ 253 #define CONFIG_CONS_INDEX 1 254 #undef CONFIG_SERIAL_SOFTWARE_FIFO 255 #define CONFIG_SYS_NS16550 256 #define CONFIG_SYS_NS16550_SERIAL 257 #define CONFIG_SYS_NS16550_REG_SIZE 1 258 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 259 260 #define CONFIG_SYS_BAUDRATE_TABLE \ 261 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 262 263 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 264 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 265 266 /* Use the HUSH parser */ 267 #define CONFIG_SYS_HUSH_PARSER 268 #ifdef CONFIG_SYS_HUSH_PARSER 269 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 270 #endif 271 272 /* 273 * Pass open firmware flat tree to kernel 274 */ 275 #define CONFIG_OF_LIBFDT 1 276 #define CONFIG_OF_BOARD_SETUP 1 277 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 278 279 280 #define CONFIG_SYS_64BIT_VSPRINTF 1 281 #define CONFIG_SYS_64BIT_STRTOUL 1 282 283 /* 284 * I2C 285 */ 286 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 287 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 288 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 289 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 290 #define CONFIG_SYS_I2C_SLAVE 0x7F 291 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 292 #define CONFIG_SYS_I2C_OFFSET 0x3100 293 294 /* 295 * RapidIO MMU 296 */ 297 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ 298 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 299 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 300 301 /* 302 * General PCI 303 * Addresses are mapped 1-1. 304 */ 305 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 306 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 307 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 308 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 309 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 310 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ 311 312 /* For RTL8139 */ 313 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 314 #define _IO_BASE 0x00000000 315 316 #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \ 317 + CONFIG_SYS_PCI1_MEM_SIZE) 318 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 319 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 320 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 321 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ 322 + CONFIG_SYS_PCI1_IO_SIZE) 323 #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE 324 325 #if defined(CONFIG_PCI) 326 327 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 328 329 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 330 331 #define CONFIG_NET_MULTI 332 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 333 334 #define CONFIG_RTL8139 335 336 #undef CONFIG_EEPRO100 337 #undef CONFIG_TULIP 338 339 /************************************************************ 340 * USB support 341 ************************************************************/ 342 #define CONFIG_PCI_OHCI 1 343 #define CONFIG_USB_OHCI_NEW 1 344 #define CONFIG_USB_KEYBOARD 1 345 #define CONFIG_SYS_DEVICE_DEREGISTER 346 #define CONFIG_SYS_USB_EVENT_POLL 1 347 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 348 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 349 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 350 351 /*PCIE video card used*/ 352 #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS 353 354 /*PCI video card used*/ 355 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ 356 357 /* video */ 358 #define CONFIG_VIDEO 359 360 #if defined(CONFIG_VIDEO) 361 #define CONFIG_BIOSEMU 362 #define CONFIG_CFB_CONSOLE 363 #define CONFIG_VIDEO_SW_CURSOR 364 #define CONFIG_VGA_AS_SINGLE_DEVICE 365 #define CONFIG_ATI_RADEON_FB 366 #define CONFIG_VIDEO_LOGO 367 /*#define CONFIG_CONSOLE_CURSOR*/ 368 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS 369 #endif 370 371 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 372 373 #define CONFIG_DOS_PARTITION 374 #define CONFIG_SCSI_AHCI 375 376 #ifdef CONFIG_SCSI_AHCI 377 #define CONFIG_SATA_ULI5288 378 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 379 #define CONFIG_SYS_SCSI_MAX_LUN 1 380 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 381 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 382 #endif 383 384 #define CONFIG_MPC86XX_PCI2 385 386 #endif /* CONFIG_PCI */ 387 388 #if defined(CONFIG_TSEC_ENET) 389 390 #ifndef CONFIG_NET_MULTI 391 #define CONFIG_NET_MULTI 1 392 #endif 393 394 #define CONFIG_MII 1 /* MII PHY management */ 395 396 #define CONFIG_TSEC1 1 397 #define CONFIG_TSEC1_NAME "eTSEC1" 398 #define CONFIG_TSEC2 1 399 #define CONFIG_TSEC2_NAME "eTSEC2" 400 #define CONFIG_TSEC3 1 401 #define CONFIG_TSEC3_NAME "eTSEC3" 402 #define CONFIG_TSEC4 1 403 #define CONFIG_TSEC4_NAME "eTSEC4" 404 405 #define TSEC1_PHY_ADDR 0 406 #define TSEC2_PHY_ADDR 1 407 #define TSEC3_PHY_ADDR 2 408 #define TSEC4_PHY_ADDR 3 409 #define TSEC1_PHYIDX 0 410 #define TSEC2_PHYIDX 0 411 #define TSEC3_PHYIDX 0 412 #define TSEC4_PHYIDX 0 413 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 414 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 415 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 416 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 417 418 #define CONFIG_ETHPRIME "eTSEC1" 419 420 #endif /* CONFIG_TSEC_ENET */ 421 422 /* 423 * BAT0 DDR 424 */ 425 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 426 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 427 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 428 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 429 430 /* 431 * BAT1 LBC (PIXIS/CF) 432 */ 433 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \ 434 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 435 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 436 | BATU_VS | BATU_VP) 437 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_LBC_BASE | BATL_PP_RW \ 438 | BATL_MEMCOHERENCE) 439 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 440 441 /* if CONFIG_PCI: 442 * BAT2 PCI1 and PCI1 MEM 443 * if CONFIG_RIO 444 * BAT2 Rapidio Memory 445 */ 446 #ifdef CONFIG_PCI 447 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ 448 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 449 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \ 450 | BATU_VS | BATU_VP) 451 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ 452 | BATL_CACHEINHIBIT) 453 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 454 #else /* CONFIG_RIO */ 455 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ 456 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 457 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 458 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 459 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 460 #endif 461 462 /* 463 * BAT3 CCSR Space 464 */ 465 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 466 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 467 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 468 | BATU_VP) 469 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 470 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 471 472 /* 473 * BAT4 PCI1_IO and PCI2_IO 474 */ 475 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ 476 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 477 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_128K \ 478 | BATU_VS | BATU_VP) 479 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 480 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 481 482 /* 483 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 484 */ 485 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 486 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 487 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 488 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 489 490 /* 491 * BAT6 FLASH 492 */ 493 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \ 494 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 495 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 496 | BATU_VP) 497 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \ 498 | BATL_MEMCOHERENCE) 499 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 500 501 /* Map the last 1M of flash where we're running from reset */ 502 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 503 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 504 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 505 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 506 | BATL_MEMCOHERENCE) 507 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 508 509 /* 510 * BAT7 FREE - used later for tmp mappings 511 */ 512 #define CONFIG_SYS_DBAT7L 0x00000000 513 #define CONFIG_SYS_DBAT7U 0x00000000 514 #define CONFIG_SYS_IBAT7L 0x00000000 515 #define CONFIG_SYS_IBAT7U 0x00000000 516 517 /* 518 * Environment 519 */ 520 #ifndef CONFIG_SYS_RAMBOOT 521 #define CONFIG_ENV_IS_IN_FLASH 1 522 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) 523 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 524 #else 525 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 526 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 527 #endif 528 #define CONFIG_ENV_SIZE 0x2000 529 530 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 531 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 532 533 534 /* 535 * BOOTP options 536 */ 537 #define CONFIG_BOOTP_BOOTFILESIZE 538 #define CONFIG_BOOTP_BOOTPATH 539 #define CONFIG_BOOTP_GATEWAY 540 #define CONFIG_BOOTP_HOSTNAME 541 542 543 /* 544 * Command line configuration. 545 */ 546 #include <config_cmd_default.h> 547 548 #define CONFIG_CMD_PING 549 #define CONFIG_CMD_I2C 550 #define CONFIG_CMD_REGINFO 551 552 #if defined(CONFIG_SYS_RAMBOOT) 553 #undef CONFIG_CMD_ENV 554 #endif 555 556 #if defined(CONFIG_PCI) 557 #define CONFIG_CMD_PCI 558 #define CONFIG_CMD_SCSI 559 #define CONFIG_CMD_EXT2 560 #define CONFIG_CMD_USB 561 #endif 562 563 564 #undef CONFIG_WATCHDOG /* watchdog disabled */ 565 566 /* 567 * Miscellaneous configurable options 568 */ 569 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 570 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 571 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 572 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 573 574 #if defined(CONFIG_CMD_KGDB) 575 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 576 #else 577 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 578 #endif 579 580 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 581 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 582 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 583 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 584 585 /* 586 * For booting Linux, the board info and command line data 587 * have to be in the first 8 MB of memory, since this is 588 * the maximum mapped by the Linux kernel during initialization. 589 */ 590 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 591 592 /* 593 * Internal Definitions 594 * 595 * Boot Flags 596 */ 597 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 598 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 599 600 #if defined(CONFIG_CMD_KGDB) 601 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 602 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 603 #endif 604 605 /* 606 * Environment Configuration 607 */ 608 609 /* The mac addresses for all ethernet interface */ 610 #if defined(CONFIG_TSEC_ENET) 611 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 612 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 613 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 614 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 615 #endif 616 617 #define CONFIG_HAS_ETH0 1 618 #define CONFIG_HAS_ETH1 1 619 #define CONFIG_HAS_ETH2 1 620 #define CONFIG_HAS_ETH3 1 621 622 #define CONFIG_IPADDR 192.168.1.100 623 624 #define CONFIG_HOSTNAME unknown 625 #define CONFIG_ROOTPATH /opt/nfsroot 626 #define CONFIG_BOOTFILE uImage 627 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 628 629 #define CONFIG_SERVERIP 192.168.1.1 630 #define CONFIG_GATEWAYIP 192.168.1.1 631 #define CONFIG_NETMASK 255.255.255.0 632 633 /* default location for tftp and bootm */ 634 #define CONFIG_LOADADDR 1000000 635 636 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 637 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 638 639 #define CONFIG_BAUDRATE 115200 640 641 #define CONFIG_EXTRA_ENV_SETTINGS \ 642 "netdev=eth0\0" \ 643 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 644 "tftpflash=tftpboot $loadaddr $uboot; " \ 645 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 646 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 647 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 648 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 649 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 650 "consoledev=ttyS0\0" \ 651 "ramdiskaddr=2000000\0" \ 652 "ramdiskfile=your.ramdisk.u-boot\0" \ 653 "fdtaddr=c00000\0" \ 654 "fdtfile=mpc8641_hpcn.dtb\0" \ 655 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 656 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 657 "maxcpus=2" 658 659 660 #define CONFIG_NFSBOOTCOMMAND \ 661 "setenv bootargs root=/dev/nfs rw " \ 662 "nfsroot=$serverip:$rootpath " \ 663 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 664 "console=$consoledev,$baudrate $othbootargs;" \ 665 "tftp $loadaddr $bootfile;" \ 666 "tftp $fdtaddr $fdtfile;" \ 667 "bootm $loadaddr - $fdtaddr" 668 669 #define CONFIG_RAMBOOTCOMMAND \ 670 "setenv bootargs root=/dev/ram rw " \ 671 "console=$consoledev,$baudrate $othbootargs;" \ 672 "tftp $ramdiskaddr $ramdiskfile;" \ 673 "tftp $loadaddr $bootfile;" \ 674 "tftp $fdtaddr $fdtfile;" \ 675 "bootm $loadaddr $ramdiskaddr $fdtaddr" 676 677 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 678 679 #endif /* __CONFIG_H */ 680