1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 42 #ifdef RUN_DIAG 43 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 44 #endif 45 46 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 47 48 /* 49 * virtual address to be used for temporary mappings. There 50 * should be 128k free at this VA. 51 */ 52 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 53 54 /* 55 * set this to enable Rapid IO. PCI and RIO are mutually exclusive 56 */ 57 /*#define CONFIG_RIO 1*/ 58 59 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ 60 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 61 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ 62 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ 63 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 65 #endif 66 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 67 68 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 69 #define CONFIG_ENV_OVERWRITE 70 71 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 72 73 #define CONFIG_ALTIVEC 1 74 75 /* 76 * L2CR setup -- make sure this is right for your board! 77 */ 78 #define CONFIG_SYS_L2 79 #define L2_INIT 0 80 #define L2_ENABLE (L2CR_L2E) 81 82 #ifndef CONFIG_SYS_CLK_FREQ 83 #ifndef __ASSEMBLY__ 84 extern unsigned long get_board_sys_clk(unsigned long dummy); 85 #endif 86 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 87 #endif 88 89 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 90 91 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 92 #define CONFIG_SYS_MEMTEST_END 0x00400000 93 94 /* 95 * Base addresses -- Note these are effective addresses where the 96 * actual resources get mapped (not physical addresses) 97 */ 98 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 99 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 100 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 101 102 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 103 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 104 105 /* 106 * DDR Setup 107 */ 108 #define CONFIG_FSL_DDR2 109 #undef CONFIG_FSL_DDR_INTERACTIVE 110 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 111 #define CONFIG_DDR_SPD 112 113 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 114 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 115 116 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 118 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 119 #define CONFIG_VERY_BIG_RAM 120 121 #define MPC86xx_DDR_SDRAM_CLK_CNTL 122 123 #define CONFIG_NUM_DDR_CONTROLLERS 2 124 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 125 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 126 127 /* 128 * I2C addresses of SPD EEPROMs 129 */ 130 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 131 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 132 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 133 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 134 135 136 /* 137 * These are used when DDR doesn't use SPD. 138 */ 139 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 140 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 141 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 142 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 143 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 144 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 145 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 146 #define CONFIG_SYS_DDR_MODE_1 0x00480432 147 #define CONFIG_SYS_DDR_MODE_2 0x00000000 148 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 149 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 150 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 151 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 152 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 153 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 154 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 155 156 #define CONFIG_ID_EEPROM 157 #define CONFIG_SYS_I2C_EEPROM_NXID 158 #define CONFIG_ID_EEPROM 159 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 161 162 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 163 164 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 165 166 /* Convert an address into the right format for the BR registers */ 167 #define BR_PHYS_ADDR(x) (x & 0xffff8000) 168 169 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \ 170 | 0x00001001) /* port size 16bit */ 171 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 172 173 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \ 174 | 0x00001001) /* port size 16bit */ 175 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 176 177 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \ 178 | 0x00000801) /* port size 8bit */ 179 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 180 181 182 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 183 #define PIXIS_BASE (CONFIG_SYS_CCSRBAR + 0x00100000) /* PIXIS registers */ 184 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 185 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 186 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 187 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 188 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 189 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 190 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 191 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 192 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 193 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 194 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 195 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 196 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 197 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 198 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 199 200 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 201 #define CF_BASE (PIXIS_BASE + 0x00100000) 202 203 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 204 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 205 206 #undef CONFIG_SYS_FLASH_CHECKSUM 207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 209 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 210 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 211 212 #define CONFIG_FLASH_CFI_DRIVER 213 #define CONFIG_SYS_FLASH_CFI 214 #define CONFIG_SYS_FLASH_EMPTY_INFO 215 216 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 217 #define CONFIG_SYS_RAMBOOT 218 #else 219 #undef CONFIG_SYS_RAMBOOT 220 #endif 221 222 #if defined(CONFIG_SYS_RAMBOOT) 223 #undef CONFIG_SPD_EEPROM 224 #define CONFIG_SYS_SDRAM_SIZE 256 225 #endif 226 227 #undef CONFIG_CLOCKS_IN_MHZ 228 229 #define CONFIG_L1_INIT_RAM 230 #define CONFIG_SYS_INIT_RAM_LOCK 1 231 #ifndef CONFIG_SYS_INIT_RAM_LOCK 232 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 233 #else 234 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 235 #endif 236 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 237 238 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 239 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 240 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 241 242 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 243 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 244 245 /* Serial Port */ 246 #define CONFIG_CONS_INDEX 1 247 #undef CONFIG_SERIAL_SOFTWARE_FIFO 248 #define CONFIG_SYS_NS16550 249 #define CONFIG_SYS_NS16550_SERIAL 250 #define CONFIG_SYS_NS16550_REG_SIZE 1 251 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 252 253 #define CONFIG_SYS_BAUDRATE_TABLE \ 254 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 255 256 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 257 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 258 259 /* Use the HUSH parser */ 260 #define CONFIG_SYS_HUSH_PARSER 261 #ifdef CONFIG_SYS_HUSH_PARSER 262 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 263 #endif 264 265 /* 266 * Pass open firmware flat tree to kernel 267 */ 268 #define CONFIG_OF_LIBFDT 1 269 #define CONFIG_OF_BOARD_SETUP 1 270 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 271 272 273 #define CONFIG_SYS_64BIT_VSPRINTF 1 274 #define CONFIG_SYS_64BIT_STRTOUL 1 275 276 /* 277 * I2C 278 */ 279 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 280 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 281 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 282 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 283 #define CONFIG_SYS_I2C_SLAVE 0x7F 284 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 285 #define CONFIG_SYS_I2C_OFFSET 0x3100 286 287 /* 288 * RapidIO MMU 289 */ 290 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ 291 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 292 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 293 294 /* 295 * General PCI 296 * Addresses are mapped 1-1. 297 */ 298 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 299 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 300 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 301 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 302 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 303 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 304 305 /* For RTL8139 */ 306 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 307 #define _IO_BASE 0x00000000 308 309 #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \ 310 + CONFIG_SYS_PCI1_MEM_SIZE) 311 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 312 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 313 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 314 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ 315 + CONFIG_SYS_PCI1_IO_SIZE) 316 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 317 318 #if defined(CONFIG_PCI) 319 320 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 321 322 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 323 324 #define CONFIG_NET_MULTI 325 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 326 327 #define CONFIG_RTL8139 328 329 #undef CONFIG_EEPRO100 330 #undef CONFIG_TULIP 331 332 /************************************************************ 333 * USB support 334 ************************************************************/ 335 #define CONFIG_PCI_OHCI 1 336 #define CONFIG_USB_OHCI_NEW 1 337 #define CONFIG_USB_KEYBOARD 1 338 #define CONFIG_SYS_DEVICE_DEREGISTER 339 #define CONFIG_SYS_USB_EVENT_POLL 1 340 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 341 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 342 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 343 344 /*PCIE video card used*/ 345 #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS 346 347 /*PCI video card used*/ 348 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ 349 350 /* video */ 351 #define CONFIG_VIDEO 352 353 #if defined(CONFIG_VIDEO) 354 #define CONFIG_BIOSEMU 355 #define CONFIG_CFB_CONSOLE 356 #define CONFIG_VIDEO_SW_CURSOR 357 #define CONFIG_VGA_AS_SINGLE_DEVICE 358 #define CONFIG_ATI_RADEON_FB 359 #define CONFIG_VIDEO_LOGO 360 /*#define CONFIG_CONSOLE_CURSOR*/ 361 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS 362 #endif 363 364 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 365 366 #define CONFIG_DOS_PARTITION 367 #define CONFIG_SCSI_AHCI 368 369 #ifdef CONFIG_SCSI_AHCI 370 #define CONFIG_SATA_ULI5288 371 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 372 #define CONFIG_SYS_SCSI_MAX_LUN 1 373 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 374 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 375 #endif 376 377 #define CONFIG_MPC86XX_PCI2 378 379 #endif /* CONFIG_PCI */ 380 381 #if defined(CONFIG_TSEC_ENET) 382 383 #ifndef CONFIG_NET_MULTI 384 #define CONFIG_NET_MULTI 1 385 #endif 386 387 #define CONFIG_MII 1 /* MII PHY management */ 388 389 #define CONFIG_TSEC1 1 390 #define CONFIG_TSEC1_NAME "eTSEC1" 391 #define CONFIG_TSEC2 1 392 #define CONFIG_TSEC2_NAME "eTSEC2" 393 #define CONFIG_TSEC3 1 394 #define CONFIG_TSEC3_NAME "eTSEC3" 395 #define CONFIG_TSEC4 1 396 #define CONFIG_TSEC4_NAME "eTSEC4" 397 398 #define TSEC1_PHY_ADDR 0 399 #define TSEC2_PHY_ADDR 1 400 #define TSEC3_PHY_ADDR 2 401 #define TSEC4_PHY_ADDR 3 402 #define TSEC1_PHYIDX 0 403 #define TSEC2_PHYIDX 0 404 #define TSEC3_PHYIDX 0 405 #define TSEC4_PHYIDX 0 406 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 407 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 408 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 409 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 410 411 #define CONFIG_ETHPRIME "eTSEC1" 412 413 #endif /* CONFIG_TSEC_ENET */ 414 415 /* 416 * BAT0 2G Cacheable, non-guarded 417 * 0x0000_0000 2G DDR 418 */ 419 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 420 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 421 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 422 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 423 424 /* 425 * BAT1 unused 426 */ 427 #define CONFIG_SYS_DBAT1L 0 428 #define CONFIG_SYS_DBAT1U 0 429 #define CONFIG_SYS_IBAT1L 0 430 #define CONFIG_SYS_IBAT1U 0 431 432 /* if CONFIG_PCI: 433 * BAT2 1G Cache-inhibited, guarded 434 * 0x8000_0000 512M PCI-Express 1 Memory 435 * 0xa000_0000 512M PCI-Express 2 Memory 436 * Changed it for operating from 0xd0000000 437 * 438 * if CONFIG_RIO 439 * BAT2 512M Cache-inhibited, guarded 440 * 0xc000_0000 512M RapidIO Memory 441 */ 442 #ifdef CONFIG_PCI 443 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ 444 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 445 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \ 446 | BATU_VS | BATU_VP) 447 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ 448 | BATL_CACHEINHIBIT) 449 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 450 #else /* CONFIG_RIO */ 451 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ 452 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 453 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 454 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 455 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 456 #endif 457 458 /* 459 * BAT3 4M Cache-inhibited, guarded 460 * 0xf800_0000 4M CCSR 461 */ 462 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 463 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 464 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 465 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 466 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 467 468 /* 469 * BAT4 32M Cache-inhibited, guarded 470 * 0xe200_0000 16M PCI-Express 1 I/O 471 * 0xe300_0000 16M PCI-Express 2 I/0 472 * Note that this is at 0xe0000000 473 */ 474 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ 475 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 476 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 477 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 478 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 479 480 /* 481 * BAT5 128K Cacheable, non-guarded 482 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 483 */ 484 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 485 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 486 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 487 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 488 489 /* 490 * BAT6 8M Cache-inhibited, guarded 491 * 0xff80_0000 8M FLASH 492 */ 493 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \ 494 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 495 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 496 | BATU_VP) 497 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \ 498 | BATL_MEMCOHERENCE) 499 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 500 501 /* Map the last 1M of flash where we're running from reset */ 502 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 503 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 504 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 505 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 506 | BATL_MEMCOHERENCE) 507 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 508 509 /* Leave BAT7 free here - it is used for various things later */ 510 #define CONFIG_SYS_DBAT7L 0x00000000 511 #define CONFIG_SYS_DBAT7U 0x00000000 512 #define CONFIG_SYS_IBAT7L 0x00000000 513 #define CONFIG_SYS_IBAT7U 0x00000000 514 515 /* 516 * Environment 517 */ 518 #ifndef CONFIG_SYS_RAMBOOT 519 #define CONFIG_ENV_IS_IN_FLASH 1 520 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) 521 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 522 #else 523 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 524 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 525 #endif 526 #define CONFIG_ENV_SIZE 0x2000 527 528 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 529 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 530 531 532 /* 533 * BOOTP options 534 */ 535 #define CONFIG_BOOTP_BOOTFILESIZE 536 #define CONFIG_BOOTP_BOOTPATH 537 #define CONFIG_BOOTP_GATEWAY 538 #define CONFIG_BOOTP_HOSTNAME 539 540 541 /* 542 * Command line configuration. 543 */ 544 #include <config_cmd_default.h> 545 546 #define CONFIG_CMD_PING 547 #define CONFIG_CMD_I2C 548 #define CONFIG_CMD_REGINFO 549 550 #if defined(CONFIG_SYS_RAMBOOT) 551 #undef CONFIG_CMD_ENV 552 #endif 553 554 #if defined(CONFIG_PCI) 555 #define CONFIG_CMD_PCI 556 #define CONFIG_CMD_SCSI 557 #define CONFIG_CMD_EXT2 558 #define CONFIG_CMD_USB 559 #endif 560 561 562 #undef CONFIG_WATCHDOG /* watchdog disabled */ 563 564 /* 565 * Miscellaneous configurable options 566 */ 567 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 568 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 569 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 570 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 571 572 #if defined(CONFIG_CMD_KGDB) 573 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 574 #else 575 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 576 #endif 577 578 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 579 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 580 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 581 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 582 583 /* 584 * For booting Linux, the board info and command line data 585 * have to be in the first 8 MB of memory, since this is 586 * the maximum mapped by the Linux kernel during initialization. 587 */ 588 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 589 590 /* 591 * Internal Definitions 592 * 593 * Boot Flags 594 */ 595 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 596 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 597 598 #if defined(CONFIG_CMD_KGDB) 599 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 600 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 601 #endif 602 603 /* 604 * Environment Configuration 605 */ 606 607 /* The mac addresses for all ethernet interface */ 608 #if defined(CONFIG_TSEC_ENET) 609 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 610 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 611 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 612 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 613 #endif 614 615 #define CONFIG_HAS_ETH0 1 616 #define CONFIG_HAS_ETH1 1 617 #define CONFIG_HAS_ETH2 1 618 #define CONFIG_HAS_ETH3 1 619 620 #define CONFIG_IPADDR 192.168.1.100 621 622 #define CONFIG_HOSTNAME unknown 623 #define CONFIG_ROOTPATH /opt/nfsroot 624 #define CONFIG_BOOTFILE uImage 625 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 626 627 #define CONFIG_SERVERIP 192.168.1.1 628 #define CONFIG_GATEWAYIP 192.168.1.1 629 #define CONFIG_NETMASK 255.255.255.0 630 631 /* default location for tftp and bootm */ 632 #define CONFIG_LOADADDR 1000000 633 634 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 635 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 636 637 #define CONFIG_BAUDRATE 115200 638 639 #define CONFIG_EXTRA_ENV_SETTINGS \ 640 "netdev=eth0\0" \ 641 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 642 "tftpflash=tftpboot $loadaddr $uboot; " \ 643 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 644 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 645 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 646 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 647 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 648 "consoledev=ttyS0\0" \ 649 "ramdiskaddr=2000000\0" \ 650 "ramdiskfile=your.ramdisk.u-boot\0" \ 651 "fdtaddr=c00000\0" \ 652 "fdtfile=mpc8641_hpcn.dtb\0" \ 653 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 654 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 655 "maxcpus=2" 656 657 658 #define CONFIG_NFSBOOTCOMMAND \ 659 "setenv bootargs root=/dev/nfs rw " \ 660 "nfsroot=$serverip:$rootpath " \ 661 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 662 "console=$consoledev,$baudrate $othbootargs;" \ 663 "tftp $loadaddr $bootfile;" \ 664 "tftp $fdtaddr $fdtfile;" \ 665 "bootm $loadaddr - $fdtaddr" 666 667 #define CONFIG_RAMBOOTCOMMAND \ 668 "setenv bootargs root=/dev/ram rw " \ 669 "console=$consoledev,$baudrate $othbootargs;" \ 670 "tftp $ramdiskaddr $ramdiskfile;" \ 671 "tftp $loadaddr $bootfile;" \ 672 "tftp $fdtaddr $fdtfile;" \ 673 "bootm $loadaddr $ramdiskaddr $fdtaddr" 674 675 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 676 677 #endif /* __CONFIG_H */ 678