1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 #undef DEBUG 42 43 #ifdef RUN_DIAG 44 #define CFG_DIAG_ADDR 0xff800000 45 #endif 46 47 #define CFG_RESET_ADDRESS 0xfff00100 48 49 #undef CONFIG_PCI 50 51 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 52 #define CONFIG_ENV_OVERWRITE 53 54 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 55 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 56 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 57 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 58 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 59 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 60 #define CONFIG_NUM_DDR_CONTROLLERS 2 61 /* #define CONFIG_DDR_INTERLEAVE 1 */ 62 #define CACHE_LINE_INTERLEAVING 0x20000000 63 #define PAGE_INTERLEAVING 0x21000000 64 #define BANK_INTERLEAVING 0x22000000 65 #define SUPER_BANK_INTERLEAVING 0x23000000 66 67 68 #define CONFIG_ALTIVEC 1 69 70 /* 71 * L2CR setup -- make sure this is right for your board! 72 */ 73 #define CFG_L2 74 #define L2_INIT 0 75 #define L2_ENABLE (L2CR_L2E) 76 77 #ifndef CONFIG_SYS_CLK_FREQ 78 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 79 #endif 80 81 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 82 83 #undef CFG_DRAM_TEST /* memory test, takes time */ 84 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 85 #define CFG_MEMTEST_END 0x00400000 86 87 88 /* 89 * Base addresses -- Note these are effective addresses where the 90 * actual resources get mapped (not physical addresses) 91 */ 92 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 93 #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 94 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 95 96 97 /* 98 * DDR Setup 99 */ 100 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 101 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 102 103 #define MPC86xx_DDR_SDRAM_CLK_CNTL 104 105 #if defined(CONFIG_SPD_EEPROM) 106 /* 107 * Determine DDR configuration from I2C interface. 108 */ 109 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 110 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 111 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 112 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 113 114 #else 115 /* 116 * Manually set up DDR1 parameters 117 */ 118 119 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 120 121 #define CFG_DDR_CS0_BNDS 0x0000000F 122 #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 123 #define CFG_DDR_EXT_REFRESH 0x00000000 124 #define CFG_DDR_TIMING_0 0x00260802 125 #define CFG_DDR_TIMING_1 0x39357322 126 #define CFG_DDR_TIMING_2 0x14904cc8 127 #define CFG_DDR_MODE_1 0x00480432 128 #define CFG_DDR_MODE_2 0x00000000 129 #define CFG_DDR_INTERVAL 0x06090100 130 #define CFG_DDR_DATA_INIT 0xdeadbeef 131 #define CFG_DDR_CLK_CTRL 0x03800000 132 #define CFG_DDR_OCD_CTRL 0x00000000 133 #define CFG_DDR_OCD_STATUS 0x00000000 134 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 135 #define CFG_DDR_CONTROL2 0x04400000 136 137 /* Not used in fixed_sdram function */ 138 139 #define CFG_DDR_MODE 0x00000022 140 #define CFG_DDR_CS1_BNDS 0x00000000 141 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 142 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 143 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 144 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 145 #endif 146 147 148 /* 149 * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. 150 * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff 151 * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. 152 * However, when u-boot comes up, the flash_init needs hard start addresses 153 * to build its info table. For user convenience, the flash addresses is 154 * fe800000 and ff800000. That way, u-boot knows where the flash is 155 * and the user can download u-boot code from promjet to fef00000, a 156 * more intuitive location than fe700000. 157 * 158 * Note that, on switching the boot location, fef00000 becomes fff00000. 159 */ 160 #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ 161 #define CFG_FLASH_BASE2 0xff800000 162 163 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 164 165 #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ 166 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ 167 168 #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ 169 #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ 170 171 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 172 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 173 174 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 175 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 176 177 178 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 179 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 180 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 181 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 182 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 183 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 184 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 185 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 186 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 187 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 188 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 189 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 190 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 191 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 192 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 193 194 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 195 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 196 197 #undef CFG_FLASH_CHECKSUM 198 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 199 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 200 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 201 202 #define CFG_FLASH_CFI_DRIVER 203 #define CFG_FLASH_CFI 204 #define CFG_FLASH_EMPTY_INFO 205 206 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 207 #define CFG_RAMBOOT 208 #else 209 #undef CFG_RAMBOOT 210 #endif 211 212 #if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT) 213 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 214 #endif 215 216 #undef CONFIG_CLOCKS_IN_MHZ 217 218 #define CONFIG_L1_INIT_RAM 219 #define CFG_INIT_RAM_LOCK 1 220 #ifndef CFG_INIT_RAM_LOCK 221 #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 222 #else 223 #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 224 #endif 225 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 226 227 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 228 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 229 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 230 231 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 232 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 233 234 /* Serial Port */ 235 #define CONFIG_CONS_INDEX 1 236 #undef CONFIG_SERIAL_SOFTWARE_FIFO 237 #define CFG_NS16550 238 #define CFG_NS16550_SERIAL 239 #define CFG_NS16550_REG_SIZE 1 240 #define CFG_NS16550_CLK get_bus_freq(0) 241 242 #define CFG_BAUDRATE_TABLE \ 243 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 244 245 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 246 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 247 248 /* Use the HUSH parser */ 249 #define CFG_HUSH_PARSER 250 #ifdef CFG_HUSH_PARSER 251 #define CFG_PROMPT_HUSH_PS2 "> " 252 #endif 253 254 /* 255 * Pass open firmware flat tree to kernel 256 */ 257 #define CONFIG_OF_FLAT_TREE 1 258 #define CONFIG_OF_BOARD_SETUP 1 259 260 /* maximum size of the flat tree (8K) */ 261 #define OF_FLAT_TREE_MAX_SIZE 8192 262 263 #define OF_CPU "PowerPC,8641@0" 264 #define OF_SOC "soc8641@f8000000" 265 #define OF_TBCLK (bd->bi_busfreq / 8) 266 #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" 267 268 #define CFG_64BIT_VSPRINTF 1 269 #define CFG_64BIT_STRTOUL 1 270 271 /* 272 * I2C 273 */ 274 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 275 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 276 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 277 #define CFG_I2C_SLAVE 0x7F 278 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 279 280 /* 281 * RapidIO MMU 282 */ 283 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 284 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 285 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 286 287 /* 288 * General PCI 289 * Addresses are mapped 1-1. 290 */ 291 #define CFG_PCI1_MEM_BASE 0x80000000 292 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 293 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 294 #define CFG_PCI1_IO_BASE 0xe2000000 295 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 296 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 297 298 /* For RTL8139 */ 299 #define _IO_BASE 0x00000000 300 301 #define CFG_PCI2_MEM_BASE 0xa0000000 302 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 303 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 304 #define CFG_PCI2_IO_BASE 0xe3000000 305 #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE 306 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ 307 308 309 #if defined(CONFIG_PCI) 310 311 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 312 313 #undef CFG_SCSI_SCAN_BUS_REVERSE 314 315 #define CONFIG_NET_MULTI 316 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 317 318 #define CONFIG_RTL8139 319 320 #undef CONFIG_EEPRO100 321 #undef CONFIG_TULIP 322 323 #if !defined(CONFIG_PCI_PNP) 324 #define PCI_ENET0_IOADDR 0xe0000000 325 #define PCI_ENET0_MEMADDR 0xe0000000 326 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 327 #endif 328 329 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 330 331 #endif /* CONFIG_PCI */ 332 333 334 #if defined(CONFIG_TSEC_ENET) 335 336 #ifndef CONFIG_NET_MULTI 337 #define CONFIG_NET_MULTI 1 338 #endif 339 340 #define CONFIG_MII 1 /* MII PHY management */ 341 342 #define CONFIG_MPC86XX_TSEC1 1 343 #define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" 344 #define CONFIG_MPC86XX_TSEC2 1 345 #define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" 346 #define CONFIG_MPC86XX_TSEC3 1 347 #define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" 348 #define CONFIG_MPC86XX_TSEC4 1 349 #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" 350 351 #define TSEC1_PHY_ADDR 0 352 #define TSEC2_PHY_ADDR 1 353 #define TSEC3_PHY_ADDR 2 354 #define TSEC4_PHY_ADDR 3 355 #define TSEC1_PHYIDX 0 356 #define TSEC2_PHYIDX 0 357 #define TSEC3_PHYIDX 0 358 #define TSEC4_PHYIDX 0 359 360 #define CONFIG_ETHPRIME "eTSEC1" 361 362 #endif /* CONFIG_TSEC_ENET */ 363 364 365 /* 366 * BAT0 2G Cacheable, non-guarded 367 * 0x0000_0000 2G DDR 368 */ 369 #define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ 370 | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) 371 #define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) 372 #define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) 373 #define CFG_IBAT0U CFG_DBAT0U 374 375 /* 376 * BAT1 1G Cache-inhibited, guarded 377 * 0x8000_0000 512M PCI-Express 1 Memory 378 * 0xa000_0000 512M PCI-Express 2 Memory 379 * Changed it for operating from 0xd0000000 380 */ 381 #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ 382 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 383 #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 384 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 385 #define CFG_IBAT1U CFG_DBAT1U 386 387 /* 388 * BAT2 512M Cache-inhibited, guarded 389 * 0xc000_0000 512M RapidIO Memory 390 */ 391 #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ 392 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 393 #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 394 #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 395 #define CFG_IBAT2U CFG_DBAT2U 396 397 /* 398 * BAT3 4M Cache-inhibited, guarded 399 * 0xf800_0000 4M CCSR 400 */ 401 #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ 402 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 403 #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 404 #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 405 #define CFG_IBAT3U CFG_DBAT3U 406 407 /* 408 * BAT4 32M Cache-inhibited, guarded 409 * 0xe200_0000 16M PCI-Express 1 I/O 410 * 0xe300_0000 16M PCI-Express 2 I/0 411 * Note that this is at 0xe0000000 412 */ 413 #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ 414 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 415 #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 416 #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 417 #define CFG_IBAT4U CFG_DBAT4U 418 419 /* 420 * BAT5 128K Cacheable, non-guarded 421 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 422 */ 423 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 424 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 425 #define CFG_IBAT5L CFG_DBAT5L 426 #define CFG_IBAT5U CFG_DBAT5U 427 428 /* 429 * BAT6 32M Cache-inhibited, guarded 430 * 0xfe00_0000 32M FLASH 431 */ 432 #define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ 433 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 434 #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 435 #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 436 #define CFG_IBAT6U CFG_DBAT6U 437 438 #define CFG_DBAT7L 0x00000000 439 #define CFG_DBAT7U 0x00000000 440 #define CFG_IBAT7L 0x00000000 441 #define CFG_IBAT7U 0x00000000 442 443 444 445 446 /* 447 * Environment 448 */ 449 #ifndef CFG_RAMBOOT 450 #define CFG_ENV_IS_IN_FLASH 1 451 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 452 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 453 #define CFG_ENV_SIZE 0x2000 454 #else 455 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 456 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 457 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 458 #define CFG_ENV_SIZE 0x2000 459 #endif 460 461 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 462 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 463 464 #if defined(CFG_RAMBOOT) 465 #if defined(CONFIG_PCI) 466 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 467 | CFG_CMD_PING \ 468 | CFG_CMD_PCI \ 469 | CFG_CMD_I2C) \ 470 & \ 471 ~(CFG_CMD_ENV \ 472 | CFG_CMD_IMLS \ 473 | CFG_CMD_FLASH \ 474 | CFG_CMD_LOADS)) 475 #else 476 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 477 | CFG_CMD_PING \ 478 | CFG_CMD_I2C) \ 479 & \ 480 ~(CFG_CMD_ENV \ 481 | CFG_CMD_IMLS \ 482 | CFG_CMD_FLASH \ 483 | CFG_CMD_LOADS)) 484 #endif 485 #else 486 #if defined(CONFIG_PCI) 487 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 488 | CFG_CMD_PCI \ 489 | CFG_CMD_PING \ 490 | CFG_CMD_I2C) 491 #else 492 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 493 | CFG_CMD_PING \ 494 | CFG_CMD_I2C) 495 #endif 496 #endif 497 498 #include <cmd_confdefs.h> 499 500 #undef CONFIG_WATCHDOG /* watchdog disabled */ 501 502 /* 503 * Miscellaneous configurable options 504 */ 505 #define CFG_LONGHELP /* undef to save memory */ 506 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 507 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 508 509 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 510 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 511 #else 512 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 513 #endif 514 515 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 516 #define CFG_MAXARGS 16 /* max number of command args */ 517 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 518 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 519 520 /* 521 * For booting Linux, the board info and command line data 522 * have to be in the first 8 MB of memory, since this is 523 * the maximum mapped by the Linux kernel during initialization. 524 */ 525 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 526 527 /* Cache Configuration */ 528 #define CFG_DCACHE_SIZE 32768 529 #define CFG_CACHELINE_SIZE 32 530 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 531 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 532 #endif 533 534 /* 535 * Internal Definitions 536 * 537 * Boot Flags 538 */ 539 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 540 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 541 542 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 543 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 544 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 545 #endif 546 547 548 /* 549 * Environment Configuration 550 */ 551 552 /* The mac addresses for all ethernet interface */ 553 #if defined(CONFIG_TSEC_ENET) 554 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 555 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 556 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 557 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 558 #endif 559 560 #define CONFIG_HAS_ETH1 1 561 #define CONFIG_HAS_ETH2 1 562 #define CONFIG_HAS_ETH3 1 563 564 #define CONFIG_IPADDR 192.168.1.100 565 566 #define CONFIG_HOSTNAME unknown 567 #define CONFIG_ROOTPATH /opt/nfsroot 568 #define CONFIG_BOOTFILE uImage 569 570 #define CONFIG_SERVERIP 192.168.1.1 571 #define CONFIG_GATEWAYIP 192.168.1.1 572 #define CONFIG_NETMASK 255.255.255.0 573 574 /* default location for tftp and bootm */ 575 #define CONFIG_LOADADDR 1000000 576 577 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 578 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 579 580 #define CONFIG_BAUDRATE 115200 581 582 #define CONFIG_EXTRA_ENV_SETTINGS \ 583 "netdev=eth0\0" \ 584 "consoledev=ttyS0\0" \ 585 "ramdiskaddr=400000\0" \ 586 "ramdiskfile=your.ramdisk.u-boot\0" \ 587 "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ 588 "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ 589 "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ 590 "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ 591 "pex=run pexstat; run pex1; run pexd\0" \ 592 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 593 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 594 "maxcpus=2" 595 596 597 #define CONFIG_NFSBOOTCOMMAND \ 598 "setenv bootargs root=/dev/nfs rw " \ 599 "nfsroot=$serverip:$rootpath " \ 600 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 601 "console=$consoledev,$baudrate $othbootargs;" \ 602 "tftp $loadaddr $bootfile;" \ 603 "bootm $loadaddr" 604 605 #define CONFIG_RAMBOOTCOMMAND \ 606 "setenv bootargs root=/dev/ram rw " \ 607 "console=$consoledev,$baudrate $othbootargs;" \ 608 "tftp $ramdiskaddr $ramdiskfile;" \ 609 "tftp $loadaddr $bootfile;" \ 610 "bootm $loadaddr $ramdiskaddr" 611 612 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 613 614 #endif /* __CONFIG_H */ 615