1 /* 2 * Copyright 2006, 2010-2011 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * MPC8641HPCN board configuration file 11 * 12 * Make sure you change the MAC address and other network params first, 13 * search for CONFIG_SERVERIP, etc. in this file. 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MP 1 /* support multiple processors */ 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 23 24 /* 25 * default CCSRBAR is at 0xff700000 26 * assume U-Boot is less than 0.5MB 27 */ 28 #define CONFIG_SYS_TEXT_BASE 0xeff00000 29 30 #ifdef RUN_DIAG 31 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 32 #endif 33 34 /* 35 * virtual address to be used for temporary mappings. There 36 * should be 128k free at this VA. 37 */ 38 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 39 40 #define CONFIG_SYS_SRIO 41 #define CONFIG_SRIO1 /* SRIO port 1 */ 42 43 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ 44 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ 45 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 48 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 52 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 53 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 54 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 55 56 #define CONFIG_ALTIVEC 1 57 58 /* 59 * L2CR setup -- make sure this is right for your board! 60 */ 61 #define CONFIG_SYS_L2 62 #define L2_INIT 0 63 #define L2_ENABLE (L2CR_L2E) 64 65 #ifndef CONFIG_SYS_CLK_FREQ 66 #ifndef __ASSEMBLY__ 67 extern unsigned long get_board_sys_clk(unsigned long dummy); 68 #endif 69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 70 #endif 71 72 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 73 #define CONFIG_SYS_MEMTEST_END 0x00400000 74 75 /* 76 * With the exception of PCI Memory and Rapid IO, most devices will simply 77 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 78 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 79 */ 80 #ifdef CONFIG_PHYS_64BIT 81 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f 82 #else 83 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 84 #endif 85 86 /* 87 * Base addresses -- Note these are effective addresses where the 88 * actual resources get mapped (not physical addresses) 89 */ 90 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 91 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 92 93 /* Physical addresses */ 94 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 95 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH 96 #define CONFIG_SYS_CCSRBAR_PHYS \ 97 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 98 CONFIG_SYS_CCSRBAR_PHYS_HIGH) 99 100 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 101 102 /* 103 * DDR Setup 104 */ 105 #define CONFIG_SYS_FSL_DDR2 106 #undef CONFIG_FSL_DDR_INTERACTIVE 107 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 108 #define CONFIG_DDR_SPD 109 110 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 111 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 112 113 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 114 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 115 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 116 #define CONFIG_VERY_BIG_RAM 117 118 #define CONFIG_NUM_DDR_CONTROLLERS 2 119 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 120 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 121 122 /* 123 * I2C addresses of SPD EEPROMs 124 */ 125 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 126 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 127 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 128 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 129 130 /* 131 * These are used when DDR doesn't use SPD. 132 */ 133 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 134 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 135 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 136 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 137 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 138 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 139 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 140 #define CONFIG_SYS_DDR_MODE_1 0x00480432 141 #define CONFIG_SYS_DDR_MODE_2 0x00000000 142 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 143 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 144 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 145 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 146 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 147 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 148 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 149 150 #define CONFIG_ID_EEPROM 151 #define CONFIG_SYS_I2C_EEPROM_NXID 152 #define CONFIG_ID_EEPROM 153 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 155 156 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 157 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE 158 #define CONFIG_SYS_FLASH_BASE_PHYS \ 159 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 160 CONFIG_SYS_PHYS_ADDR_HIGH) 161 162 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 163 164 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 165 | 0x00001001) /* port size 16bit */ 166 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 167 168 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 169 | 0x00001001) /* port size 16bit */ 170 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 171 172 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 173 | 0x00000801) /* port size 8bit */ 174 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 175 176 /* 177 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 178 * The PIXIS and CF by themselves aren't large enough to take up the 128k 179 * required for the smallest BAT mapping, so there's a 64k hole. 180 */ 181 #define CONFIG_SYS_LBC_BASE 0xffde0000 182 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE 183 184 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 185 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 186 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) 187 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ 188 CONFIG_SYS_PHYS_ADDR_HIGH) 189 #define PIXIS_SIZE 0x00008000 /* 32k */ 190 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 191 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 192 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 193 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 194 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 195 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 196 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 197 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 198 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 199 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 200 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 201 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 202 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 203 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 204 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 205 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 206 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 207 208 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 209 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 210 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 211 212 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 213 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 214 215 #undef CONFIG_SYS_FLASH_CHECKSUM 216 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 219 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 220 221 #define CONFIG_FLASH_CFI_DRIVER 222 #define CONFIG_SYS_FLASH_CFI 223 #define CONFIG_SYS_FLASH_EMPTY_INFO 224 225 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 226 #define CONFIG_SYS_RAMBOOT 227 #else 228 #undef CONFIG_SYS_RAMBOOT 229 #endif 230 231 #if defined(CONFIG_SYS_RAMBOOT) 232 #undef CONFIG_SPD_EEPROM 233 #define CONFIG_SYS_SDRAM_SIZE 256 234 #endif 235 236 #undef CONFIG_CLOCKS_IN_MHZ 237 238 #define CONFIG_SYS_INIT_RAM_LOCK 1 239 #ifndef CONFIG_SYS_INIT_RAM_LOCK 240 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 241 #else 242 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 243 #endif 244 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 245 246 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 247 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 248 249 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 250 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 251 252 /* Serial Port */ 253 #define CONFIG_CONS_INDEX 1 254 #define CONFIG_SYS_NS16550_SERIAL 255 #define CONFIG_SYS_NS16550_REG_SIZE 1 256 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 257 258 #define CONFIG_SYS_BAUDRATE_TABLE \ 259 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 260 261 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 262 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 263 264 /* 265 * I2C 266 */ 267 #define CONFIG_SYS_I2C 268 #define CONFIG_SYS_I2C_FSL 269 #define CONFIG_SYS_FSL_I2C_SPEED 400000 270 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 271 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 272 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 273 274 /* 275 * RapidIO MMU 276 */ 277 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 280 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c 281 #else 282 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE 283 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 284 #endif 285 #define CONFIG_SYS_SRIO1_MEM_PHYS \ 286 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 287 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) 288 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 289 290 /* 291 * General PCI 292 * Addresses are mapped 1-1. 293 */ 294 295 #define CONFIG_SYS_PCIE1_NAME "ULI" 296 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 297 #ifdef CONFIG_PHYS_64BIT 298 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 299 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 300 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c 301 #else 302 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 303 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT 304 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 305 #endif 306 #define CONFIG_SYS_PCIE1_MEM_PHYS \ 307 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 308 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) 309 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 310 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 311 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 312 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT 313 #define CONFIG_SYS_PCIE1_IO_PHYS \ 314 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 315 CONFIG_SYS_PHYS_ADDR_HIGH) 316 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 317 318 #ifdef CONFIG_PHYS_64BIT 319 /* 320 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 321 * This will increase the amount of PCI address space available for 322 * for mapping RAM. 323 */ 324 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 325 #else 326 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 327 + CONFIG_SYS_PCIE1_MEM_SIZE) 328 #endif 329 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 330 + CONFIG_SYS_PCIE1_MEM_SIZE) 331 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ 332 + CONFIG_SYS_PCIE1_MEM_SIZE) 333 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 334 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 335 + CONFIG_SYS_PCIE1_MEM_SIZE) 336 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 337 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 338 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 339 + CONFIG_SYS_PCIE1_IO_SIZE) 340 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ 341 + CONFIG_SYS_PCIE1_IO_SIZE) 342 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 343 + CONFIG_SYS_PCIE1_IO_SIZE) 344 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 345 346 #if defined(CONFIG_PCI) 347 348 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 349 350 #undef CONFIG_EEPRO100 351 #undef CONFIG_TULIP 352 353 /************************************************************ 354 * USB support 355 ************************************************************/ 356 #define CONFIG_PCI_OHCI 1 357 #define CONFIG_USB_OHCI_NEW 1 358 #define CONFIG_SYS_USB_EVENT_POLL 1 359 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 360 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 361 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 362 363 /*PCIE video card used*/ 364 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 365 366 /*PCI video card used*/ 367 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 368 369 /* video */ 370 371 #if defined(CONFIG_VIDEO) 372 #define CONFIG_BIOSEMU 373 #define CONFIG_ATI_RADEON_FB 374 #define CONFIG_VIDEO_LOGO 375 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 376 #endif 377 378 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 379 380 #define CONFIG_DOS_PARTITION 381 #define CONFIG_SCSI_AHCI 382 383 #ifdef CONFIG_SCSI_AHCI 384 #define CONFIG_LIBATA 385 #define CONFIG_SATA_ULI5288 386 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 387 #define CONFIG_SYS_SCSI_MAX_LUN 1 388 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 389 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 390 #endif 391 392 #endif /* CONFIG_PCI */ 393 394 #if defined(CONFIG_TSEC_ENET) 395 396 #define CONFIG_MII 1 /* MII PHY management */ 397 398 #define CONFIG_TSEC1 1 399 #define CONFIG_TSEC1_NAME "eTSEC1" 400 #define CONFIG_TSEC2 1 401 #define CONFIG_TSEC2_NAME "eTSEC2" 402 #define CONFIG_TSEC3 1 403 #define CONFIG_TSEC3_NAME "eTSEC3" 404 #define CONFIG_TSEC4 1 405 #define CONFIG_TSEC4_NAME "eTSEC4" 406 407 #define TSEC1_PHY_ADDR 0 408 #define TSEC2_PHY_ADDR 1 409 #define TSEC3_PHY_ADDR 2 410 #define TSEC4_PHY_ADDR 3 411 #define TSEC1_PHYIDX 0 412 #define TSEC2_PHYIDX 0 413 #define TSEC3_PHYIDX 0 414 #define TSEC4_PHYIDX 0 415 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 416 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 417 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 419 420 #define CONFIG_ETHPRIME "eTSEC1" 421 422 #endif /* CONFIG_TSEC_ENET */ 423 424 #ifdef CONFIG_PHYS_64BIT 425 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 426 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 427 428 /* Put physical address into the BAT format */ 429 #define BAT_PHYS_ADDR(low, high) \ 430 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) 431 /* Convert high/low pairs to actual 64-bit value */ 432 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) 433 #else 434 /* 32-bit systems just ignore the "high" bits */ 435 #define BAT_PHYS_ADDR(low, high) (low) 436 #define PAIRED_PHYS_TO_PHYS(low, high) (low) 437 #endif 438 439 /* 440 * BAT0 DDR 441 */ 442 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 443 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 444 445 /* 446 * BAT1 LBC (PIXIS/CF) 447 */ 448 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 449 CONFIG_SYS_PHYS_ADDR_HIGH) \ 450 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 451 BATL_GUARDEDSTORAGE) 452 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 453 | BATU_VS | BATU_VP) 454 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 455 CONFIG_SYS_PHYS_ADDR_HIGH) \ 456 | BATL_PP_RW | BATL_MEMCOHERENCE) 457 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 458 459 /* if CONFIG_PCI: 460 * BAT2 PCIE1 and PCIE1 MEM 461 * if CONFIG_RIO 462 * BAT2 Rapidio Memory 463 */ 464 #ifdef CONFIG_PCI 465 #define CONFIG_PCI_INDIRECT_BRIDGE 466 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 467 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 468 | BATL_PP_RW | BATL_CACHEINHIBIT \ 469 | BATL_GUARDEDSTORAGE) 470 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 471 | BATU_VS | BATU_VP) 472 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 473 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 474 | BATL_PP_RW | BATL_CACHEINHIBIT) 475 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 476 #else /* CONFIG_RIO */ 477 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 478 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 479 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 480 BATL_GUARDEDSTORAGE) 481 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ 482 | BATU_VS | BATU_VP) 483 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 484 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 485 | BATL_PP_RW | BATL_CACHEINHIBIT) 486 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 487 #endif 488 489 /* 490 * BAT3 CCSR Space 491 */ 492 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 493 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 494 | BATL_PP_RW | BATL_CACHEINHIBIT \ 495 | BATL_GUARDEDSTORAGE) 496 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 497 | BATU_VP) 498 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 499 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 500 | BATL_PP_RW | BATL_CACHEINHIBIT) 501 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 502 503 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 504 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 505 | BATL_PP_RW | BATL_CACHEINHIBIT \ 506 | BATL_GUARDEDSTORAGE) 507 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 508 | BATU_BL_1M | BATU_VS | BATU_VP) 509 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 510 | BATL_PP_RW | BATL_CACHEINHIBIT) 511 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 512 #endif 513 514 /* 515 * BAT4 PCIE1_IO and PCIE2_IO 516 */ 517 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 518 CONFIG_SYS_PHYS_ADDR_HIGH) \ 519 | BATL_PP_RW | BATL_CACHEINHIBIT \ 520 | BATL_GUARDEDSTORAGE) 521 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 522 | BATU_VS | BATU_VP) 523 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 524 CONFIG_SYS_PHYS_ADDR_HIGH) \ 525 | BATL_PP_RW | BATL_CACHEINHIBIT) 526 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 527 528 /* 529 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 530 */ 531 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 532 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 533 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 534 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 535 536 /* 537 * BAT6 FLASH 538 */ 539 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 540 CONFIG_SYS_PHYS_ADDR_HIGH) \ 541 | BATL_PP_RW | BATL_CACHEINHIBIT \ 542 | BATL_GUARDEDSTORAGE) 543 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 544 | BATU_VP) 545 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 546 CONFIG_SYS_PHYS_ADDR_HIGH) \ 547 | BATL_PP_RW | BATL_MEMCOHERENCE) 548 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 549 550 /* Map the last 1M of flash where we're running from reset */ 551 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 552 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 553 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 554 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 555 | BATL_MEMCOHERENCE) 556 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 557 558 /* 559 * BAT7 FREE - used later for tmp mappings 560 */ 561 #define CONFIG_SYS_DBAT7L 0x00000000 562 #define CONFIG_SYS_DBAT7U 0x00000000 563 #define CONFIG_SYS_IBAT7L 0x00000000 564 #define CONFIG_SYS_IBAT7U 0x00000000 565 566 /* 567 * Environment 568 */ 569 #ifndef CONFIG_SYS_RAMBOOT 570 #define CONFIG_ENV_IS_IN_FLASH 1 571 #define CONFIG_ENV_ADDR \ 572 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 573 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 574 #else 575 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 576 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 577 #endif 578 #define CONFIG_ENV_SIZE 0x2000 579 580 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 581 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 582 583 /* 584 * BOOTP options 585 */ 586 #define CONFIG_BOOTP_BOOTFILESIZE 587 #define CONFIG_BOOTP_BOOTPATH 588 #define CONFIG_BOOTP_GATEWAY 589 #define CONFIG_BOOTP_HOSTNAME 590 591 /* 592 * Command line configuration. 593 */ 594 #define CONFIG_CMD_REGINFO 595 596 #if defined(CONFIG_PCI) 597 #define CONFIG_CMD_PCI 598 #define CONFIG_SCSI 599 #endif 600 601 #undef CONFIG_WATCHDOG /* watchdog disabled */ 602 603 /* 604 * Miscellaneous configurable options 605 */ 606 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 607 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 608 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 609 610 #if defined(CONFIG_CMD_KGDB) 611 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 612 #else 613 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 614 #endif 615 616 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 617 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 618 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 619 620 /* 621 * For booting Linux, the board info and command line data 622 * have to be in the first 8 MB of memory, since this is 623 * the maximum mapped by the Linux kernel during initialization. 624 */ 625 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 626 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 627 628 #if defined(CONFIG_CMD_KGDB) 629 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 630 #endif 631 632 /* 633 * Environment Configuration 634 */ 635 636 #define CONFIG_HAS_ETH0 1 637 #define CONFIG_HAS_ETH1 1 638 #define CONFIG_HAS_ETH2 1 639 #define CONFIG_HAS_ETH3 1 640 641 #define CONFIG_IPADDR 192.168.1.100 642 643 #define CONFIG_HOSTNAME unknown 644 #define CONFIG_ROOTPATH "/opt/nfsroot" 645 #define CONFIG_BOOTFILE "uImage" 646 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 647 648 #define CONFIG_SERVERIP 192.168.1.1 649 #define CONFIG_GATEWAYIP 192.168.1.1 650 #define CONFIG_NETMASK 255.255.255.0 651 652 /* default location for tftp and bootm */ 653 #define CONFIG_LOADADDR 0x10000000 654 655 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 656 657 #define CONFIG_BAUDRATE 115200 658 659 #define CONFIG_EXTRA_ENV_SETTINGS \ 660 "netdev=eth0\0" \ 661 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 662 "tftpflash=tftpboot $loadaddr $uboot; " \ 663 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 664 " +$filesize; " \ 665 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 666 " +$filesize; " \ 667 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 668 " $filesize; " \ 669 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 670 " +$filesize; " \ 671 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 672 " $filesize\0" \ 673 "consoledev=ttyS0\0" \ 674 "ramdiskaddr=0x18000000\0" \ 675 "ramdiskfile=your.ramdisk.u-boot\0" \ 676 "fdtaddr=0x17c00000\0" \ 677 "fdtfile=mpc8641_hpcn.dtb\0" \ 678 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 679 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 680 "maxcpus=2" 681 682 #define CONFIG_NFSBOOTCOMMAND \ 683 "setenv bootargs root=/dev/nfs rw " \ 684 "nfsroot=$serverip:$rootpath " \ 685 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 686 "console=$consoledev,$baudrate $othbootargs;" \ 687 "tftp $loadaddr $bootfile;" \ 688 "tftp $fdtaddr $fdtfile;" \ 689 "bootm $loadaddr - $fdtaddr" 690 691 #define CONFIG_RAMBOOTCOMMAND \ 692 "setenv bootargs root=/dev/ram rw " \ 693 "console=$consoledev,$baudrate $othbootargs;" \ 694 "tftp $ramdiskaddr $ramdiskfile;" \ 695 "tftp $loadaddr $bootfile;" \ 696 "tftp $fdtaddr $fdtfile;" \ 697 "bootm $loadaddr $ramdiskaddr $fdtaddr" 698 699 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 700 701 #endif /* __CONFIG_H */ 702