1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ 42 43 #ifdef RUN_DIAG 44 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 45 #endif 46 47 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 48 49 /* 50 * virtual address to be used for temporary mappings. There 51 * should be 128k free at this VA. 52 */ 53 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 54 55 /* 56 * set this to enable Rapid IO. PCI and RIO are mutually exclusive 57 */ 58 /*#define CONFIG_RIO 1*/ 59 60 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ 61 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 62 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ 63 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ 64 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 65 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 66 #endif 67 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 68 69 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 70 #define CONFIG_ENV_OVERWRITE 71 72 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 73 74 #define CONFIG_ALTIVEC 1 75 76 /* 77 * L2CR setup -- make sure this is right for your board! 78 */ 79 #define CONFIG_SYS_L2 80 #define L2_INIT 0 81 #define L2_ENABLE (L2CR_L2E) 82 83 #ifndef CONFIG_SYS_CLK_FREQ 84 #ifndef __ASSEMBLY__ 85 extern unsigned long get_board_sys_clk(unsigned long dummy); 86 #endif 87 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 88 #endif 89 90 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 91 92 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 93 #define CONFIG_SYS_MEMTEST_END 0x00400000 94 95 /* 96 * With the exception of PCI Memory and Rapid IO, most devices will simply 97 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 98 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 99 */ 100 #ifdef CONFIG_PHYS_64BIT 101 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL 102 #else 103 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 104 #endif 105 106 /* 107 * Base addresses -- Note these are effective addresses where the 108 * actual resources get mapped (not physical addresses) 109 */ 110 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 111 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 112 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 113 114 /* Physical addresses */ 115 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 118 #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 119 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) 120 #else 121 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 122 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 123 #endif 124 125 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 126 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 127 128 /* 129 * DDR Setup 130 */ 131 #define CONFIG_FSL_DDR2 132 #undef CONFIG_FSL_DDR_INTERACTIVE 133 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 134 #define CONFIG_DDR_SPD 135 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 137 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 138 139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 141 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 142 #define CONFIG_VERY_BIG_RAM 143 144 #define MPC86xx_DDR_SDRAM_CLK_CNTL 145 146 #define CONFIG_NUM_DDR_CONTROLLERS 2 147 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 148 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 149 150 /* 151 * I2C addresses of SPD EEPROMs 152 */ 153 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 154 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 155 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 156 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 157 158 159 /* 160 * These are used when DDR doesn't use SPD. 161 */ 162 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 163 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 164 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 165 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 166 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 167 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 168 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 169 #define CONFIG_SYS_DDR_MODE_1 0x00480432 170 #define CONFIG_SYS_DDR_MODE_2 0x00000000 171 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 172 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 173 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 174 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 175 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 176 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 177 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 178 179 #define CONFIG_ID_EEPROM 180 #define CONFIG_SYS_I2C_EEPROM_NXID 181 #define CONFIG_ID_EEPROM 182 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 184 185 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 186 #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ 187 | CONFIG_SYS_PHYS_ADDR_HIGH) 188 189 190 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 191 192 /* Convert an address into the right format for the BR registers */ 193 #ifdef CONFIG_PHYS_64BIT 194 #define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ 195 ((x & 0x300000000ULL) >> 19))) 196 #else 197 #define BR_PHYS_ADDR(x) (x & 0xffff8000) 198 #endif 199 200 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 201 | 0x00001001) /* port size 16bit */ 202 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 203 204 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 205 | 0x00001001) /* port size 16bit */ 206 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 207 208 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 209 | 0x00000801) /* port size 8bit */ 210 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 211 212 /* 213 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 214 * The PIXIS and CF by themselves aren't large enough to take up the 128k 215 * required for the smallest BAT mapping, so there's a 64k hole. 216 */ 217 #define CONFIG_SYS_LBC_BASE 0xffde0000 218 #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ 219 | CONFIG_SYS_PHYS_ADDR_HIGH) 220 221 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 222 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 223 #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) 224 #define PIXIS_SIZE 0x00008000 /* 32k */ 225 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 226 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 227 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 228 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 229 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 230 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 231 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 232 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 233 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 234 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 235 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 236 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 237 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 238 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 239 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 240 241 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 242 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 243 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 244 245 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 246 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 247 248 #undef CONFIG_SYS_FLASH_CHECKSUM 249 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 250 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 251 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 252 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 253 254 #define CONFIG_FLASH_CFI_DRIVER 255 #define CONFIG_SYS_FLASH_CFI 256 #define CONFIG_SYS_FLASH_EMPTY_INFO 257 258 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 259 #define CONFIG_SYS_RAMBOOT 260 #else 261 #undef CONFIG_SYS_RAMBOOT 262 #endif 263 264 #if defined(CONFIG_SYS_RAMBOOT) 265 #undef CONFIG_SPD_EEPROM 266 #define CONFIG_SYS_SDRAM_SIZE 256 267 #endif 268 269 #undef CONFIG_CLOCKS_IN_MHZ 270 271 #define CONFIG_SYS_INIT_RAM_LOCK 1 272 #ifndef CONFIG_SYS_INIT_RAM_LOCK 273 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 274 #else 275 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 276 #endif 277 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 278 279 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 280 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 281 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 282 283 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 284 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 285 286 /* Serial Port */ 287 #define CONFIG_CONS_INDEX 1 288 #undef CONFIG_SERIAL_SOFTWARE_FIFO 289 #define CONFIG_SYS_NS16550 290 #define CONFIG_SYS_NS16550_SERIAL 291 #define CONFIG_SYS_NS16550_REG_SIZE 1 292 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 293 294 #define CONFIG_SYS_BAUDRATE_TABLE \ 295 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 296 297 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 298 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 299 300 /* Use the HUSH parser */ 301 #define CONFIG_SYS_HUSH_PARSER 302 #ifdef CONFIG_SYS_HUSH_PARSER 303 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 304 #endif 305 306 /* 307 * Pass open firmware flat tree to kernel 308 */ 309 #define CONFIG_OF_LIBFDT 1 310 #define CONFIG_OF_BOARD_SETUP 1 311 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 312 313 314 #define CONFIG_SYS_64BIT_VSPRINTF 1 315 #define CONFIG_SYS_64BIT_STRTOUL 1 316 317 /* 318 * I2C 319 */ 320 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 321 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 322 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 323 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 324 #define CONFIG_SYS_I2C_SLAVE 0x7F 325 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 326 #define CONFIG_SYS_I2C_OFFSET 0x3100 327 328 /* 329 * RapidIO MMU 330 */ 331 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ 332 #ifdef CONFIG_PHYS_64BIT 333 #define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL 334 #else 335 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 336 #endif 337 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 338 339 /* 340 * General PCI 341 * Addresses are mapped 1-1. 342 */ 343 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 344 #ifdef CONFIG_PHYS_64BIT 345 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL 346 #else 347 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 348 #endif 349 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 350 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 351 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 352 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ 353 | CONFIG_SYS_PHYS_ADDR_HIGH) 354 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ 355 356 /* For RTL8139 */ 357 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 358 #define _IO_BASE 0x00000000 359 360 #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \ 361 + CONFIG_SYS_PCI1_MEM_SIZE) 362 #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ 363 + CONFIG_SYS_PCI1_MEM_SIZE) 364 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 365 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 366 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ 367 + CONFIG_SYS_PCI1_IO_SIZE) 368 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ 369 + CONFIG_SYS_PCI1_IO_SIZE) 370 #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE 371 372 #if defined(CONFIG_PCI) 373 374 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 375 376 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 377 378 #define CONFIG_NET_MULTI 379 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 380 381 #define CONFIG_RTL8139 382 383 #undef CONFIG_EEPRO100 384 #undef CONFIG_TULIP 385 386 /************************************************************ 387 * USB support 388 ************************************************************/ 389 #define CONFIG_PCI_OHCI 1 390 #define CONFIG_USB_OHCI_NEW 1 391 #define CONFIG_USB_KEYBOARD 1 392 #define CONFIG_SYS_DEVICE_DEREGISTER 393 #define CONFIG_SYS_USB_EVENT_POLL 1 394 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 395 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 396 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 397 398 /*PCIE video card used*/ 399 #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT 400 401 /*PCI video card used*/ 402 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 403 404 /* video */ 405 #define CONFIG_VIDEO 406 407 #if defined(CONFIG_VIDEO) 408 #define CONFIG_BIOSEMU 409 #define CONFIG_CFB_CONSOLE 410 #define CONFIG_VIDEO_SW_CURSOR 411 #define CONFIG_VGA_AS_SINGLE_DEVICE 412 #define CONFIG_ATI_RADEON_FB 413 #define CONFIG_VIDEO_LOGO 414 /*#define CONFIG_CONSOLE_CURSOR*/ 415 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT 416 #endif 417 418 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 419 420 #define CONFIG_DOS_PARTITION 421 #define CONFIG_SCSI_AHCI 422 423 #ifdef CONFIG_SCSI_AHCI 424 #define CONFIG_SATA_ULI5288 425 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 426 #define CONFIG_SYS_SCSI_MAX_LUN 1 427 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 428 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 429 #endif 430 431 #define CONFIG_MPC86XX_PCI2 432 433 #endif /* CONFIG_PCI */ 434 435 #if defined(CONFIG_TSEC_ENET) 436 437 #ifndef CONFIG_NET_MULTI 438 #define CONFIG_NET_MULTI 1 439 #endif 440 441 #define CONFIG_MII 1 /* MII PHY management */ 442 443 #define CONFIG_TSEC1 1 444 #define CONFIG_TSEC1_NAME "eTSEC1" 445 #define CONFIG_TSEC2 1 446 #define CONFIG_TSEC2_NAME "eTSEC2" 447 #define CONFIG_TSEC3 1 448 #define CONFIG_TSEC3_NAME "eTSEC3" 449 #define CONFIG_TSEC4 1 450 #define CONFIG_TSEC4_NAME "eTSEC4" 451 452 #define TSEC1_PHY_ADDR 0 453 #define TSEC2_PHY_ADDR 1 454 #define TSEC3_PHY_ADDR 2 455 #define TSEC4_PHY_ADDR 3 456 #define TSEC1_PHYIDX 0 457 #define TSEC2_PHYIDX 0 458 #define TSEC3_PHYIDX 0 459 #define TSEC4_PHYIDX 0 460 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 461 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 462 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 463 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 464 465 #define CONFIG_ETHPRIME "eTSEC1" 466 467 #endif /* CONFIG_TSEC_ENET */ 468 469 /* Contort an addr into the format needed for BATs */ 470 #ifdef CONFIG_PHYS_64BIT 471 #define BAT_PHYS_ADDR(x) ((unsigned long) \ 472 ((x & 0x00000000ffffffffULL) | \ 473 ((x & 0x0000000e00000000ULL) >> 24) | \ 474 ((x & 0x0000000100000000ULL) >> 30))) 475 #else 476 #define BAT_PHYS_ADDR(x) (x) 477 #endif 478 479 480 /* Put high physical address bits into the BAT format */ 481 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 482 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 483 484 /* 485 * BAT0 DDR 486 */ 487 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 488 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 489 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 490 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 491 492 /* 493 * BAT1 LBC (PIXIS/CF) 494 */ 495 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 496 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 497 BATL_GUARDEDSTORAGE) 498 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 499 | BATU_VS | BATU_VP) 500 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 501 | BATL_PP_RW | BATL_MEMCOHERENCE) 502 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 503 504 /* if CONFIG_PCI: 505 * BAT2 PCI1 and PCI1 MEM 506 * if CONFIG_RIO 507 * BAT2 Rapidio Memory 508 */ 509 #ifdef CONFIG_PCI 510 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ 511 | BATL_PP_RW | BATL_CACHEINHIBIT \ 512 | BATL_GUARDEDSTORAGE) 513 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \ 514 | BATU_VS | BATU_VP) 515 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ 516 | BATL_PP_RW | BATL_CACHEINHIBIT) 517 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 518 #else /* CONFIG_RIO */ 519 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 520 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 521 BATL_GUARDEDSTORAGE) 522 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ 523 | BATU_VS | BATU_VP) 524 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 525 | BATL_PP_RW | BATL_CACHEINHIBIT) 526 527 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ 528 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 529 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 530 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 531 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 532 #endif 533 534 /* 535 * BAT3 CCSR Space 536 * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs 537 * instead. The assembler chokes on ULL. 538 */ 539 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 540 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 541 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 542 | BATL_PP_RW | BATL_CACHEINHIBIT \ 543 | BATL_GUARDEDSTORAGE) 544 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 545 | BATU_VP) 546 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 547 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 548 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 549 | BATL_PP_RW | BATL_CACHEINHIBIT) 550 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 551 552 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 553 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 554 | BATL_PP_RW | BATL_CACHEINHIBIT \ 555 | BATL_GUARDEDSTORAGE) 556 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 557 | BATU_BL_1M | BATU_VS | BATU_VP) 558 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 559 | BATL_PP_RW | BATL_CACHEINHIBIT) 560 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 561 #endif 562 563 /* 564 * BAT4 PCI1_IO and PCI2_IO 565 */ 566 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ 567 | BATL_PP_RW | BATL_CACHEINHIBIT \ 568 | BATL_GUARDEDSTORAGE) 569 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \ 570 | BATU_VS | BATU_VP) 571 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ 572 | BATL_PP_RW | BATL_CACHEINHIBIT) 573 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 574 575 /* 576 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 577 */ 578 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 579 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 580 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 581 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 582 583 /* 584 * BAT6 FLASH 585 */ 586 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 587 | BATL_PP_RW | BATL_CACHEINHIBIT \ 588 | BATL_GUARDEDSTORAGE) 589 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 590 | BATU_VP) 591 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 592 | BATL_PP_RW | BATL_MEMCOHERENCE) 593 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 594 595 /* Map the last 1M of flash where we're running from reset */ 596 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 597 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 598 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 599 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 600 | BATL_MEMCOHERENCE) 601 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 602 603 /* 604 * BAT7 FREE - used later for tmp mappings 605 */ 606 #define CONFIG_SYS_DBAT7L 0x00000000 607 #define CONFIG_SYS_DBAT7U 0x00000000 608 #define CONFIG_SYS_IBAT7L 0x00000000 609 #define CONFIG_SYS_IBAT7U 0x00000000 610 611 /* 612 * Environment 613 */ 614 #ifndef CONFIG_SYS_RAMBOOT 615 #define CONFIG_ENV_IS_IN_FLASH 1 616 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) 617 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 618 #else 619 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 620 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 621 #endif 622 #define CONFIG_ENV_SIZE 0x2000 623 624 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 625 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 626 627 628 /* 629 * BOOTP options 630 */ 631 #define CONFIG_BOOTP_BOOTFILESIZE 632 #define CONFIG_BOOTP_BOOTPATH 633 #define CONFIG_BOOTP_GATEWAY 634 #define CONFIG_BOOTP_HOSTNAME 635 636 637 /* 638 * Command line configuration. 639 */ 640 #include <config_cmd_default.h> 641 642 #define CONFIG_CMD_PING 643 #define CONFIG_CMD_I2C 644 #define CONFIG_CMD_REGINFO 645 646 #if defined(CONFIG_SYS_RAMBOOT) 647 #undef CONFIG_CMD_ENV 648 #endif 649 650 #if defined(CONFIG_PCI) 651 #define CONFIG_CMD_PCI 652 #define CONFIG_CMD_SCSI 653 #define CONFIG_CMD_EXT2 654 #define CONFIG_CMD_USB 655 #endif 656 657 658 #undef CONFIG_WATCHDOG /* watchdog disabled */ 659 660 /* 661 * Miscellaneous configurable options 662 */ 663 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 664 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 665 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 666 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 667 668 #if defined(CONFIG_CMD_KGDB) 669 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 670 #else 671 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 672 #endif 673 674 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 675 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 676 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 677 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 678 679 /* 680 * For booting Linux, the board info and command line data 681 * have to be in the first 8 MB of memory, since this is 682 * the maximum mapped by the Linux kernel during initialization. 683 */ 684 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 685 686 /* 687 * Internal Definitions 688 * 689 * Boot Flags 690 */ 691 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 692 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 693 694 #if defined(CONFIG_CMD_KGDB) 695 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 696 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 697 #endif 698 699 /* 700 * Environment Configuration 701 */ 702 703 /* The mac addresses for all ethernet interface */ 704 #if defined(CONFIG_TSEC_ENET) 705 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 706 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 707 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 708 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 709 #endif 710 711 #define CONFIG_HAS_ETH0 1 712 #define CONFIG_HAS_ETH1 1 713 #define CONFIG_HAS_ETH2 1 714 #define CONFIG_HAS_ETH3 1 715 716 #define CONFIG_IPADDR 192.168.1.100 717 718 #define CONFIG_HOSTNAME unknown 719 #define CONFIG_ROOTPATH /opt/nfsroot 720 #define CONFIG_BOOTFILE uImage 721 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 722 723 #define CONFIG_SERVERIP 192.168.1.1 724 #define CONFIG_GATEWAYIP 192.168.1.1 725 #define CONFIG_NETMASK 255.255.255.0 726 727 /* default location for tftp and bootm */ 728 #define CONFIG_LOADADDR 1000000 729 730 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 731 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 732 733 #define CONFIG_BAUDRATE 115200 734 735 #define CONFIG_EXTRA_ENV_SETTINGS \ 736 "netdev=eth0\0" \ 737 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 738 "tftpflash=tftpboot $loadaddr $uboot; " \ 739 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 740 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 741 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 742 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 743 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 744 "consoledev=ttyS0\0" \ 745 "ramdiskaddr=2000000\0" \ 746 "ramdiskfile=your.ramdisk.u-boot\0" \ 747 "fdtaddr=c00000\0" \ 748 "fdtfile=mpc8641_hpcn.dtb\0" \ 749 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 750 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 751 "maxcpus=2" 752 753 754 #define CONFIG_NFSBOOTCOMMAND \ 755 "setenv bootargs root=/dev/nfs rw " \ 756 "nfsroot=$serverip:$rootpath " \ 757 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 758 "console=$consoledev,$baudrate $othbootargs;" \ 759 "tftp $loadaddr $bootfile;" \ 760 "tftp $fdtaddr $fdtfile;" \ 761 "bootm $loadaddr - $fdtaddr" 762 763 #define CONFIG_RAMBOOTCOMMAND \ 764 "setenv bootargs root=/dev/ram rw " \ 765 "console=$consoledev,$baudrate $othbootargs;" \ 766 "tftp $ramdiskaddr $ramdiskfile;" \ 767 "tftp $loadaddr $bootfile;" \ 768 "tftp $fdtaddr $fdtfile;" \ 769 "bootm $loadaddr $ramdiskaddr $fdtaddr" 770 771 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 772 773 #endif /* __CONFIG_H */ 774