1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 #undef DEBUG 42 43 #ifdef RUN_DIAG 44 #define CFG_DIAG_ADDR 0xff800000 45 #endif 46 47 #define CFG_RESET_ADDRESS 0xfff00100 48 49 #undef CONFIG_PCI 50 51 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 52 #define CONFIG_ENV_OVERWRITE 53 54 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 55 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 56 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 57 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 58 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 59 60 #define CONFIG_ALTIVEC 1 61 62 /* 63 * L2CR setup -- make sure this is right for your board! 64 */ 65 #define CFG_L2 66 #define L2_INIT 0 67 #define L2_ENABLE (L2CR_L2E) 68 69 #ifndef CONFIG_SYS_CLK_FREQ 70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 71 #endif 72 73 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 74 75 #undef CFG_DRAM_TEST /* memory test, takes time */ 76 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 77 #define CFG_MEMTEST_END 0x00400000 78 79 80 /* 81 * Base addresses -- Note these are effective addresses where the 82 * actual resources get mapped (not physical addresses) 83 */ 84 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 85 #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 86 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 87 88 89 /* 90 * DDR Setup 91 */ 92 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 93 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 94 95 #define MPC86xx_DDR_SDRAM_CLK_CNTL 96 97 #if defined(CONFIG_SPD_EEPROM) 98 /* 99 * Determine DDR configuration from I2C interface. 100 */ 101 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 102 103 #else 104 /* 105 * Manually set up DDR parameters 106 */ 107 108 /* DDR I */ 109 #if 1 110 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 111 112 #define CFG_DDR_CS0_BNDS 0x0000000F 113 #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 114 #define CFG_DDR_EXT_REFRESH 0x00000000 115 #define CFG_DDR_TIMING_0 0x00260802 116 #define CFG_DDR_TIMING_1 0x39357322 117 #define CFG_DDR_TIMING_2 0x14904cc8 118 #define CFG_DDR_MODE_1 0x00480432 119 #define CFG_DDR_MODE_2 0x00000000 120 #define CFG_DDR_INTERVAL 0x06090100 121 #define CFG_DDR_DATA_INIT 0xdeadbeef 122 #define CFG_DDR_CLK_CTRL 0x03800000 123 #define CFG_DDR_OCD_CTRL 0x00000000 124 #define CFG_DDR_OCD_STATUS 0x00000000 125 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 126 #define CFG_DDR_CONTROL2 0x04400000 127 128 //Not used in fixed_sdram function 129 130 #define CFG_DDR_MODE 0x00000022 131 #define CFG_DDR_CS1_BNDS 0x00000000 132 #define CFG_DDR_CS2_BNDS 0x00000FFF //Not done 133 #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done 134 #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done 135 #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done 136 #endif 137 #endif 138 139 140 /* 141 * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 142 * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff 143 * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. 144 * However, when u-boot comes up, the flash_init needs hard start addresses 145 * to build its info table. For user convenience, we have the flash addresses 146 * as fe800000 and ff800000. That way, when we do flash operations, u-boot 147 * knows where the flash is and the user can download u-boot code from promjet to 148 * fef00000 <- more intuitive than fe700000. Note that, on switching the boot 149 * location, fef00000 becomes fff00000. 150 */ 151 #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ 152 #define CFG_FLASH_BASE2 0xff800000 153 154 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 155 156 #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ 157 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ 158 159 #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ 160 #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ 161 162 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 163 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 164 165 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 166 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 167 168 169 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 170 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 171 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 172 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 173 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 174 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 175 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 176 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 177 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 178 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 179 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 180 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 181 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 182 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 183 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 184 185 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 186 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 187 188 #undef CFG_FLASH_CHECKSUM 189 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 190 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 191 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 192 193 #define CFG_FLASH_CFI 194 #define CFG_FLASH_EMPTY_INFO 195 196 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 197 #define CFG_RAMBOOT 198 #else 199 #undef CFG_RAMBOOT 200 #endif 201 202 #if !defined(CFG_RAMBOOT) 203 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 204 #endif 205 206 #undef CONFIG_CLOCKS_IN_MHZ 207 208 #define CONFIG_L1_INIT_RAM 209 #undef CFG_INIT_RAM_LOCK 210 #ifndef CFG_INIT_RAM_LOCK 211 #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 212 #else 213 #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 214 #endif 215 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 216 217 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 218 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 219 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 220 221 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 222 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 223 224 /* Serial Port */ 225 #define CONFIG_CONS_INDEX 1 226 #undef CONFIG_SERIAL_SOFTWARE_FIFO 227 #define CFG_NS16550 228 #define CFG_NS16550_SERIAL 229 #define CFG_NS16550_REG_SIZE 1 230 #define CFG_NS16550_CLK get_bus_freq(0) 231 232 #define CFG_BAUDRATE_TABLE \ 233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 234 235 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 236 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 237 238 /* Use the HUSH parser */ 239 #define CFG_HUSH_PARSER 240 #ifdef CFG_HUSH_PARSER 241 #define CFG_PROMPT_HUSH_PS2 "> " 242 #endif 243 244 /* 245 * Pass open firmware flat tree to kernel 246 */ 247 #define CONFIG_OF_FLAT_TREE 1 248 #define CONFIG_OF_BOARD_SETUP 1 249 250 /* maximum size of the flat tree (8K) */ 251 #define OF_FLAT_TREE_MAX_SIZE 8192 252 253 #define OF_CPU "PowerPC,8641@0" 254 #define OF_SOC "soc8641@f8000000" 255 #define OF_TBCLK (bd->bi_busfreq / 8) 256 #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" 257 258 #define CFG_64BIT_VSPRINTF 1 259 #define CFG_64BIT_STRTOUL 1 260 261 /* I2C */ 262 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 263 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 264 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 265 #define CFG_I2C_SLAVE 0x7F 266 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 267 268 /* RapidIO MMU */ 269 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 270 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 271 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 272 273 /* 274 * General PCI 275 * Addresses are mapped 1-1. 276 */ 277 #define CFG_PCI1_MEM_BASE 0x80000000 278 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 279 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 280 #define CFG_PCI1_IO_BASE 0xe2000000 281 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 282 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 283 284 /* For RTL8139 */ 285 #define _IO_BASE 0x00000000 286 287 #define CFG_PCI2_MEM_BASE 0xa0000000 288 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 289 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 290 #define CFG_PCI2_IO_BASE 0xe3000000 291 #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE 292 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ 293 294 295 #if defined(CONFIG_PCI) 296 297 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 298 299 #undef CFG_SCSI_SCAN_BUS_REVERSE 300 301 #define CONFIG_NET_MULTI 302 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 303 304 #define CONFIG_RTL8139 305 306 #undef CONFIG_EEPRO100 307 #undef CONFIG_TULIP 308 309 #if !defined(CONFIG_PCI_PNP) 310 #define PCI_ENET0_IOADDR 0xe0000000 311 #define PCI_ENET0_MEMADDR 0xe0000000 312 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 313 #endif 314 315 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 316 317 #endif /* CONFIG_PCI */ 318 319 320 #if defined(CONFIG_TSEC_ENET) 321 322 #ifndef CONFIG_NET_MULTI 323 #define CONFIG_NET_MULTI 1 324 #endif 325 326 #define CONFIG_MII 1 /* MII PHY management */ 327 328 #define CONFIG_MPC86XX_TSEC1 1 329 #define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" 330 #define CONFIG_MPC86XX_TSEC2 1 331 #define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" 332 #define CONFIG_MPC86XX_TSEC3 1 333 #define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" 334 #define CONFIG_MPC86XX_TSEC4 1 335 #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" 336 337 #define TSEC1_PHY_ADDR 0 338 #define TSEC2_PHY_ADDR 1 339 #define TSEC3_PHY_ADDR 2 340 #define TSEC4_PHY_ADDR 3 341 #define TSEC1_PHYIDX 0 342 #define TSEC2_PHYIDX 0 343 #define TSEC3_PHYIDX 0 344 #define TSEC4_PHYIDX 0 345 346 #define CONFIG_ETHPRIME "eTSEC1" 347 348 #endif /* CONFIG_TSEC_ENET */ 349 350 351 /* BAT0 2G Cacheable, non-guarded 352 * 0x0000_0000 2G DDR 353 */ 354 #define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ 355 | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) 356 #define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP ) 357 #define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) 358 #define CFG_IBAT0U CFG_DBAT0U 359 360 /* BAT1 1G Cache-inhibited, guarded 361 * 0x8000_0000 512M PCI-Express 1 Memory 362 * 0xa000_0000 512M PCI-Express 2 Memory 363 ** SS - Changed it for operating from 0xd0000000 364 */ 365 #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ 366 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 367 #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 368 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 369 #define CFG_IBAT1U CFG_DBAT1U 370 371 /* BAT2 512M Cache-inhibited, guarded 372 * 0xc000_0000 512M RapidIO Memory 373 */ 374 #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ 375 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 376 #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 377 #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 378 #define CFG_IBAT2U CFG_DBAT2U 379 380 /* BAT3 4M Cache-inhibited, guarded 381 * 0xf800_0000 4M CCSR 382 */ 383 #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ 384 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 385 #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 386 #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 387 #define CFG_IBAT3U CFG_DBAT3U 388 389 /* BAT4 32M Cache-inhibited, guarded 390 * 0xe200_0000 16M PCI-Express 1 I/O 391 * 0xe300_0000 16M PCI-Express 2 I/0 392 ** SS - Note that this is at 0xe0000000 393 */ 394 #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ 395 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 396 #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 397 #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 398 #define CFG_IBAT4U CFG_DBAT4U 399 400 /* BAT5 128K Cacheable, non-guarded 401 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 402 */ 403 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 404 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 405 #define CFG_IBAT5L CFG_DBAT5L 406 #define CFG_IBAT5U CFG_DBAT5U 407 408 /* BAT6 32M Cache-inhibited, guarded 409 * 0xfe00_0000 32M FLASH 410 */ 411 #define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ 412 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 413 #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 414 #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 415 #define CFG_IBAT6U CFG_DBAT6U 416 417 #define CFG_DBAT7L 0x00000000 418 #define CFG_DBAT7U 0x00000000 419 #define CFG_IBAT7L 0x00000000 420 #define CFG_IBAT7U 0x00000000 421 422 423 424 425 /* 426 * Environment 427 */ 428 #ifndef CFG_RAMBOOT 429 #define CFG_ENV_IS_IN_FLASH 1 430 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 431 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 432 #define CFG_ENV_SIZE 0x2000 433 #else 434 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 435 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 436 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 437 #define CFG_ENV_SIZE 0x2000 438 #endif 439 440 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 441 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 442 443 #if defined(CFG_RAMBOOT) 444 #if defined(CONFIG_PCI) 445 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 446 | CFG_CMD_PING \ 447 | CFG_CMD_PCI \ 448 | CFG_CMD_I2C) \ 449 & \ 450 ~(CFG_CMD_ENV \ 451 | CFG_CMD_IMLS \ 452 | CFG_CMD_FLASH \ 453 | CFG_CMD_LOADS)) 454 #else 455 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 456 | CFG_CMD_PING \ 457 | CFG_CMD_I2C) \ 458 & \ 459 ~(CFG_CMD_ENV \ 460 | CFG_CMD_IMLS \ 461 | CFG_CMD_FLASH \ 462 | CFG_CMD_LOADS)) 463 #endif 464 #else 465 #if defined(CONFIG_PCI) 466 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 467 | CFG_CMD_PCI \ 468 | CFG_CMD_PING \ 469 | CFG_CMD_I2C) 470 #else 471 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 472 | CFG_CMD_PING \ 473 | CFG_CMD_I2C) 474 #endif 475 #endif 476 477 #include <cmd_confdefs.h> 478 479 #undef CONFIG_WATCHDOG /* watchdog disabled */ 480 481 /* 482 * Miscellaneous configurable options 483 */ 484 #define CFG_LONGHELP /* undef to save memory */ 485 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 486 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 487 488 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 489 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 490 #else 491 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 492 #endif 493 494 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 495 #define CFG_MAXARGS 16 /* max number of command args */ 496 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 497 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 498 499 /* 500 * For booting Linux, the board info and command line data 501 * have to be in the first 8 MB of memory, since this is 502 * the maximum mapped by the Linux kernel during initialization. 503 */ 504 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 505 506 /* Cache Configuration */ 507 #define CFG_DCACHE_SIZE 32768 508 #define CFG_CACHELINE_SIZE 32 509 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 510 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 511 #endif 512 513 /* 514 * Internal Definitions 515 * 516 * Boot Flags 517 */ 518 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 519 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 520 521 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 522 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 523 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 524 #endif 525 526 527 /* 528 * Environment Configuration 529 */ 530 531 /* The mac addresses for all ethernet interface */ 532 #if defined(CONFIG_TSEC_ENET) 533 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 534 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 535 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 536 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 537 #endif 538 539 #define CONFIG_HAS_ETH1 1 540 #define CONFIG_HAS_ETH2 1 541 #define CONFIG_HAS_ETH3 1 542 543 #define CONFIG_IPADDR 10.82.193.138 544 545 #define CONFIG_HOSTNAME unknown 546 #define CONFIG_ROOTPATH /opt/nfsroot 547 #define CONFIG_BOOTFILE uImage 548 549 #define CONFIG_SERVERIP 192.168.1.1 550 #define CONFIG_GATEWAYIP 10.82.193.104 551 #define CONFIG_NETMASK 255.255.255.0 552 553 /* default location for tftp and bootm */ 554 #define CONFIG_LOADADDR 1000000 555 556 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 557 //#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 558 #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" 559 560 #define CONFIG_BAUDRATE 115200 561 562 #define CONFIG_EXTRA_ENV_SETTINGS \ 563 "netdev=eth0\0" \ 564 "consoledev=ttyS0\0" \ 565 "ramdiskaddr=400000\0" \ 566 "ramdiskfile=your.ramdisk.u-boot\0" \ 567 "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ 568 "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ 569 "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ 570 "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ 571 "pex=run pexstat; run pex1; run pexd\0" \ 572 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 573 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 574 "maxcpus=2" 575 576 577 #define CONFIG_NFSBOOTCOMMAND \ 578 "setenv bootargs root=/dev/nfs rw " \ 579 "nfsroot=$serverip:$rootpath " \ 580 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 581 "console=$consoledev,$baudrate $othbootargs;" \ 582 "tftp $loadaddr $bootfile;" \ 583 "bootm $loadaddr" 584 585 #define CONFIG_RAMBOOTCOMMAND \ 586 "setenv bootargs root=/dev/ram rw " \ 587 "console=$consoledev,$baudrate $othbootargs;" \ 588 "tftp $ramdiskaddr $ramdiskfile;" \ 589 "tftp $loadaddr $bootfile;" \ 590 "bootm $loadaddr $ramdiskaddr" 591 592 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 593 594 #endif /* __CONFIG_H */ 595