1 /* 2 * Copyright 2006, 2010-2011 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * MPC8641HPCN board configuration file 11 * 12 * Make sure you change the MAC address and other network params first, 13 * search for CONFIG_SERVERIP, etc. in this file. 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 21 #define CONFIG_MP 1 /* support multiple processors */ 22 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 23 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 24 25 /* 26 * default CCSRBAR is at 0xff700000 27 * assume U-Boot is less than 0.5MB 28 */ 29 #define CONFIG_SYS_TEXT_BASE 0xeff00000 30 31 #ifdef RUN_DIAG 32 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 33 #endif 34 35 /* 36 * virtual address to be used for temporary mappings. There 37 * should be 128k free at this VA. 38 */ 39 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 40 41 #define CONFIG_SYS_SRIO 42 #define CONFIG_SRIO1 /* SRIO port 1 */ 43 44 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ 45 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ 46 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 47 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 48 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 53 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 54 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 55 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 56 57 #define CONFIG_ALTIVEC 1 58 59 /* 60 * L2CR setup -- make sure this is right for your board! 61 */ 62 #define CONFIG_SYS_L2 63 #define L2_INIT 0 64 #define L2_ENABLE (L2CR_L2E) 65 66 #ifndef CONFIG_SYS_CLK_FREQ 67 #ifndef __ASSEMBLY__ 68 extern unsigned long get_board_sys_clk(unsigned long dummy); 69 #endif 70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 71 #endif 72 73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 74 #define CONFIG_SYS_MEMTEST_END 0x00400000 75 76 /* 77 * With the exception of PCI Memory and Rapid IO, most devices will simply 78 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 79 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 80 */ 81 #ifdef CONFIG_PHYS_64BIT 82 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f 83 #else 84 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 85 #endif 86 87 /* 88 * Base addresses -- Note these are effective addresses where the 89 * actual resources get mapped (not physical addresses) 90 */ 91 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 92 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 93 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 94 95 /* Physical addresses */ 96 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 97 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH 98 #define CONFIG_SYS_CCSRBAR_PHYS \ 99 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 100 CONFIG_SYS_CCSRBAR_PHYS_HIGH) 101 102 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 103 104 /* 105 * DDR Setup 106 */ 107 #define CONFIG_SYS_FSL_DDR2 108 #undef CONFIG_FSL_DDR_INTERACTIVE 109 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 110 #define CONFIG_DDR_SPD 111 112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 113 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 114 115 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 117 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 118 #define CONFIG_VERY_BIG_RAM 119 120 #define CONFIG_NUM_DDR_CONTROLLERS 2 121 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 122 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 123 124 /* 125 * I2C addresses of SPD EEPROMs 126 */ 127 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 128 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 129 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 130 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 131 132 /* 133 * These are used when DDR doesn't use SPD. 134 */ 135 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 136 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 137 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 138 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 139 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 140 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 141 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 142 #define CONFIG_SYS_DDR_MODE_1 0x00480432 143 #define CONFIG_SYS_DDR_MODE_2 0x00000000 144 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 145 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 146 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 147 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 148 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 149 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 150 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 151 152 #define CONFIG_ID_EEPROM 153 #define CONFIG_SYS_I2C_EEPROM_NXID 154 #define CONFIG_ID_EEPROM 155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 157 158 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 159 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE 160 #define CONFIG_SYS_FLASH_BASE_PHYS \ 161 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 162 CONFIG_SYS_PHYS_ADDR_HIGH) 163 164 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 165 166 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 167 | 0x00001001) /* port size 16bit */ 168 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 169 170 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 171 | 0x00001001) /* port size 16bit */ 172 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 173 174 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 175 | 0x00000801) /* port size 8bit */ 176 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 177 178 /* 179 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 180 * The PIXIS and CF by themselves aren't large enough to take up the 128k 181 * required for the smallest BAT mapping, so there's a 64k hole. 182 */ 183 #define CONFIG_SYS_LBC_BASE 0xffde0000 184 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE 185 186 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 187 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 188 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) 189 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ 190 CONFIG_SYS_PHYS_ADDR_HIGH) 191 #define PIXIS_SIZE 0x00008000 /* 32k */ 192 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 193 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 194 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 195 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 196 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 197 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 198 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 199 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 200 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 201 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 202 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 203 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 204 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 205 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 206 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 207 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 208 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 209 210 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 211 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 212 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 213 214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 215 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 216 217 #undef CONFIG_SYS_FLASH_CHECKSUM 218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 221 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 222 223 #define CONFIG_FLASH_CFI_DRIVER 224 #define CONFIG_SYS_FLASH_CFI 225 #define CONFIG_SYS_FLASH_EMPTY_INFO 226 227 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 228 #define CONFIG_SYS_RAMBOOT 229 #else 230 #undef CONFIG_SYS_RAMBOOT 231 #endif 232 233 #if defined(CONFIG_SYS_RAMBOOT) 234 #undef CONFIG_SPD_EEPROM 235 #define CONFIG_SYS_SDRAM_SIZE 256 236 #endif 237 238 #undef CONFIG_CLOCKS_IN_MHZ 239 240 #define CONFIG_SYS_INIT_RAM_LOCK 1 241 #ifndef CONFIG_SYS_INIT_RAM_LOCK 242 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 243 #else 244 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 245 #endif 246 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 247 248 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 249 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 250 251 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 252 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 253 254 /* Serial Port */ 255 #define CONFIG_CONS_INDEX 1 256 #define CONFIG_SYS_NS16550_SERIAL 257 #define CONFIG_SYS_NS16550_REG_SIZE 1 258 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 259 260 #define CONFIG_SYS_BAUDRATE_TABLE \ 261 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 262 263 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 264 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 265 266 /* 267 * I2C 268 */ 269 #define CONFIG_SYS_I2C 270 #define CONFIG_SYS_I2C_FSL 271 #define CONFIG_SYS_FSL_I2C_SPEED 400000 272 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 273 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 274 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 275 276 /* 277 * RapidIO MMU 278 */ 279 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ 280 #ifdef CONFIG_PHYS_64BIT 281 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 282 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c 283 #else 284 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE 285 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 286 #endif 287 #define CONFIG_SYS_SRIO1_MEM_PHYS \ 288 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 289 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) 290 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 291 292 /* 293 * General PCI 294 * Addresses are mapped 1-1. 295 */ 296 297 #define CONFIG_SYS_PCIE1_NAME "ULI" 298 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 299 #ifdef CONFIG_PHYS_64BIT 300 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 301 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 302 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c 303 #else 304 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 305 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT 306 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 307 #endif 308 #define CONFIG_SYS_PCIE1_MEM_PHYS \ 309 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 310 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) 311 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 312 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 313 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 314 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT 315 #define CONFIG_SYS_PCIE1_IO_PHYS \ 316 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 317 CONFIG_SYS_PHYS_ADDR_HIGH) 318 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 319 320 #ifdef CONFIG_PHYS_64BIT 321 /* 322 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 323 * This will increase the amount of PCI address space available for 324 * for mapping RAM. 325 */ 326 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 327 #else 328 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 329 + CONFIG_SYS_PCIE1_MEM_SIZE) 330 #endif 331 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 332 + CONFIG_SYS_PCIE1_MEM_SIZE) 333 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ 334 + CONFIG_SYS_PCIE1_MEM_SIZE) 335 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 336 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 337 + CONFIG_SYS_PCIE1_MEM_SIZE) 338 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 339 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 340 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 341 + CONFIG_SYS_PCIE1_IO_SIZE) 342 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ 343 + CONFIG_SYS_PCIE1_IO_SIZE) 344 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 345 + CONFIG_SYS_PCIE1_IO_SIZE) 346 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 347 348 #if defined(CONFIG_PCI) 349 350 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 351 352 #undef CONFIG_EEPRO100 353 #undef CONFIG_TULIP 354 355 /************************************************************ 356 * USB support 357 ************************************************************/ 358 #define CONFIG_PCI_OHCI 1 359 #define CONFIG_USB_OHCI_NEW 1 360 #define CONFIG_SYS_USB_EVENT_POLL 1 361 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 362 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 363 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 364 365 /*PCIE video card used*/ 366 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 367 368 /*PCI video card used*/ 369 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 370 371 /* video */ 372 373 #if defined(CONFIG_VIDEO) 374 #define CONFIG_BIOSEMU 375 #define CONFIG_ATI_RADEON_FB 376 #define CONFIG_VIDEO_LOGO 377 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 378 #endif 379 380 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 381 382 #define CONFIG_DOS_PARTITION 383 #define CONFIG_SCSI_AHCI 384 385 #ifdef CONFIG_SCSI_AHCI 386 #define CONFIG_LIBATA 387 #define CONFIG_SATA_ULI5288 388 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 389 #define CONFIG_SYS_SCSI_MAX_LUN 1 390 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 391 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 392 #endif 393 394 #endif /* CONFIG_PCI */ 395 396 #if defined(CONFIG_TSEC_ENET) 397 398 #define CONFIG_MII 1 /* MII PHY management */ 399 400 #define CONFIG_TSEC1 1 401 #define CONFIG_TSEC1_NAME "eTSEC1" 402 #define CONFIG_TSEC2 1 403 #define CONFIG_TSEC2_NAME "eTSEC2" 404 #define CONFIG_TSEC3 1 405 #define CONFIG_TSEC3_NAME "eTSEC3" 406 #define CONFIG_TSEC4 1 407 #define CONFIG_TSEC4_NAME "eTSEC4" 408 409 #define TSEC1_PHY_ADDR 0 410 #define TSEC2_PHY_ADDR 1 411 #define TSEC3_PHY_ADDR 2 412 #define TSEC4_PHY_ADDR 3 413 #define TSEC1_PHYIDX 0 414 #define TSEC2_PHYIDX 0 415 #define TSEC3_PHYIDX 0 416 #define TSEC4_PHYIDX 0 417 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 419 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 420 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 421 422 #define CONFIG_ETHPRIME "eTSEC1" 423 424 #endif /* CONFIG_TSEC_ENET */ 425 426 #ifdef CONFIG_PHYS_64BIT 427 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 428 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 429 430 /* Put physical address into the BAT format */ 431 #define BAT_PHYS_ADDR(low, high) \ 432 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) 433 /* Convert high/low pairs to actual 64-bit value */ 434 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) 435 #else 436 /* 32-bit systems just ignore the "high" bits */ 437 #define BAT_PHYS_ADDR(low, high) (low) 438 #define PAIRED_PHYS_TO_PHYS(low, high) (low) 439 #endif 440 441 /* 442 * BAT0 DDR 443 */ 444 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 445 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 446 447 /* 448 * BAT1 LBC (PIXIS/CF) 449 */ 450 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 451 CONFIG_SYS_PHYS_ADDR_HIGH) \ 452 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 453 BATL_GUARDEDSTORAGE) 454 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 455 | BATU_VS | BATU_VP) 456 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 457 CONFIG_SYS_PHYS_ADDR_HIGH) \ 458 | BATL_PP_RW | BATL_MEMCOHERENCE) 459 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 460 461 /* if CONFIG_PCI: 462 * BAT2 PCIE1 and PCIE1 MEM 463 * if CONFIG_RIO 464 * BAT2 Rapidio Memory 465 */ 466 #ifdef CONFIG_PCI 467 #define CONFIG_PCI_INDIRECT_BRIDGE 468 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 469 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 470 | BATL_PP_RW | BATL_CACHEINHIBIT \ 471 | BATL_GUARDEDSTORAGE) 472 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 473 | BATU_VS | BATU_VP) 474 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 475 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 476 | BATL_PP_RW | BATL_CACHEINHIBIT) 477 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 478 #else /* CONFIG_RIO */ 479 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 480 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 481 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 482 BATL_GUARDEDSTORAGE) 483 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ 484 | BATU_VS | BATU_VP) 485 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 486 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 487 | BATL_PP_RW | BATL_CACHEINHIBIT) 488 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 489 #endif 490 491 /* 492 * BAT3 CCSR Space 493 */ 494 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 495 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 496 | BATL_PP_RW | BATL_CACHEINHIBIT \ 497 | BATL_GUARDEDSTORAGE) 498 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 499 | BATU_VP) 500 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 501 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 502 | BATL_PP_RW | BATL_CACHEINHIBIT) 503 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 504 505 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 506 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 507 | BATL_PP_RW | BATL_CACHEINHIBIT \ 508 | BATL_GUARDEDSTORAGE) 509 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 510 | BATU_BL_1M | BATU_VS | BATU_VP) 511 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 512 | BATL_PP_RW | BATL_CACHEINHIBIT) 513 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 514 #endif 515 516 /* 517 * BAT4 PCIE1_IO and PCIE2_IO 518 */ 519 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 520 CONFIG_SYS_PHYS_ADDR_HIGH) \ 521 | BATL_PP_RW | BATL_CACHEINHIBIT \ 522 | BATL_GUARDEDSTORAGE) 523 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 524 | BATU_VS | BATU_VP) 525 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 526 CONFIG_SYS_PHYS_ADDR_HIGH) \ 527 | BATL_PP_RW | BATL_CACHEINHIBIT) 528 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 529 530 /* 531 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 532 */ 533 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 534 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 535 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 536 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 537 538 /* 539 * BAT6 FLASH 540 */ 541 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 542 CONFIG_SYS_PHYS_ADDR_HIGH) \ 543 | BATL_PP_RW | BATL_CACHEINHIBIT \ 544 | BATL_GUARDEDSTORAGE) 545 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 546 | BATU_VP) 547 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 548 CONFIG_SYS_PHYS_ADDR_HIGH) \ 549 | BATL_PP_RW | BATL_MEMCOHERENCE) 550 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 551 552 /* Map the last 1M of flash where we're running from reset */ 553 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 554 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 555 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 556 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 557 | BATL_MEMCOHERENCE) 558 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 559 560 /* 561 * BAT7 FREE - used later for tmp mappings 562 */ 563 #define CONFIG_SYS_DBAT7L 0x00000000 564 #define CONFIG_SYS_DBAT7U 0x00000000 565 #define CONFIG_SYS_IBAT7L 0x00000000 566 #define CONFIG_SYS_IBAT7U 0x00000000 567 568 /* 569 * Environment 570 */ 571 #ifndef CONFIG_SYS_RAMBOOT 572 #define CONFIG_ENV_IS_IN_FLASH 1 573 #define CONFIG_ENV_ADDR \ 574 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 575 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 576 #else 577 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 578 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 579 #endif 580 #define CONFIG_ENV_SIZE 0x2000 581 582 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 583 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 584 585 /* 586 * BOOTP options 587 */ 588 #define CONFIG_BOOTP_BOOTFILESIZE 589 #define CONFIG_BOOTP_BOOTPATH 590 #define CONFIG_BOOTP_GATEWAY 591 #define CONFIG_BOOTP_HOSTNAME 592 593 /* 594 * Command line configuration. 595 */ 596 #define CONFIG_CMD_REGINFO 597 598 #if defined(CONFIG_PCI) 599 #define CONFIG_CMD_PCI 600 #define CONFIG_SCSI 601 #endif 602 603 #undef CONFIG_WATCHDOG /* watchdog disabled */ 604 605 /* 606 * Miscellaneous configurable options 607 */ 608 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 609 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 610 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 611 612 #if defined(CONFIG_CMD_KGDB) 613 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 614 #else 615 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 616 #endif 617 618 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 619 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 620 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 621 622 /* 623 * For booting Linux, the board info and command line data 624 * have to be in the first 8 MB of memory, since this is 625 * the maximum mapped by the Linux kernel during initialization. 626 */ 627 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 628 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 629 630 #if defined(CONFIG_CMD_KGDB) 631 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 632 #endif 633 634 /* 635 * Environment Configuration 636 */ 637 638 #define CONFIG_HAS_ETH0 1 639 #define CONFIG_HAS_ETH1 1 640 #define CONFIG_HAS_ETH2 1 641 #define CONFIG_HAS_ETH3 1 642 643 #define CONFIG_IPADDR 192.168.1.100 644 645 #define CONFIG_HOSTNAME unknown 646 #define CONFIG_ROOTPATH "/opt/nfsroot" 647 #define CONFIG_BOOTFILE "uImage" 648 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 649 650 #define CONFIG_SERVERIP 192.168.1.1 651 #define CONFIG_GATEWAYIP 192.168.1.1 652 #define CONFIG_NETMASK 255.255.255.0 653 654 /* default location for tftp and bootm */ 655 #define CONFIG_LOADADDR 0x10000000 656 657 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 658 659 #define CONFIG_BAUDRATE 115200 660 661 #define CONFIG_EXTRA_ENV_SETTINGS \ 662 "netdev=eth0\0" \ 663 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 664 "tftpflash=tftpboot $loadaddr $uboot; " \ 665 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 666 " +$filesize; " \ 667 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 668 " +$filesize; " \ 669 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 670 " $filesize; " \ 671 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 672 " +$filesize; " \ 673 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 674 " $filesize\0" \ 675 "consoledev=ttyS0\0" \ 676 "ramdiskaddr=0x18000000\0" \ 677 "ramdiskfile=your.ramdisk.u-boot\0" \ 678 "fdtaddr=0x17c00000\0" \ 679 "fdtfile=mpc8641_hpcn.dtb\0" \ 680 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 681 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 682 "maxcpus=2" 683 684 #define CONFIG_NFSBOOTCOMMAND \ 685 "setenv bootargs root=/dev/nfs rw " \ 686 "nfsroot=$serverip:$rootpath " \ 687 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 688 "console=$consoledev,$baudrate $othbootargs;" \ 689 "tftp $loadaddr $bootfile;" \ 690 "tftp $fdtaddr $fdtfile;" \ 691 "bootm $loadaddr - $fdtaddr" 692 693 #define CONFIG_RAMBOOTCOMMAND \ 694 "setenv bootargs root=/dev/ram rw " \ 695 "console=$consoledev,$baudrate $othbootargs;" \ 696 "tftp $ramdiskaddr $ramdiskfile;" \ 697 "tftp $loadaddr $bootfile;" \ 698 "tftp $fdtaddr $fdtfile;" \ 699 "bootm $loadaddr $ramdiskaddr $fdtaddr" 700 701 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 702 703 #endif /* __CONFIG_H */ 704