1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_MPC86xx 1 /* MPC86xx */ 18 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 19 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 20 #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 23 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 24 25 /* video */ 26 #undef CONFIG_VIDEO 27 28 #if defined(CONFIG_VIDEO) 29 #define CONFIG_CFB_CONSOLE 30 #define CONFIG_VGA_AS_SINGLE_DEVICE 31 #endif 32 33 #ifdef RUN_DIAG 34 #define CONFIG_SYS_DIAG_ADDR 0xff800000 35 #endif 36 37 /* 38 * virtual address to be used for temporary mappings. There 39 * should be 128k free at this VA. 40 */ 41 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 42 43 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 44 #define CONFIG_PCI1 1 /* PCI controler 1 */ 45 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 46 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 48 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 49 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 50 51 #define CONFIG_ENV_OVERWRITE 52 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 53 54 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 55 #define CONFIG_ALTIVEC 1 56 57 /* 58 * L2CR setup -- make sure this is right for your board! 59 */ 60 #define CONFIG_SYS_L2 61 #define L2_INIT 0 62 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 63 64 #ifndef CONFIG_SYS_CLK_FREQ 65 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 66 #endif 67 68 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 69 #define CONFIG_MISC_INIT_R 1 70 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 72 #define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 /* 75 * Base addresses -- Note these are effective addresses where the 76 * actual resources get mapped (not physical addresses) 77 */ 78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 79 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 81 82 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 83 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 84 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 85 86 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 87 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 88 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 89 90 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) 91 92 /* DDR Setup */ 93 #define CONFIG_FSL_DDR2 94 #undef CONFIG_FSL_DDR_INTERACTIVE 95 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 96 #define CONFIG_DDR_SPD 97 98 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 99 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 100 101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 103 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 104 #define CONFIG_VERY_BIG_RAM 105 106 #define MPC86xx_DDR_SDRAM_CLK_CNTL 107 108 #define CONFIG_NUM_DDR_CONTROLLERS 1 109 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 110 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 111 112 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 113 114 /* These are used when DDR doesn't use SPD. */ 115 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 116 117 #if 0 /* TODO */ 118 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 119 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 120 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 121 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 122 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 123 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 124 #define CONFIG_SYS_DDR_MODE_1 0x00480432 125 #define CONFIG_SYS_DDR_MODE_2 0x00000000 126 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 127 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 128 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 129 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 130 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 131 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 132 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 133 134 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 135 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 136 #define CONFIG_SYS_DDR_SBE 0x000f0000 137 138 #endif 139 140 141 #define CONFIG_ID_EEPROM 142 #define CONFIG_SYS_I2C_EEPROM_NXID 143 #define CONFIG_ID_EEPROM 144 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 145 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 146 147 148 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 149 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 150 151 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 152 153 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 154 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 155 156 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 157 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 158 #if 0 /* TODO */ 159 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 160 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 161 #endif 162 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 163 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 164 165 166 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 167 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 168 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 169 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 170 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 171 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 172 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 173 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 174 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 175 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 176 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 177 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 178 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 179 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 180 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 181 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 182 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 183 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ 184 185 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 186 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 187 188 #undef CONFIG_SYS_FLASH_CHECKSUM 189 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 191 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 192 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 193 194 #define CONFIG_FLASH_CFI_DRIVER 195 #define CONFIG_SYS_FLASH_CFI 196 #define CONFIG_SYS_FLASH_EMPTY_INFO 197 198 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 199 #define CONFIG_SYS_RAMBOOT 200 #else 201 #undef CONFIG_SYS_RAMBOOT 202 #endif 203 204 #if defined(CONFIG_SYS_RAMBOOT) 205 #undef CONFIG_SPD_EEPROM 206 #define CONFIG_SYS_SDRAM_SIZE 256 207 #endif 208 209 #undef CONFIG_CLOCKS_IN_MHZ 210 211 #define CONFIG_SYS_INIT_RAM_LOCK 1 212 #ifndef CONFIG_SYS_INIT_RAM_LOCK 213 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 214 #else 215 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 216 #endif 217 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 218 219 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 220 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 221 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 222 223 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 224 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 225 226 /* Serial Port */ 227 #define CONFIG_CONS_INDEX 1 228 #undef CONFIG_SERIAL_SOFTWARE_FIFO 229 #define CONFIG_SYS_NS16550 230 #define CONFIG_SYS_NS16550_SERIAL 231 #define CONFIG_SYS_NS16550_REG_SIZE 1 232 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 233 234 #define CONFIG_SYS_BAUDRATE_TABLE \ 235 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 236 237 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 238 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 239 240 /* Use the HUSH parser */ 241 #define CONFIG_SYS_HUSH_PARSER 242 #ifdef CONFIG_SYS_HUSH_PARSER 243 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 244 #endif 245 246 /* 247 * Pass open firmware flat tree to kernel 248 */ 249 #define CONFIG_OF_LIBFDT 1 250 #define CONFIG_OF_BOARD_SETUP 1 251 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 252 253 254 /* maximum size of the flat tree (8K) */ 255 #define OF_FLAT_TREE_MAX_SIZE 8192 256 257 #define CONFIG_SYS_64BIT_VSPRINTF 1 258 #define CONFIG_SYS_64BIT_STRTOUL 1 259 260 /* 261 * I2C 262 */ 263 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 264 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 265 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 266 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 267 #define CONFIG_SYS_I2C_SLAVE 0x7F 268 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 269 #define CONFIG_SYS_I2C_OFFSET 0x3000 270 271 /* 272 * General PCI 273 * Addresses are mapped 1-1. 274 */ 275 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 276 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 277 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 278 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 279 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 280 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 281 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 282 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 283 284 /* controller 1, Base address 0xa000 */ 285 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 286 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 287 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 288 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 289 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 290 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 291 292 /* controller 2, Base Address 0x9000 */ 293 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 294 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 295 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 296 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 297 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 298 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 299 300 301 #if defined(CONFIG_PCI) 302 303 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 304 305 #define CONFIG_NET_MULTI 306 #define CONFIG_CMD_NET 307 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 308 #define CONFIG_CMD_REGINFO 309 310 #define CONFIG_ULI526X 311 #ifdef CONFIG_ULI526X 312 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 313 #endif 314 315 /************************************************************ 316 * USB support 317 ************************************************************/ 318 #define CONFIG_PCI_OHCI 1 319 #define CONFIG_USB_OHCI_NEW 1 320 #define CONFIG_USB_KEYBOARD 1 321 #define CONFIG_SYS_STDIO_DEREGISTER 322 #define CONFIG_SYS_USB_EVENT_POLL 1 323 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 324 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 325 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 326 327 #if !defined(CONFIG_PCI_PNP) 328 #define PCI_ENET0_IOADDR 0xe0000000 329 #define PCI_ENET0_MEMADDR 0xe0000000 330 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 331 #endif 332 333 #define CONFIG_DOS_PARTITION 334 #define CONFIG_SCSI_AHCI 335 336 #ifdef CONFIG_SCSI_AHCI 337 #define CONFIG_SATA_ULI5288 338 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 339 #define CONFIG_SYS_SCSI_MAX_LUN 1 340 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 341 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 342 #endif 343 344 #endif /* CONFIG_PCI */ 345 346 /* 347 * BAT0 2G Cacheable, non-guarded 348 * 0x0000_0000 2G DDR 349 */ 350 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 351 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 352 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 353 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 354 355 /* 356 * BAT1 1G Cache-inhibited, guarded 357 * 0x8000_0000 256M PCI-1 Memory 358 * 0xa000_0000 256M PCI-Express 1 Memory 359 * 0x9000_0000 256M PCI-Express 2 Memory 360 */ 361 362 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 363 | BATL_GUARDEDSTORAGE) 364 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 365 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 366 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 367 368 /* 369 * BAT2 16M Cache-inhibited, guarded 370 * 0xe100_0000 1M PCI-1 I/O 371 */ 372 373 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 374 | BATL_GUARDEDSTORAGE) 375 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 376 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 377 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 378 379 /* 380 * BAT3 4M Cache-inhibited, guarded 381 * 0xe000_0000 4M CCSR 382 */ 383 384 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 385 | BATL_GUARDEDSTORAGE) 386 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 387 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 388 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 389 390 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 391 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 392 | BATL_PP_RW | BATL_CACHEINHIBIT \ 393 | BATL_GUARDEDSTORAGE) 394 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 395 | BATU_BL_1M | BATU_VS | BATU_VP) 396 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 397 | BATL_PP_RW | BATL_CACHEINHIBIT) 398 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 399 #endif 400 401 /* 402 * BAT4 32M Cache-inhibited, guarded 403 * 0xe200_0000 1M PCI-Express 2 I/O 404 * 0xe300_0000 1M PCI-Express 1 I/O 405 */ 406 407 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 408 | BATL_GUARDEDSTORAGE) 409 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 410 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 411 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 412 413 414 /* 415 * BAT5 128K Cacheable, non-guarded 416 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 417 */ 418 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 419 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 420 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 421 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 422 423 /* 424 * BAT6 256M Cache-inhibited, guarded 425 * 0xf000_0000 256M FLASH 426 */ 427 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 428 | BATL_GUARDEDSTORAGE) 429 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 430 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 431 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 432 433 /* Map the last 1M of flash where we're running from reset */ 434 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 435 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 436 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 437 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 438 | BATL_MEMCOHERENCE) 439 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 440 441 /* 442 * BAT7 4M Cache-inhibited, guarded 443 * 0xe800_0000 4M PIXIS 444 */ 445 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 446 | BATL_GUARDEDSTORAGE) 447 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 448 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 449 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 450 451 452 /* 453 * Environment 454 */ 455 #ifndef CONFIG_SYS_RAMBOOT 456 #define CONFIG_ENV_IS_IN_FLASH 1 457 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 458 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 459 #define CONFIG_ENV_SIZE 0x2000 460 #else 461 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 462 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 463 #define CONFIG_ENV_SIZE 0x2000 464 #endif 465 466 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 467 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 468 469 470 /* 471 * BOOTP options 472 */ 473 #define CONFIG_BOOTP_BOOTFILESIZE 474 #define CONFIG_BOOTP_BOOTPATH 475 #define CONFIG_BOOTP_GATEWAY 476 #define CONFIG_BOOTP_HOSTNAME 477 478 479 /* 480 * Command line configuration. 481 */ 482 #include <config_cmd_default.h> 483 484 #define CONFIG_CMD_PING 485 #define CONFIG_CMD_I2C 486 #define CONFIG_CMD_MII 487 488 #if defined(CONFIG_SYS_RAMBOOT) 489 #undef CONFIG_CMD_SAVEENV 490 #endif 491 492 #if defined(CONFIG_PCI) 493 #define CONFIG_CMD_PCI 494 #define CONFIG_CMD_SCSI 495 #define CONFIG_CMD_EXT2 496 #define CONFIG_CMD_USB 497 #endif 498 499 500 #define CONFIG_WATCHDOG /* watchdog enabled */ 501 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 502 503 /*DIU Configuration*/ 504 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ 505 506 /* 507 * Miscellaneous configurable options 508 */ 509 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 510 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 511 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 512 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 513 514 #if defined(CONFIG_CMD_KGDB) 515 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 516 #else 517 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 518 #endif 519 520 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 521 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 522 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 523 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 524 525 /* 526 * For booting Linux, the board info and command line data 527 * have to be in the first 8 MB of memory, since this is 528 * the maximum mapped by the Linux kernel during initialization. 529 */ 530 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 531 532 /* 533 * Internal Definitions 534 * 535 * Boot Flags 536 */ 537 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 538 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 539 540 #if defined(CONFIG_CMD_KGDB) 541 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 542 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 543 #endif 544 545 /* 546 * Environment Configuration 547 */ 548 #define CONFIG_IPADDR 192.168.1.100 549 550 #define CONFIG_HOSTNAME unknown 551 #define CONFIG_ROOTPATH /opt/nfsroot 552 #define CONFIG_BOOTFILE uImage 553 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 554 555 #define CONFIG_SERVERIP 192.168.1.1 556 #define CONFIG_GATEWAYIP 192.168.1.1 557 #define CONFIG_NETMASK 255.255.255.0 558 559 /* default location for tftp and bootm */ 560 #define CONFIG_LOADADDR 1000000 561 562 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 563 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 564 565 #define CONFIG_BAUDRATE 115200 566 567 #if defined(CONFIG_PCI1) 568 #define PCI_ENV \ 569 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 570 "echo e;md ${a}e00 9\0" \ 571 "pci1regs=setenv a e0008; run pcireg\0" \ 572 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 573 "pci d.w $b.0 56 1\0" \ 574 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 575 "pci w.w $b.0 56 ffff\0" \ 576 "pci1err=setenv a e0008; run pcierr\0" \ 577 "pci1errc=setenv a e0008; run pcierrc\0" 578 #else 579 #define PCI_ENV "" 580 #endif 581 582 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 583 #define PCIE_ENV \ 584 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 585 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 586 "pcie1regs=setenv a e000a; run pciereg\0" \ 587 "pcie2regs=setenv a e0009; run pciereg\0" \ 588 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 589 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 590 "pci d $b.0 130 1\0" \ 591 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 592 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 593 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 594 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 595 "pcie1err=setenv a e000a; run pcieerr\0" \ 596 "pcie2err=setenv a e0009; run pcieerr\0" \ 597 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 598 "pcie2errc=setenv a e0009; run pcieerrc\0" 599 #else 600 #define PCIE_ENV "" 601 #endif 602 603 #define DMA_ENV \ 604 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 605 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 606 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 607 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 608 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 609 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 610 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 611 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 612 613 #ifdef ENV_DEBUG 614 #define CONFIG_EXTRA_ENV_SETTINGS \ 615 "netdev=eth0\0" \ 616 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 617 "tftpflash=tftpboot $loadaddr $uboot; " \ 618 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 619 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 620 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 621 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 622 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 623 "consoledev=ttyS0\0" \ 624 "ramdiskaddr=2000000\0" \ 625 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 626 "fdtaddr=c00000\0" \ 627 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 628 "bdev=sda3\0" \ 629 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 630 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 631 "maxcpus=1" \ 632 "eoi=mw e00400b0 0\0" \ 633 "iack=md e00400a0 1\0" \ 634 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 635 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 636 "md ${a}f00 5\0" \ 637 "ddr1regs=setenv a e0002; run ddrreg\0" \ 638 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 639 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 640 "md ${a}e60 1; md ${a}ef0 1d\0" \ 641 "guregs=setenv a e00e0; run gureg\0" \ 642 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 643 "mcmregs=setenv a e0001; run mcmreg\0" \ 644 "diuregs=md e002c000 1d\0" \ 645 "dium=mw e002c01c\0" \ 646 "diuerr=md e002c014 1\0" \ 647 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ 648 "monitor=0-DVI\0" \ 649 "pmregs=md e00e1000 2b\0" \ 650 "lawregs=md e0000c08 4b\0" \ 651 "lbcregs=md e0005000 36\0" \ 652 "dma0regs=md e0021100 12\0" \ 653 "dma1regs=md e0021180 12\0" \ 654 "dma2regs=md e0021200 12\0" \ 655 "dma3regs=md e0021280 12\0" \ 656 PCI_ENV \ 657 PCIE_ENV \ 658 DMA_ENV 659 #else 660 #define CONFIG_EXTRA_ENV_SETTINGS \ 661 "netdev=eth0\0" \ 662 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 663 "consoledev=ttyS0\0" \ 664 "ramdiskaddr=2000000\0" \ 665 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 666 "fdtaddr=c00000\0" \ 667 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 668 "bdev=sda3\0" \ 669 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ 670 "monitor=0-DVI\0" 671 #endif 672 673 #define CONFIG_NFSBOOTCOMMAND \ 674 "setenv bootargs root=/dev/nfs rw " \ 675 "nfsroot=$serverip:$rootpath " \ 676 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 677 "console=$consoledev,$baudrate $othbootargs;" \ 678 "tftp $loadaddr $bootfile;" \ 679 "tftp $fdtaddr $fdtfile;" \ 680 "bootm $loadaddr - $fdtaddr" 681 682 #define CONFIG_RAMBOOTCOMMAND \ 683 "setenv bootargs root=/dev/ram rw " \ 684 "console=$consoledev,$baudrate $othbootargs;" \ 685 "tftp $ramdiskaddr $ramdiskfile;" \ 686 "tftp $loadaddr $bootfile;" \ 687 "tftp $fdtaddr $fdtfile;" \ 688 "bootm $loadaddr $ramdiskaddr $fdtaddr" 689 690 #define CONFIG_BOOTCOMMAND \ 691 "setenv bootargs root=/dev/$bdev rw " \ 692 "console=$consoledev,$baudrate $othbootargs;" \ 693 "tftp $loadaddr $bootfile;" \ 694 "tftp $fdtaddr $fdtfile;" \ 695 "bootm $loadaddr - $fdtaddr" 696 697 #endif /* __CONFIG_H */ 698