1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 * 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 /* High Level Configuration Options */ 18 #define CONFIG_MPC86xx 1 /* MPC86xx */ 19 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 20 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 21 #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ 22 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 23 24 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 25 #ifdef RUN_DIAG 26 #define CFG_DIAG_ADDR 0xff800000 27 #endif 28 29 #define CFG_RESET_ADDRESS 0xfff00100 30 31 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 32 #define CONFIG_PCI1 1 /* PCI controler 1 */ 33 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 34 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 35 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 36 37 #define CONFIG_ENV_OVERWRITE 38 39 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 40 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 41 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 42 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 43 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 44 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 45 #define CONFIG_NUM_DDR_CONTROLLERS 1 46 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 47 48 #define CONFIG_ALTIVEC 1 49 50 /* 51 * L2CR setup -- make sure this is right for your board! 52 */ 53 #define CFG_L2 54 #define L2_INIT 0 55 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 56 57 #ifndef CONFIG_SYS_CLK_FREQ 58 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 59 #endif 60 61 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 62 #define CONFIG_MISC_INIT_R 1 63 64 #undef CFG_DRAM_TEST /* memory test, takes time */ 65 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 66 #define CFG_MEMTEST_END 0x00400000 67 #define CFG_ALT_MEMTEST 68 69 /* 70 * Base addresses -- Note these are effective addresses where the 71 * actual resources get mapped (not physical addresses) 72 */ 73 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 74 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 75 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 76 77 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 78 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 79 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 80 81 #define CFG_DIU_ADDR (CFG_CCSRBAR+0x2c000) 82 83 /* 84 * DDR Setup 85 */ 86 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 87 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 88 #define CONFIG_VERY_BIG_RAM 89 90 #define MPC86xx_DDR_SDRAM_CLK_CNTL 91 92 #if defined(CONFIG_SPD_EEPROM) 93 /* 94 * Determine DDR configuration from I2C interface. 95 */ 96 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 97 #else 98 /* 99 * Manually set up DDR1 parameters 100 */ 101 102 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 103 104 #if 0 /* TODO */ 105 #define CFG_DDR_CS0_BNDS 0x0000000F 106 #define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 107 #define CFG_DDR_EXT_REFRESH 0x00000000 108 #define CFG_DDR_TIMING_0 0x00260802 109 #define CFG_DDR_TIMING_1 0x3935d322 110 #define CFG_DDR_TIMING_2 0x14904cc8 111 #define CFG_DDR_MODE_1 0x00480432 112 #define CFG_DDR_MODE_2 0x00000000 113 #define CFG_DDR_INTERVAL 0x06180100 114 #define CFG_DDR_DATA_INIT 0xdeadbeef 115 #define CFG_DDR_CLK_CTRL 0x03800000 116 #define CFG_DDR_OCD_CTRL 0x00000000 117 #define CFG_DDR_OCD_STATUS 0x00000000 118 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 119 #define CFG_DDR_CONTROL2 0x04400010 120 121 #define CFG_DDR_ERR_INT_EN 0x00000000 122 #define CFG_DDR_ERR_DIS 0x00000000 123 #define CFG_DDR_SBE 0x000f0000 124 /* Not used in fixed_sdram function */ 125 #define CFG_DDR_MODE 0x00000022 126 #define CFG_DDR_CS1_BNDS 0x00000000 127 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 128 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 129 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 130 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 131 #endif 132 #endif 133 134 #define CFG_ID_EEPROM 135 #define ID_EEPROM_ADDR 0x57 136 137 138 #define CFG_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 139 #define CFG_FLASH_BASE2 0xf8000000 140 141 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 142 143 #define CFG_BR0_PRELIM 0xf8001001 /* port size 16bit */ 144 #define CFG_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 145 146 #define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */ 147 #define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 148 #if 0 /* TODO */ 149 #define CFG_BR2_PRELIM 0xf0000000 150 #define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 151 #endif 152 #define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */ 153 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 154 155 156 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 157 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 158 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 159 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 160 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 161 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 162 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 163 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 164 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 165 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 166 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 167 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 168 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 169 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 170 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 171 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 172 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 173 #define CFG_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ 174 175 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 176 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ 177 178 #undef CFG_FLASH_CHECKSUM 179 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 180 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 181 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 182 183 #define CFG_FLASH_CFI_DRIVER 184 #define CFG_FLASH_CFI 185 #define CFG_FLASH_EMPTY_INFO 186 187 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 188 #define CFG_RAMBOOT 189 #else 190 #undef CFG_RAMBOOT 191 #endif 192 193 #if defined(CFG_RAMBOOT) 194 #undef CONFIG_SPD_EEPROM 195 #define CFG_SDRAM_SIZE 256 196 #endif 197 198 #undef CONFIG_CLOCKS_IN_MHZ 199 200 #define CONFIG_L1_INIT_RAM 201 #define CFG_INIT_RAM_LOCK 1 202 #ifndef CFG_INIT_RAM_LOCK 203 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 204 #else 205 #define CFG_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 206 #endif 207 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 208 209 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 210 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 211 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 212 213 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 214 #define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 215 216 /* Serial Port */ 217 #define CONFIG_CONS_INDEX 1 218 #undef CONFIG_SERIAL_SOFTWARE_FIFO 219 #define CFG_NS16550 220 #define CFG_NS16550_SERIAL 221 #define CFG_NS16550_REG_SIZE 1 222 #define CFG_NS16550_CLK get_bus_freq(0) 223 224 #define CFG_BAUDRATE_TABLE \ 225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 226 227 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 228 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 229 230 /* Use the HUSH parser */ 231 #define CFG_HUSH_PARSER 232 #ifdef CFG_HUSH_PARSER 233 #define CFG_PROMPT_HUSH_PS2 "> " 234 #endif 235 236 /* 237 * Pass open firmware flat tree to kernel 238 */ 239 #define CONFIG_OF_FLAT_TREE 1 240 #define CONFIG_OF_BOARD_SETUP 1 241 242 /* maximum size of the flat tree (8K) */ 243 #define OF_FLAT_TREE_MAX_SIZE 8192 244 245 #define OF_CPU "PowerPC,8610@0" 246 #define OF_SOC "soc@e0000000" 247 #define OF_TBCLK (bd->bi_busfreq / 4) 248 #define OF_STDOUT_PATH "/soc@e0000000/serial@4500" 249 250 #define CFG_64BIT_VSPRINTF 1 251 #define CFG_64BIT_STRTOUL 1 252 253 /* 254 * I2C 255 */ 256 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 257 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 258 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 259 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 260 #define CFG_I2C_SLAVE 0x7F 261 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 262 #define CFG_I2C_OFFSET 0x3000 263 264 /* 265 * General PCI 266 * Addresses are mapped 1-1. 267 */ 268 #define CFG_PCI1_MEM_BASE 0x80000000 269 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 270 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 271 #define CFG_PCI1_IO_BASE 0x00000000 272 #define CFG_PCI1_IO_PHYS 0xe1000000 273 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 274 275 /* PCI view of System Memory */ 276 #define CFG_PCI_MEMORY_BUS 0x00000000 277 #define CFG_PCI_MEMORY_PHYS 0x00000000 278 #define CFG_PCI_MEMORY_SIZE 0x80000000 279 280 /* For RTL8139 */ 281 #define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) 282 #define _IO_BASE 0x00000000 283 284 /* controller 1, Base address 0xa000 */ 285 #define CFG_PCIE1_MEM_BASE 0xa0000000 286 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 287 #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 288 #define CFG_PCIE1_IO_BASE 0x00000000 289 #define CFG_PCIE1_IO_PHYS 0xe3000000 290 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ 291 292 /* controller 2, Base Address 0x9000 */ 293 #define CFG_PCIE2_MEM_BASE 0x90000000 294 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 295 #define CFG_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 296 #define CFG_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */ 297 #define CFG_PCIE2_IO_PHYS 0xe2000000 298 #define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ 299 300 301 #if defined(CONFIG_PCI) 302 303 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 304 305 #define CONFIG_NET_MULTI 306 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 307 308 #if 0 /* TODO */ 309 /* enable onboard uli network support */ 310 #endif 311 312 #define CONFIG_RTL8139 313 #define CONFIG_SK98 314 #define CONFIG_EEPRO100 315 #define CONFIG_TULIP 316 317 #if 0 /* TODO */ 318 /************************************************************ 319 * USB support 320 ************************************************************/ 321 #define CONFIG_USB_OHCI 1 322 #define CONFIG_USB_KEYBOARD 1 323 #define CFG_DEVICE_DEREGISTER 324 #define CFG_USB_INTERRUPT_POLL 1 325 #endif 326 327 #if !defined(CONFIG_PCI_PNP) 328 #define PCI_ENET0_IOADDR 0xe0000000 329 #define PCI_ENET0_MEMADDR 0xe0000000 330 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 331 #endif 332 333 #define CONFIG_DOS_PARTITION 334 #define CONFIG_SCSI_AHCI 335 336 #ifdef CONFIG_SCSI_AHCI 337 #define CONFIG_SATA_ULI5288 338 #define CFG_SCSI_MAX_SCSI_ID 4 339 #define CFG_SCSI_MAX_LUN 1 340 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 341 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 342 #endif 343 344 #endif /* CONFIG_PCI */ 345 346 /* 347 * BAT0 2G Cacheable, non-guarded 348 * 0x0000_0000 2G DDR 349 */ 350 #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 351 #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 352 #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 353 #define CFG_IBAT0U CFG_DBAT0U 354 355 /* 356 * BAT1 1G Cache-inhibited, guarded 357 * 0x8000_0000 256M PCI-1 Memory 358 * 0xa000_0000 256M PCI-Express 1 Memory 359 * 0x9000_0000 256M PCI-Express 2 Memory 360 */ 361 362 #define CFG_DBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 363 | BATL_GUARDEDSTORAGE) 364 #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) 365 #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 366 #define CFG_IBAT1U CFG_DBAT1U 367 368 /* 369 * BAT2 16M Cache-inhibited, guarded 370 * 0xe100_0000 1M PCI-1 I/O 371 */ 372 373 #define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 374 | BATL_GUARDEDSTORAGE) 375 #define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP) 376 #define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 377 #define CFG_IBAT2U CFG_DBAT2U 378 379 /* 380 * BAT3 32M Cache-inhibited, guarded 381 * 0xe200_0000 1M PCI-Express 2 I/O 382 * 0xe300_0000 1M PCI-Express 1 I/O 383 */ 384 385 #define CFG_DBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 386 | BATL_GUARDEDSTORAGE) 387 #define CFG_DBAT3U (CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 388 #define CFG_IBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 389 #define CFG_IBAT3U CFG_DBAT3U 390 391 /* 392 * BAT4 4M Cache-inhibited, guarded 393 * 0xe000_0000 4M CCSR 394 */ 395 #define CFG_DBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 396 | BATL_GUARDEDSTORAGE) 397 #define CFG_DBAT4U (CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 398 #define CFG_IBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 399 #define CFG_IBAT4U CFG_DBAT4U 400 401 /* 402 * BAT5 128K Cacheable, non-guarded 403 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 404 */ 405 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 406 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 407 #define CFG_IBAT5L CFG_DBAT5L 408 #define CFG_IBAT5U CFG_DBAT5U 409 410 /* 411 * BAT6 256M Cache-inhibited, guarded 412 * 0xf000_0000 256M FLASH 413 */ 414 #define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 415 | BATL_GUARDEDSTORAGE) 416 #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 417 #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 418 #define CFG_IBAT6U CFG_DBAT6U 419 420 /* 421 * BAT7 4M Cache-inhibited, guarded 422 * 0xe800_0000 4M PIXIS 423 */ 424 #define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 425 | BATL_GUARDEDSTORAGE) 426 #define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 427 #define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 428 #define CFG_IBAT7U CFG_DBAT7U 429 430 431 /* 432 * Environment 433 */ 434 #ifndef CFG_RAMBOOT 435 #define CFG_ENV_IS_IN_FLASH 1 436 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 437 #define CFG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 438 #define CFG_ENV_SIZE 0x2000 439 #else 440 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 441 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 442 #define CFG_ENV_SIZE 0x2000 443 #endif 444 445 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 446 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 447 448 449 /* 450 * BOOTP options 451 */ 452 #define CONFIG_BOOTP_BOOTFILESIZE 453 #define CONFIG_BOOTP_BOOTPATH 454 #define CONFIG_BOOTP_GATEWAY 455 #define CONFIG_BOOTP_HOSTNAME 456 457 458 /* 459 * Command line configuration. 460 */ 461 #include <config_cmd_default.h> 462 463 #define CONFIG_CMD_PING 464 #define CONFIG_CMD_I2C 465 #define CONFIG_CMD_MII 466 467 #if defined(CFG_RAMBOOT) 468 #undef CONFIG_CMD_ENV 469 #endif 470 471 #if defined(CONFIG_PCI) 472 #define CONFIG_CMD_PCI 473 #define CONFIG_CMD_SCSI 474 #define CONFIG_CMD_EXT2 475 #endif 476 477 478 #undef CONFIG_WATCHDOG /* watchdog disabled */ 479 480 /*DIU Configuration*/ 481 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ 482 483 /* 484 * Miscellaneous configurable options 485 */ 486 #define CFG_LONGHELP /* undef to save memory */ 487 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 488 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 489 490 #if defined(CONFIG_CMD_KGDB) 491 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 492 #else 493 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 494 #endif 495 496 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 497 #define CFG_MAXARGS 16 /* max number of command args */ 498 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 499 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 500 501 /* 502 * For booting Linux, the board info and command line data 503 * have to be in the first 8 MB of memory, since this is 504 * the maximum mapped by the Linux kernel during initialization. 505 */ 506 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 507 508 /* Cache Configuration */ 509 #define CFG_DCACHE_SIZE 32768 510 #define CFG_CACHELINE_SIZE 32 511 #if defined(CONFIG_CMD_KGDB) 512 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 513 #endif 514 515 /* 516 * Internal Definitions 517 * 518 * Boot Flags 519 */ 520 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 521 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 522 523 #if defined(CONFIG_CMD_KGDB) 524 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 525 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 526 #endif 527 528 /* 529 * Environment Configuration 530 */ 531 #define CONFIG_IPADDR 192.168.1.100 532 533 #define CONFIG_HOSTNAME unknown 534 #define CONFIG_ROOTPATH /opt/nfsroot 535 #define CONFIG_BOOTFILE uImage 536 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 537 538 #define CONFIG_SERVERIP 192.168.1.1 539 #define CONFIG_GATEWAYIP 192.168.1.1 540 #define CONFIG_NETMASK 255.255.255.0 541 542 /* default location for tftp and bootm */ 543 #define CONFIG_LOADADDR 1000000 544 545 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 546 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 547 548 #define CONFIG_BAUDRATE 115200 549 550 #if defined(CONFIG_PCI1) 551 #define PCI_ENV \ 552 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 553 "echo e;md ${a}e00 9\0" \ 554 "pci1regs=setenv a e0008; run pcireg\0" \ 555 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 556 "pci d.w $b.0 56 1\0" \ 557 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 558 "pci w.w $b.0 56 ffff\0" \ 559 "pci1err=setenv a e0008; run pcierr\0" \ 560 "pci1errc=setenv a e0008; run pcierrc\0" 561 #else 562 #define PCI_ENV "" 563 #endif 564 565 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 566 #define PCIE_ENV \ 567 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 568 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 569 "pcie1regs=setenv a e000a; run pciereg\0" \ 570 "pcie2regs=setenv a e0009; run pciereg\0" \ 571 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 572 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 573 "pci d $b.0 130 1\0" \ 574 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 575 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 576 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 577 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 578 "pcie1err=setenv a e000a; run pcieerr\0" \ 579 "pcie2err=setenv a e0009; run pcieerr\0" \ 580 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 581 "pcie2errc=setenv a e0009; run pcieerrc\0" 582 #else 583 #define PCIE_ENV "" 584 #endif 585 586 #define DMA_ENV \ 587 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 588 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 589 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 590 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 591 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 592 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 593 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 594 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 595 596 #ifdef ENV_DEBUG 597 #define CONFIG_EXTRA_ENV_SETTINGS \ 598 "netdev=eth0\0" \ 599 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 600 "tftpflash=tftpboot $loadaddr $uboot; " \ 601 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 602 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 603 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 604 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 605 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 606 "consoledev=ttyS0\0" \ 607 "ramdiskaddr=2000000\0" \ 608 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 609 "dtbaddr=c00000\0" \ 610 "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 611 "bdev=sda3\0" \ 612 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 613 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 614 "maxcpus=1" \ 615 "eoi=mw e00400b0 0\0" \ 616 "iack=md e00400a0 1\0" \ 617 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 618 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 619 "md ${a}f00 5\0" \ 620 "ddr1regs=setenv a e0002; run ddrreg\0" \ 621 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 622 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 623 "md ${a}e60 1; md ${a}ef0 1d\0" \ 624 "guregs=setenv a e00e0; run gureg\0" \ 625 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 626 "mcmregs=setenv a e0001; run mcmreg\0" \ 627 "diuregs=md e002c000 1d\0" \ 628 "dium=mw e002c01c\0" \ 629 "diuerr=md e002c014 1\0" \ 630 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ 631 "monitor=0-DVI\0" \ 632 "pmregs=md e00e1000 2b\0" \ 633 "lawregs=md e0000c08 4b\0" \ 634 "lbcregs=md e0005000 36\0" \ 635 "dma0regs=md e0021100 12\0" \ 636 "dma1regs=md e0021180 12\0" \ 637 "dma2regs=md e0021200 12\0" \ 638 "dma3regs=md e0021280 12\0" \ 639 PCI_ENV \ 640 PCIE_ENV \ 641 DMA_ENV 642 #else 643 #define CONFIG_EXTRA_ENV_SETTINGS \ 644 "netdev=eth0\0" \ 645 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 646 "consoledev=ttyS0\0" \ 647 "ramdiskaddr=2000000\0" \ 648 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 649 "dtbaddr=c00000\0" \ 650 "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 651 "bdev=sda3\0" \ 652 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ 653 "monitor=0-DVI\0" 654 #endif 655 656 #define CONFIG_NFSBOOTCOMMAND \ 657 "setenv bootargs root=/dev/nfs rw " \ 658 "nfsroot=$serverip:$rootpath " \ 659 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 660 "console=$consoledev,$baudrate $othbootargs;" \ 661 "tftp $loadaddr $bootfile;" \ 662 "tftp $dtbaddr $dtbfile;" \ 663 "bootm $loadaddr - $dtbaddr" 664 665 #define CONFIG_RAMBOOTCOMMAND \ 666 "setenv bootargs root=/dev/ram rw " \ 667 "console=$consoledev,$baudrate $othbootargs;" \ 668 "tftp $ramdiskaddr $ramdiskfile;" \ 669 "tftp $loadaddr $bootfile;" \ 670 "tftp $dtbaddr $dtbfile;" \ 671 "bootm $loadaddr $ramdiskaddr $dtbaddr" 672 673 #define CONFIG_BOOTCOMMAND \ 674 "setenv bootargs root=/dev/$bdev rw " \ 675 "console=$consoledev,$baudrate $othbootargs;" \ 676 "tftp $loadaddr $bootfile;" \ 677 "tftp $dtbaddr $dtbfile;" \ 678 "bootm $loadaddr - $dtbaddr" 679 680 #endif /* __CONFIG_H */ 681