1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 /* 8 * MPC8610HPCD board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 /* High Level Configuration Options */ 17 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 18 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 19 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xfff00000 22 23 24 /* video */ 25 #define CONFIG_FSL_DIU_FB 26 27 #ifdef CONFIG_FSL_DIU_FB 28 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 29 #define CONFIG_VIDEO 30 #define CONFIG_CMD_BMP 31 #define CONFIG_CFB_CONSOLE 32 #define CONFIG_VIDEO_SW_CURSOR 33 #define CONFIG_VGA_AS_SINGLE_DEVICE 34 #define CONFIG_VIDEO_LOGO 35 #define CONFIG_VIDEO_BMP_LOGO 36 #endif 37 38 #ifdef RUN_DIAG 39 #define CONFIG_SYS_DIAG_ADDR 0xff800000 40 #endif 41 42 /* 43 * virtual address to be used for temporary mappings. There 44 * should be 128k free at this VA. 45 */ 46 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 47 48 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 49 #define CONFIG_PCI1 1 /* PCI controler 1 */ 50 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 51 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 52 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 53 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 54 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 55 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 56 57 #define CONFIG_ENV_OVERWRITE 58 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 59 60 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 61 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 62 #define CONFIG_ALTIVEC 1 63 64 /* 65 * L2CR setup -- make sure this is right for your board! 66 */ 67 #define CONFIG_SYS_L2 68 #define L2_INIT 0 69 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 70 71 #ifndef CONFIG_SYS_CLK_FREQ 72 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 73 #endif 74 75 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 76 #define CONFIG_MISC_INIT_R 1 77 78 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 79 #define CONFIG_SYS_MEMTEST_END 0x00400000 80 81 /* 82 * Base addresses -- Note these are effective addresses where the 83 * actual resources get mapped (not physical addresses) 84 */ 85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 86 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 87 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 88 89 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 90 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 91 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 92 93 /* DDR Setup */ 94 #define CONFIG_SYS_FSL_DDR2 95 #undef CONFIG_FSL_DDR_INTERACTIVE 96 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 97 #define CONFIG_DDR_SPD 98 99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 100 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 101 102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 104 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 105 #define CONFIG_VERY_BIG_RAM 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 112 113 /* These are used when DDR doesn't use SPD. */ 114 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 115 116 #if 0 /* TODO */ 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 118 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 122 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 123 #define CONFIG_SYS_DDR_MODE_1 0x00480432 124 #define CONFIG_SYS_DDR_MODE_2 0x00000000 125 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 131 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 132 133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135 #define CONFIG_SYS_DDR_SBE 0x000f0000 136 137 #endif 138 139 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_NXID 142 #define CONFIG_ID_EEPROM 143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 145 146 147 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 148 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 149 150 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 151 152 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 153 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 154 155 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 156 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 157 #if 0 /* TODO */ 158 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 159 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 160 #endif 161 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 162 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 163 164 165 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 166 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 167 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 168 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 169 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 170 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 171 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 172 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 173 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 174 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 175 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 176 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 177 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 178 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 179 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 180 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 181 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 182 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 183 184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 185 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 186 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 191 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 192 193 #define CONFIG_FLASH_CFI_DRIVER 194 #define CONFIG_SYS_FLASH_CFI 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 197 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 198 #define CONFIG_SYS_RAMBOOT 199 #else 200 #undef CONFIG_SYS_RAMBOOT 201 #endif 202 203 #if defined(CONFIG_SYS_RAMBOOT) 204 #undef CONFIG_SPD_EEPROM 205 #define CONFIG_SYS_SDRAM_SIZE 256 206 #endif 207 208 #undef CONFIG_CLOCKS_IN_MHZ 209 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #ifndef CONFIG_SYS_INIT_RAM_LOCK 212 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 213 #else 214 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 215 #endif 216 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 217 218 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 219 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 220 221 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 222 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 223 224 /* Serial Port */ 225 #define CONFIG_CONS_INDEX 1 226 #define CONFIG_SYS_NS16550_SERIAL 227 #define CONFIG_SYS_NS16550_REG_SIZE 1 228 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 229 230 #define CONFIG_SYS_BAUDRATE_TABLE \ 231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 232 233 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 234 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 235 236 /* Use the HUSH parser */ 237 #define CONFIG_SYS_HUSH_PARSER 238 239 /* 240 * Pass open firmware flat tree to kernel 241 */ 242 #define CONFIG_OF_BOARD_SETUP 1 243 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 244 245 246 /* maximum size of the flat tree (8K) */ 247 #define OF_FLAT_TREE_MAX_SIZE 8192 248 249 /* 250 * I2C 251 */ 252 #define CONFIG_SYS_I2C 253 #define CONFIG_SYS_I2C_FSL 254 #define CONFIG_SYS_FSL_I2C_SPEED 400000 255 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 256 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 257 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 258 259 /* 260 * General PCI 261 * Addresses are mapped 1-1. 262 */ 263 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 264 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 265 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 266 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 267 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 268 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 269 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 270 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 271 272 /* controller 1, Base address 0xa000 */ 273 #define CONFIG_SYS_PCIE1_NAME "ULI" 274 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 275 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 276 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 277 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 278 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 279 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 280 281 /* controller 2, Base Address 0x9000 */ 282 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 283 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 284 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 285 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 286 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 287 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 288 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 289 290 291 #if defined(CONFIG_PCI) 292 293 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 294 295 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 296 #define CONFIG_CMD_REGINFO 297 298 #define CONFIG_ULI526X 299 #ifdef CONFIG_ULI526X 300 #endif 301 302 /************************************************************ 303 * USB support 304 ************************************************************/ 305 #define CONFIG_PCI_OHCI 1 306 #define CONFIG_USB_OHCI_NEW 1 307 #define CONFIG_USB_KEYBOARD 1 308 #define CONFIG_SYS_STDIO_DEREGISTER 309 #define CONFIG_SYS_USB_EVENT_POLL 1 310 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 311 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 312 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 313 314 #if !defined(CONFIG_PCI_PNP) 315 #define PCI_ENET0_IOADDR 0xe0000000 316 #define PCI_ENET0_MEMADDR 0xe0000000 317 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 318 #endif 319 320 #define CONFIG_DOS_PARTITION 321 #define CONFIG_SCSI_AHCI 322 323 #ifdef CONFIG_SCSI_AHCI 324 #define CONFIG_LIBATA 325 #define CONFIG_SATA_ULI5288 326 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 327 #define CONFIG_SYS_SCSI_MAX_LUN 1 328 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 329 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 330 #endif 331 332 #endif /* CONFIG_PCI */ 333 334 /* 335 * BAT0 2G Cacheable, non-guarded 336 * 0x0000_0000 2G DDR 337 */ 338 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 339 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 340 341 /* 342 * BAT1 1G Cache-inhibited, guarded 343 * 0x8000_0000 256M PCI-1 Memory 344 * 0xa000_0000 256M PCI-Express 1 Memory 345 * 0x9000_0000 256M PCI-Express 2 Memory 346 */ 347 348 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 349 | BATL_GUARDEDSTORAGE) 350 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 351 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 352 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 353 354 /* 355 * BAT2 16M Cache-inhibited, guarded 356 * 0xe100_0000 1M PCI-1 I/O 357 */ 358 359 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 360 | BATL_GUARDEDSTORAGE) 361 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 362 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 363 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 364 365 /* 366 * BAT3 4M Cache-inhibited, guarded 367 * 0xe000_0000 4M CCSR 368 */ 369 370 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 371 | BATL_GUARDEDSTORAGE) 372 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 373 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 374 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 375 376 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 377 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 378 | BATL_PP_RW | BATL_CACHEINHIBIT \ 379 | BATL_GUARDEDSTORAGE) 380 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 381 | BATU_BL_1M | BATU_VS | BATU_VP) 382 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 383 | BATL_PP_RW | BATL_CACHEINHIBIT) 384 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 385 #endif 386 387 /* 388 * BAT4 32M Cache-inhibited, guarded 389 * 0xe200_0000 1M PCI-Express 2 I/O 390 * 0xe300_0000 1M PCI-Express 1 I/O 391 */ 392 393 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 394 | BATL_GUARDEDSTORAGE) 395 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 396 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 397 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 398 399 400 /* 401 * BAT5 128K Cacheable, non-guarded 402 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 403 */ 404 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 405 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 406 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 407 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 408 409 /* 410 * BAT6 256M Cache-inhibited, guarded 411 * 0xf000_0000 256M FLASH 412 */ 413 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 414 | BATL_GUARDEDSTORAGE) 415 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 416 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 417 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 418 419 /* Map the last 1M of flash where we're running from reset */ 420 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 421 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 422 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 423 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 424 | BATL_MEMCOHERENCE) 425 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 426 427 /* 428 * BAT7 4M Cache-inhibited, guarded 429 * 0xe800_0000 4M PIXIS 430 */ 431 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 432 | BATL_GUARDEDSTORAGE) 433 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 434 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 435 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 436 437 438 /* 439 * Environment 440 */ 441 #ifndef CONFIG_SYS_RAMBOOT 442 #define CONFIG_ENV_IS_IN_FLASH 1 443 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 444 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 445 #define CONFIG_ENV_SIZE 0x2000 446 #else 447 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 448 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 449 #define CONFIG_ENV_SIZE 0x2000 450 #endif 451 452 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 453 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 454 455 456 /* 457 * BOOTP options 458 */ 459 #define CONFIG_BOOTP_BOOTFILESIZE 460 #define CONFIG_BOOTP_BOOTPATH 461 #define CONFIG_BOOTP_GATEWAY 462 #define CONFIG_BOOTP_HOSTNAME 463 464 465 /* 466 * Command line configuration. 467 */ 468 #define CONFIG_CMD_PING 469 #define CONFIG_CMD_I2C 470 #define CONFIG_CMD_MII 471 472 #if defined(CONFIG_PCI) 473 #define CONFIG_CMD_PCI 474 #define CONFIG_CMD_SCSI 475 #define CONFIG_CMD_EXT2 476 #define CONFIG_CMD_USB 477 #endif 478 479 480 #define CONFIG_WATCHDOG /* watchdog enabled */ 481 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 482 483 /* 484 * Miscellaneous configurable options 485 */ 486 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 487 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 488 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 489 490 #if defined(CONFIG_CMD_KGDB) 491 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 492 #else 493 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 494 #endif 495 496 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 497 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 498 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 499 500 /* 501 * For booting Linux, the board info and command line data 502 * have to be in the first 8 MB of memory, since this is 503 * the maximum mapped by the Linux kernel during initialization. 504 */ 505 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 506 507 #if defined(CONFIG_CMD_KGDB) 508 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 509 #endif 510 511 /* 512 * Environment Configuration 513 */ 514 #define CONFIG_IPADDR 192.168.1.100 515 516 #define CONFIG_HOSTNAME unknown 517 #define CONFIG_ROOTPATH "/opt/nfsroot" 518 #define CONFIG_BOOTFILE "uImage" 519 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 520 521 #define CONFIG_SERVERIP 192.168.1.1 522 #define CONFIG_GATEWAYIP 192.168.1.1 523 #define CONFIG_NETMASK 255.255.255.0 524 525 /* default location for tftp and bootm */ 526 #define CONFIG_LOADADDR 1000000 527 528 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 529 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 530 531 #define CONFIG_BAUDRATE 115200 532 533 #if defined(CONFIG_PCI1) 534 #define PCI_ENV \ 535 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 536 "echo e;md ${a}e00 9\0" \ 537 "pci1regs=setenv a e0008; run pcireg\0" \ 538 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 539 "pci d.w $b.0 56 1\0" \ 540 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 541 "pci w.w $b.0 56 ffff\0" \ 542 "pci1err=setenv a e0008; run pcierr\0" \ 543 "pci1errc=setenv a e0008; run pcierrc\0" 544 #else 545 #define PCI_ENV "" 546 #endif 547 548 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 549 #define PCIE_ENV \ 550 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 551 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 552 "pcie1regs=setenv a e000a; run pciereg\0" \ 553 "pcie2regs=setenv a e0009; run pciereg\0" \ 554 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 555 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 556 "pci d $b.0 130 1\0" \ 557 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 558 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 559 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 560 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 561 "pcie1err=setenv a e000a; run pcieerr\0" \ 562 "pcie2err=setenv a e0009; run pcieerr\0" \ 563 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 564 "pcie2errc=setenv a e0009; run pcieerrc\0" 565 #else 566 #define PCIE_ENV "" 567 #endif 568 569 #define DMA_ENV \ 570 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 571 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 572 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 573 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 574 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 575 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 576 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 577 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 578 579 #ifdef ENV_DEBUG 580 #define CONFIG_EXTRA_ENV_SETTINGS \ 581 "netdev=eth0\0" \ 582 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 583 "tftpflash=tftpboot $loadaddr $uboot; " \ 584 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 585 " +$filesize; " \ 586 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 587 " +$filesize; " \ 588 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 589 " $filesize; " \ 590 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 591 " +$filesize; " \ 592 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 593 " $filesize\0" \ 594 "consoledev=ttyS0\0" \ 595 "ramdiskaddr=2000000\0" \ 596 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 597 "fdtaddr=c00000\0" \ 598 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 599 "bdev=sda3\0" \ 600 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 601 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 602 "maxcpus=1" \ 603 "eoi=mw e00400b0 0\0" \ 604 "iack=md e00400a0 1\0" \ 605 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 606 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 607 "md ${a}f00 5\0" \ 608 "ddr1regs=setenv a e0002; run ddrreg\0" \ 609 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 610 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 611 "md ${a}e60 1; md ${a}ef0 1d\0" \ 612 "guregs=setenv a e00e0; run gureg\0" \ 613 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 614 "mcmregs=setenv a e0001; run mcmreg\0" \ 615 "diuregs=md e002c000 1d\0" \ 616 "dium=mw e002c01c\0" \ 617 "diuerr=md e002c014 1\0" \ 618 "pmregs=md e00e1000 2b\0" \ 619 "lawregs=md e0000c08 4b\0" \ 620 "lbcregs=md e0005000 36\0" \ 621 "dma0regs=md e0021100 12\0" \ 622 "dma1regs=md e0021180 12\0" \ 623 "dma2regs=md e0021200 12\0" \ 624 "dma3regs=md e0021280 12\0" \ 625 PCI_ENV \ 626 PCIE_ENV \ 627 DMA_ENV 628 #else 629 #define CONFIG_EXTRA_ENV_SETTINGS \ 630 "netdev=eth0\0" \ 631 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 632 "consoledev=ttyS0\0" \ 633 "ramdiskaddr=2000000\0" \ 634 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 635 "fdtaddr=c00000\0" \ 636 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 637 "bdev=sda3\0" 638 #endif 639 640 #define CONFIG_NFSBOOTCOMMAND \ 641 "setenv bootargs root=/dev/nfs rw " \ 642 "nfsroot=$serverip:$rootpath " \ 643 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 644 "console=$consoledev,$baudrate $othbootargs;" \ 645 "tftp $loadaddr $bootfile;" \ 646 "tftp $fdtaddr $fdtfile;" \ 647 "bootm $loadaddr - $fdtaddr" 648 649 #define CONFIG_RAMBOOTCOMMAND \ 650 "setenv bootargs root=/dev/ram rw " \ 651 "console=$consoledev,$baudrate $othbootargs;" \ 652 "tftp $ramdiskaddr $ramdiskfile;" \ 653 "tftp $loadaddr $bootfile;" \ 654 "tftp $fdtaddr $fdtfile;" \ 655 "bootm $loadaddr $ramdiskaddr $fdtaddr" 656 657 #define CONFIG_BOOTCOMMAND \ 658 "setenv bootargs root=/dev/$bdev rw " \ 659 "console=$consoledev,$baudrate $othbootargs;" \ 660 "tftp $loadaddr $bootfile;" \ 661 "tftp $fdtaddr $fdtfile;" \ 662 "bootm $loadaddr - $fdtaddr" 663 664 #endif /* __CONFIG_H */ 665