1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 * 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 /* High Level Configuration Options */ 18 #define CONFIG_MPC86xx 1 /* MPC86xx */ 19 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 20 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 21 #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ 22 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 23 24 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 25 26 /* video */ 27 #undef CONFIG_VIDEO 28 29 #if defined(CONFIG_VIDEO) 30 #define CONFIG_CFB_CONSOLE 31 #define CONFIG_VGA_AS_SINGLE_DEVICE 32 #endif 33 34 #ifdef RUN_DIAG 35 #define CFG_DIAG_ADDR 0xff800000 36 #endif 37 38 #define CFG_RESET_ADDRESS 0xfff00100 39 40 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 41 #define CONFIG_PCI1 1 /* PCI controler 1 */ 42 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 43 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_ENV_OVERWRITE 48 49 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 50 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 51 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 52 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 54 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 55 #define CONFIG_NUM_DDR_CONTROLLERS 1 56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 57 58 #define CONFIG_ALTIVEC 1 59 60 /* 61 * L2CR setup -- make sure this is right for your board! 62 */ 63 #define CFG_L2 64 #define L2_INIT 0 65 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 66 67 #ifndef CONFIG_SYS_CLK_FREQ 68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 69 #endif 70 71 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 72 #define CONFIG_MISC_INIT_R 1 73 74 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 75 #define CFG_MEMTEST_END 0x00400000 76 77 /* 78 * Base addresses -- Note these are effective addresses where the 79 * actual resources get mapped (not physical addresses) 80 */ 81 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 82 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 83 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 84 85 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 86 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 87 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 88 89 #define CFG_DIU_ADDR (CFG_CCSRBAR+0x2c000) 90 91 /* 92 * DDR Setup 93 */ 94 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 95 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 96 #define CONFIG_VERY_BIG_RAM 97 98 #define MPC86xx_DDR_SDRAM_CLK_CNTL 99 100 #if defined(CONFIG_SPD_EEPROM) 101 /* 102 * Determine DDR configuration from I2C interface. 103 */ 104 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 105 #else 106 /* 107 * Manually set up DDR1 parameters 108 */ 109 110 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 111 112 #if 0 /* TODO */ 113 #define CFG_DDR_CS0_BNDS 0x0000000F 114 #define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 115 #define CFG_DDR_TIMING_3 0x00000000 116 #define CFG_DDR_TIMING_0 0x00260802 117 #define CFG_DDR_TIMING_1 0x3935d322 118 #define CFG_DDR_TIMING_2 0x14904cc8 119 #define CFG_DDR_MODE_1 0x00480432 120 #define CFG_DDR_MODE_2 0x00000000 121 #define CFG_DDR_INTERVAL 0x06180100 122 #define CFG_DDR_DATA_INIT 0xdeadbeef 123 #define CFG_DDR_CLK_CTRL 0x03800000 124 #define CFG_DDR_OCD_CTRL 0x00000000 125 #define CFG_DDR_OCD_STATUS 0x00000000 126 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 127 #define CFG_DDR_CONTROL2 0x04400010 128 129 #define CFG_DDR_ERR_INT_EN 0x00000000 130 #define CFG_DDR_ERR_DIS 0x00000000 131 #define CFG_DDR_SBE 0x000f0000 132 /* Not used in fixed_sdram function */ 133 #define CFG_DDR_MODE 0x00000022 134 #define CFG_DDR_CS1_BNDS 0x00000000 135 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 136 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 137 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 138 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 139 #endif 140 #endif 141 142 #define CFG_ID_EEPROM 143 #ifdef CFG_ID_EEPROM 144 #define CONFIG_ID_EEPROM 145 #endif 146 #define ID_EEPROM_ADDR 0x57 147 148 149 #define CFG_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 150 #define CFG_FLASH_BASE2 0xf8000000 151 152 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 153 154 #define CFG_BR0_PRELIM 0xf8001001 /* port size 16bit */ 155 #define CFG_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 156 157 #define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */ 158 #define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 159 #if 0 /* TODO */ 160 #define CFG_BR2_PRELIM 0xf0000000 161 #define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 162 #endif 163 #define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */ 164 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 165 166 167 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 168 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 169 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 170 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 171 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 172 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 173 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 174 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 175 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 176 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 177 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 178 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 179 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 180 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 181 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 182 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 183 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 184 #define CFG_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ 185 186 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 187 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ 188 189 #undef CFG_FLASH_CHECKSUM 190 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 191 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 192 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 193 194 #define CFG_FLASH_CFI_DRIVER 195 #define CFG_FLASH_CFI 196 #define CFG_FLASH_EMPTY_INFO 197 198 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 199 #define CFG_RAMBOOT 200 #else 201 #undef CFG_RAMBOOT 202 #endif 203 204 #if defined(CFG_RAMBOOT) 205 #undef CONFIG_SPD_EEPROM 206 #define CFG_SDRAM_SIZE 256 207 #endif 208 209 #undef CONFIG_CLOCKS_IN_MHZ 210 211 #define CONFIG_L1_INIT_RAM 212 #define CFG_INIT_RAM_LOCK 1 213 #ifndef CFG_INIT_RAM_LOCK 214 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 215 #else 216 #define CFG_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 217 #endif 218 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 219 220 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 221 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 222 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 223 224 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 225 #define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 226 227 /* Serial Port */ 228 #define CONFIG_CONS_INDEX 1 229 #undef CONFIG_SERIAL_SOFTWARE_FIFO 230 #define CFG_NS16550 231 #define CFG_NS16550_SERIAL 232 #define CFG_NS16550_REG_SIZE 1 233 #define CFG_NS16550_CLK get_bus_freq(0) 234 235 #define CFG_BAUDRATE_TABLE \ 236 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 237 238 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 239 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 240 241 /* Use the HUSH parser */ 242 #define CFG_HUSH_PARSER 243 #ifdef CFG_HUSH_PARSER 244 #define CFG_PROMPT_HUSH_PS2 "> " 245 #endif 246 247 /* 248 * Pass open firmware flat tree to kernel 249 */ 250 #define CONFIG_OF_LIBFDT 1 251 #define CONFIG_OF_BOARD_SETUP 1 252 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 253 254 255 /* maximum size of the flat tree (8K) */ 256 #define OF_FLAT_TREE_MAX_SIZE 8192 257 258 #define CFG_64BIT_VSPRINTF 1 259 #define CFG_64BIT_STRTOUL 1 260 261 /* 262 * I2C 263 */ 264 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 265 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 266 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 267 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 268 #define CFG_I2C_SLAVE 0x7F 269 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 270 #define CFG_I2C_OFFSET 0x3000 271 272 /* 273 * General PCI 274 * Addresses are mapped 1-1. 275 */ 276 #define CFG_PCI1_MEM_BASE 0x80000000 277 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 278 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 279 #define CFG_PCI1_IO_BASE 0x00000000 280 #define CFG_PCI1_IO_PHYS 0xe1000000 281 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 282 283 /* PCI view of System Memory */ 284 #define CFG_PCI_MEMORY_BUS 0x00000000 285 #define CFG_PCI_MEMORY_PHYS 0x00000000 286 #define CFG_PCI_MEMORY_SIZE 0x80000000 287 288 /* For RTL8139 */ 289 #define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) 290 #define _IO_BASE 0x00000000 291 292 /* controller 1, Base address 0xa000 */ 293 #define CFG_PCIE1_MEM_BASE 0xa0000000 294 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 295 #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 296 #define CFG_PCIE1_IO_BASE 0x00000000 297 #define CFG_PCIE1_IO_PHYS 0xe3000000 298 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ 299 300 /* controller 2, Base Address 0x9000 */ 301 #define CFG_PCIE2_MEM_BASE 0x90000000 302 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 303 #define CFG_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 304 #define CFG_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */ 305 #define CFG_PCIE2_IO_PHYS 0xe2000000 306 #define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ 307 308 309 #if defined(CONFIG_PCI) 310 311 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 312 313 #define CONFIG_NET_MULTI 314 #define CONFIG_CMD_NET 315 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 316 #define CONFIG_CMD_REGINFO 317 318 #define CONFIG_ULI526X 319 #ifdef CONFIG_ULI526X 320 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 321 #endif 322 323 /************************************************************ 324 * USB support 325 ************************************************************/ 326 #define CONFIG_PCI_OHCI 1 327 #define CONFIG_USB_OHCI_NEW 1 328 #define CONFIG_USB_KEYBOARD 1 329 #define CFG_DEVICE_DEREGISTER 330 #define CFG_USB_EVENT_POLL 1 331 #define CFG_USB_OHCI_SLOT_NAME "ohci_pci" 332 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 333 #define CFG_OHCI_SWAP_REG_ACCESS 1 334 335 #if !defined(CONFIG_PCI_PNP) 336 #define PCI_ENET0_IOADDR 0xe0000000 337 #define PCI_ENET0_MEMADDR 0xe0000000 338 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 339 #endif 340 341 #define CONFIG_DOS_PARTITION 342 #define CONFIG_SCSI_AHCI 343 344 #ifdef CONFIG_SCSI_AHCI 345 #define CONFIG_SATA_ULI5288 346 #define CFG_SCSI_MAX_SCSI_ID 4 347 #define CFG_SCSI_MAX_LUN 1 348 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 349 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 350 #endif 351 352 #endif /* CONFIG_PCI */ 353 354 /* 355 * BAT0 2G Cacheable, non-guarded 356 * 0x0000_0000 2G DDR 357 */ 358 #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 359 #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 360 #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 361 #define CFG_IBAT0U CFG_DBAT0U 362 363 /* 364 * BAT1 1G Cache-inhibited, guarded 365 * 0x8000_0000 256M PCI-1 Memory 366 * 0xa000_0000 256M PCI-Express 1 Memory 367 * 0x9000_0000 256M PCI-Express 2 Memory 368 */ 369 370 #define CFG_DBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 371 | BATL_GUARDEDSTORAGE) 372 #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) 373 #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 374 #define CFG_IBAT1U CFG_DBAT1U 375 376 /* 377 * BAT2 16M Cache-inhibited, guarded 378 * 0xe100_0000 1M PCI-1 I/O 379 */ 380 381 #define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 382 | BATL_GUARDEDSTORAGE) 383 #define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP) 384 #define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 385 #define CFG_IBAT2U CFG_DBAT2U 386 387 /* 388 * BAT3 32M Cache-inhibited, guarded 389 * 0xe200_0000 1M PCI-Express 2 I/O 390 * 0xe300_0000 1M PCI-Express 1 I/O 391 */ 392 393 #define CFG_DBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 394 | BATL_GUARDEDSTORAGE) 395 #define CFG_DBAT3U (CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 396 #define CFG_IBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 397 #define CFG_IBAT3U CFG_DBAT3U 398 399 /* 400 * BAT4 4M Cache-inhibited, guarded 401 * 0xe000_0000 4M CCSR 402 */ 403 #define CFG_DBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 404 | BATL_GUARDEDSTORAGE) 405 #define CFG_DBAT4U (CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 406 #define CFG_IBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 407 #define CFG_IBAT4U CFG_DBAT4U 408 409 /* 410 * BAT5 128K Cacheable, non-guarded 411 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 412 */ 413 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 414 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 415 #define CFG_IBAT5L CFG_DBAT5L 416 #define CFG_IBAT5U CFG_DBAT5U 417 418 /* 419 * BAT6 256M Cache-inhibited, guarded 420 * 0xf000_0000 256M FLASH 421 */ 422 #define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 423 | BATL_GUARDEDSTORAGE) 424 #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 425 #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 426 #define CFG_IBAT6U CFG_DBAT6U 427 428 /* 429 * BAT7 4M Cache-inhibited, guarded 430 * 0xe800_0000 4M PIXIS 431 */ 432 #define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 433 | BATL_GUARDEDSTORAGE) 434 #define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 435 #define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 436 #define CFG_IBAT7U CFG_DBAT7U 437 438 439 /* 440 * Environment 441 */ 442 #ifndef CFG_RAMBOOT 443 #define CFG_ENV_IS_IN_FLASH 1 444 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 445 #define CFG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 446 #define CFG_ENV_SIZE 0x2000 447 #else 448 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 449 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 450 #define CFG_ENV_SIZE 0x2000 451 #endif 452 453 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 454 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 455 456 457 /* 458 * BOOTP options 459 */ 460 #define CONFIG_BOOTP_BOOTFILESIZE 461 #define CONFIG_BOOTP_BOOTPATH 462 #define CONFIG_BOOTP_GATEWAY 463 #define CONFIG_BOOTP_HOSTNAME 464 465 466 /* 467 * Command line configuration. 468 */ 469 #include <config_cmd_default.h> 470 471 #define CONFIG_CMD_PING 472 #define CONFIG_CMD_I2C 473 #define CONFIG_CMD_MII 474 475 #if defined(CFG_RAMBOOT) 476 #undef CONFIG_CMD_ENV 477 #endif 478 479 #if defined(CONFIG_PCI) 480 #define CONFIG_CMD_PCI 481 #define CONFIG_CMD_SCSI 482 #define CONFIG_CMD_EXT2 483 #define CONFIG_CMD_USB 484 #endif 485 486 487 #undef CONFIG_WATCHDOG /* watchdog disabled */ 488 489 /*DIU Configuration*/ 490 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ 491 492 /* 493 * Miscellaneous configurable options 494 */ 495 #define CFG_LONGHELP /* undef to save memory */ 496 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 497 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 498 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 499 500 #if defined(CONFIG_CMD_KGDB) 501 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 502 #else 503 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 504 #endif 505 506 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 507 #define CFG_MAXARGS 16 /* max number of command args */ 508 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 509 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 510 511 /* 512 * For booting Linux, the board info and command line data 513 * have to be in the first 8 MB of memory, since this is 514 * the maximum mapped by the Linux kernel during initialization. 515 */ 516 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 517 518 /* 519 * Internal Definitions 520 * 521 * Boot Flags 522 */ 523 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 524 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 525 526 #if defined(CONFIG_CMD_KGDB) 527 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 528 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 529 #endif 530 531 /* 532 * Environment Configuration 533 */ 534 #define CONFIG_IPADDR 192.168.1.100 535 536 #define CONFIG_HOSTNAME unknown 537 #define CONFIG_ROOTPATH /opt/nfsroot 538 #define CONFIG_BOOTFILE uImage 539 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 540 541 #define CONFIG_SERVERIP 192.168.1.1 542 #define CONFIG_GATEWAYIP 192.168.1.1 543 #define CONFIG_NETMASK 255.255.255.0 544 545 /* default location for tftp and bootm */ 546 #define CONFIG_LOADADDR 1000000 547 548 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 549 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 550 551 #define CONFIG_BAUDRATE 115200 552 553 #if defined(CONFIG_PCI1) 554 #define PCI_ENV \ 555 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 556 "echo e;md ${a}e00 9\0" \ 557 "pci1regs=setenv a e0008; run pcireg\0" \ 558 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 559 "pci d.w $b.0 56 1\0" \ 560 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 561 "pci w.w $b.0 56 ffff\0" \ 562 "pci1err=setenv a e0008; run pcierr\0" \ 563 "pci1errc=setenv a e0008; run pcierrc\0" 564 #else 565 #define PCI_ENV "" 566 #endif 567 568 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 569 #define PCIE_ENV \ 570 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 571 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 572 "pcie1regs=setenv a e000a; run pciereg\0" \ 573 "pcie2regs=setenv a e0009; run pciereg\0" \ 574 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 575 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 576 "pci d $b.0 130 1\0" \ 577 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 578 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 579 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 580 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 581 "pcie1err=setenv a e000a; run pcieerr\0" \ 582 "pcie2err=setenv a e0009; run pcieerr\0" \ 583 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 584 "pcie2errc=setenv a e0009; run pcieerrc\0" 585 #else 586 #define PCIE_ENV "" 587 #endif 588 589 #define DMA_ENV \ 590 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 591 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 592 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 593 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 594 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 595 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 596 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 597 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 598 599 #ifdef ENV_DEBUG 600 #define CONFIG_EXTRA_ENV_SETTINGS \ 601 "netdev=eth0\0" \ 602 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 603 "tftpflash=tftpboot $loadaddr $uboot; " \ 604 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 605 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 606 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 607 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 608 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 609 "consoledev=ttyS0\0" \ 610 "ramdiskaddr=2000000\0" \ 611 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 612 "fdtaddr=c00000\0" \ 613 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 614 "bdev=sda3\0" \ 615 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 616 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 617 "maxcpus=1" \ 618 "eoi=mw e00400b0 0\0" \ 619 "iack=md e00400a0 1\0" \ 620 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 621 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 622 "md ${a}f00 5\0" \ 623 "ddr1regs=setenv a e0002; run ddrreg\0" \ 624 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 625 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 626 "md ${a}e60 1; md ${a}ef0 1d\0" \ 627 "guregs=setenv a e00e0; run gureg\0" \ 628 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 629 "mcmregs=setenv a e0001; run mcmreg\0" \ 630 "diuregs=md e002c000 1d\0" \ 631 "dium=mw e002c01c\0" \ 632 "diuerr=md e002c014 1\0" \ 633 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ 634 "monitor=0-DVI\0" \ 635 "pmregs=md e00e1000 2b\0" \ 636 "lawregs=md e0000c08 4b\0" \ 637 "lbcregs=md e0005000 36\0" \ 638 "dma0regs=md e0021100 12\0" \ 639 "dma1regs=md e0021180 12\0" \ 640 "dma2regs=md e0021200 12\0" \ 641 "dma3regs=md e0021280 12\0" \ 642 PCI_ENV \ 643 PCIE_ENV \ 644 DMA_ENV 645 #else 646 #define CONFIG_EXTRA_ENV_SETTINGS \ 647 "netdev=eth0\0" \ 648 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 649 "consoledev=ttyS0\0" \ 650 "ramdiskaddr=2000000\0" \ 651 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 652 "fdtaddr=c00000\0" \ 653 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 654 "bdev=sda3\0" \ 655 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ 656 "monitor=0-DVI\0" 657 #endif 658 659 #define CONFIG_NFSBOOTCOMMAND \ 660 "setenv bootargs root=/dev/nfs rw " \ 661 "nfsroot=$serverip:$rootpath " \ 662 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 663 "console=$consoledev,$baudrate $othbootargs;" \ 664 "tftp $loadaddr $bootfile;" \ 665 "tftp $fdtaddr $fdtfile;" \ 666 "bootm $loadaddr - $fdtaddr" 667 668 #define CONFIG_RAMBOOTCOMMAND \ 669 "setenv bootargs root=/dev/ram rw " \ 670 "console=$consoledev,$baudrate $othbootargs;" \ 671 "tftp $ramdiskaddr $ramdiskfile;" \ 672 "tftp $loadaddr $bootfile;" \ 673 "tftp $fdtaddr $fdtfile;" \ 674 "bootm $loadaddr $ramdiskaddr $fdtaddr" 675 676 #define CONFIG_BOOTCOMMAND \ 677 "setenv bootargs root=/dev/$bdev rw " \ 678 "console=$consoledev,$baudrate $othbootargs;" \ 679 "tftp $loadaddr $bootfile;" \ 680 "tftp $fdtaddr $fdtfile;" \ 681 "bootm $loadaddr - $fdtaddr" 682 683 #endif /* __CONFIG_H */ 684