1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_MPC86xx 1 /* MPC86xx */ 18 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 19 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 20 #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 23 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 24 25 /* video */ 26 #undef CONFIG_VIDEO 27 28 #if defined(CONFIG_VIDEO) 29 #define CONFIG_CFB_CONSOLE 30 #define CONFIG_VGA_AS_SINGLE_DEVICE 31 #endif 32 33 #ifdef RUN_DIAG 34 #define CONFIG_SYS_DIAG_ADDR 0xff800000 35 #endif 36 37 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 38 39 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 40 #define CONFIG_PCI1 1 /* PCI controler 1 */ 41 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 42 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 44 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 49 50 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 51 #define CONFIG_ALTIVEC 1 52 53 /* 54 * L2CR setup -- make sure this is right for your board! 55 */ 56 #define CONFIG_SYS_L2 57 #define L2_INIT 0 58 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 59 60 #ifndef CONFIG_SYS_CLK_FREQ 61 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 62 #endif 63 64 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 65 #define CONFIG_MISC_INIT_R 1 66 67 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 68 #define CONFIG_SYS_MEMTEST_END 0x00400000 69 70 /* 71 * Base addresses -- Note these are effective addresses where the 72 * actual resources get mapped (not physical addresses) 73 */ 74 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 75 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 76 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 77 78 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 79 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 80 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 81 82 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) 83 84 /* DDR Setup */ 85 #define CONFIG_FSL_DDR2 86 #undef CONFIG_FSL_DDR_INTERACTIVE 87 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 88 #define CONFIG_DDR_SPD 89 90 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 91 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 92 93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 #define CONFIG_VERY_BIG_RAM 96 97 #define MPC86xx_DDR_SDRAM_CLK_CNTL 98 99 #define CONFIG_NUM_DDR_CONTROLLERS 1 100 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 101 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 102 103 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 104 105 /* These are used when DDR doesn't use SPD. */ 106 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 107 108 #if 0 /* TODO */ 109 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 110 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 111 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 112 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 113 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 114 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 115 #define CONFIG_SYS_DDR_MODE_1 0x00480432 116 #define CONFIG_SYS_DDR_MODE_2 0x00000000 117 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 118 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 119 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 120 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 121 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 122 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 123 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 124 125 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 126 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 127 #define CONFIG_SYS_DDR_SBE 0x000f0000 128 129 #endif 130 131 132 #define CONFIG_ID_EEPROM 133 #define CONFIG_SYS_I2C_EEPROM_NXID 134 #define CONFIG_ID_EEPROM 135 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 136 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 137 138 139 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 140 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 141 142 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 143 144 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 145 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 146 147 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 148 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 149 #if 0 /* TODO */ 150 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 151 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 152 #endif 153 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 154 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 155 156 157 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 158 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 159 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 160 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 161 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 162 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 163 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 164 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 165 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 166 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 167 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 168 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 169 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 170 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 171 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 172 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 173 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 174 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ 175 176 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 177 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 178 179 #undef CONFIG_SYS_FLASH_CHECKSUM 180 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 181 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 182 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 183 184 #define CONFIG_FLASH_CFI_DRIVER 185 #define CONFIG_SYS_FLASH_CFI 186 #define CONFIG_SYS_FLASH_EMPTY_INFO 187 188 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 189 #define CONFIG_SYS_RAMBOOT 190 #else 191 #undef CONFIG_SYS_RAMBOOT 192 #endif 193 194 #if defined(CONFIG_SYS_RAMBOOT) 195 #undef CONFIG_SPD_EEPROM 196 #define CONFIG_SYS_SDRAM_SIZE 256 197 #endif 198 199 #undef CONFIG_CLOCKS_IN_MHZ 200 201 #define CONFIG_L1_INIT_RAM 202 #define CONFIG_SYS_INIT_RAM_LOCK 1 203 #ifndef CONFIG_SYS_INIT_RAM_LOCK 204 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 205 #else 206 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 207 #endif 208 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 209 210 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 211 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 212 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 213 214 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 215 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 216 217 /* Serial Port */ 218 #define CONFIG_CONS_INDEX 1 219 #undef CONFIG_SERIAL_SOFTWARE_FIFO 220 #define CONFIG_SYS_NS16550 221 #define CONFIG_SYS_NS16550_SERIAL 222 #define CONFIG_SYS_NS16550_REG_SIZE 1 223 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 224 225 #define CONFIG_SYS_BAUDRATE_TABLE \ 226 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 227 228 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 229 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 230 231 /* Use the HUSH parser */ 232 #define CONFIG_SYS_HUSH_PARSER 233 #ifdef CONFIG_SYS_HUSH_PARSER 234 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 235 #endif 236 237 /* 238 * Pass open firmware flat tree to kernel 239 */ 240 #define CONFIG_OF_LIBFDT 1 241 #define CONFIG_OF_BOARD_SETUP 1 242 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 243 244 245 /* maximum size of the flat tree (8K) */ 246 #define OF_FLAT_TREE_MAX_SIZE 8192 247 248 #define CONFIG_SYS_64BIT_VSPRINTF 1 249 #define CONFIG_SYS_64BIT_STRTOUL 1 250 251 /* 252 * I2C 253 */ 254 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 255 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 256 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 257 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 258 #define CONFIG_SYS_I2C_SLAVE 0x7F 259 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 260 #define CONFIG_SYS_I2C_OFFSET 0x3000 261 262 /* 263 * General PCI 264 * Addresses are mapped 1-1. 265 */ 266 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 267 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 268 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 269 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 270 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 271 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 272 273 /* For RTL8139 */ 274 #define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) 275 #define _IO_BASE 0x00000000 276 277 /* controller 1, Base address 0xa000 */ 278 #define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 279 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE 280 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 281 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 282 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 283 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 284 285 /* controller 2, Base Address 0x9000 */ 286 #define CONFIG_SYS_PCIE2_MEM_BASE 0x90000000 287 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE 288 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 289 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */ 290 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 291 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 292 293 294 #if defined(CONFIG_PCI) 295 296 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 297 298 #define CONFIG_NET_MULTI 299 #define CONFIG_CMD_NET 300 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 301 #define CONFIG_CMD_REGINFO 302 303 #define CONFIG_ULI526X 304 #ifdef CONFIG_ULI526X 305 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 306 #endif 307 308 /************************************************************ 309 * USB support 310 ************************************************************/ 311 #define CONFIG_PCI_OHCI 1 312 #define CONFIG_USB_OHCI_NEW 1 313 #define CONFIG_USB_KEYBOARD 1 314 #define CONFIG_SYS_DEVICE_DEREGISTER 315 #define CONFIG_SYS_USB_EVENT_POLL 1 316 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 317 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 318 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 319 320 #if !defined(CONFIG_PCI_PNP) 321 #define PCI_ENET0_IOADDR 0xe0000000 322 #define PCI_ENET0_MEMADDR 0xe0000000 323 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 324 #endif 325 326 #define CONFIG_DOS_PARTITION 327 #define CONFIG_SCSI_AHCI 328 329 #ifdef CONFIG_SCSI_AHCI 330 #define CONFIG_SATA_ULI5288 331 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 332 #define CONFIG_SYS_SCSI_MAX_LUN 1 333 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 334 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 335 #endif 336 337 #endif /* CONFIG_PCI */ 338 339 /* 340 * BAT0 2G Cacheable, non-guarded 341 * 0x0000_0000 2G DDR 342 */ 343 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 344 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 345 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 346 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 347 348 /* 349 * BAT1 1G Cache-inhibited, guarded 350 * 0x8000_0000 256M PCI-1 Memory 351 * 0xa000_0000 256M PCI-Express 1 Memory 352 * 0x9000_0000 256M PCI-Express 2 Memory 353 */ 354 355 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 356 | BATL_GUARDEDSTORAGE) 357 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) 358 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 359 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 360 361 /* 362 * BAT2 16M Cache-inhibited, guarded 363 * 0xe100_0000 1M PCI-1 I/O 364 */ 365 366 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 367 | BATL_GUARDEDSTORAGE) 368 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP) 369 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 370 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 371 372 /* 373 * BAT3 4M Cache-inhibited, guarded 374 * 0xe000_0000 4M CCSR 375 */ 376 377 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 378 | BATL_GUARDEDSTORAGE) 379 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 380 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 381 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 382 383 /* 384 * BAT4 32M Cache-inhibited, guarded 385 * 0xe200_0000 1M PCI-Express 2 I/O 386 * 0xe300_0000 1M PCI-Express 1 I/O 387 */ 388 389 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 390 | BATL_GUARDEDSTORAGE) 391 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 392 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 393 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 394 395 396 /* 397 * BAT5 128K Cacheable, non-guarded 398 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 399 */ 400 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 401 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 402 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 403 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 404 405 /* 406 * BAT6 256M Cache-inhibited, guarded 407 * 0xf000_0000 256M FLASH 408 */ 409 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 410 | BATL_GUARDEDSTORAGE) 411 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 412 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 413 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 414 415 /* 416 * BAT7 4M Cache-inhibited, guarded 417 * 0xe800_0000 4M PIXIS 418 */ 419 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 420 | BATL_GUARDEDSTORAGE) 421 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 422 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 423 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 424 425 426 /* 427 * Environment 428 */ 429 #ifndef CONFIG_SYS_RAMBOOT 430 #define CONFIG_ENV_IS_IN_FLASH 1 431 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 432 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 433 #define CONFIG_ENV_SIZE 0x2000 434 #else 435 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 436 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 437 #define CONFIG_ENV_SIZE 0x2000 438 #endif 439 440 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 441 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 442 443 444 /* 445 * BOOTP options 446 */ 447 #define CONFIG_BOOTP_BOOTFILESIZE 448 #define CONFIG_BOOTP_BOOTPATH 449 #define CONFIG_BOOTP_GATEWAY 450 #define CONFIG_BOOTP_HOSTNAME 451 452 453 /* 454 * Command line configuration. 455 */ 456 #include <config_cmd_default.h> 457 458 #define CONFIG_CMD_PING 459 #define CONFIG_CMD_I2C 460 #define CONFIG_CMD_MII 461 462 #if defined(CONFIG_SYS_RAMBOOT) 463 #undef CONFIG_CMD_ENV 464 #endif 465 466 #if defined(CONFIG_PCI) 467 #define CONFIG_CMD_PCI 468 #define CONFIG_CMD_SCSI 469 #define CONFIG_CMD_EXT2 470 #define CONFIG_CMD_USB 471 #endif 472 473 474 #define CONFIG_WATCHDOG /* watchdog enabled */ 475 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 476 477 /*DIU Configuration*/ 478 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ 479 480 /* 481 * Miscellaneous configurable options 482 */ 483 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 484 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 485 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 486 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 487 488 #if defined(CONFIG_CMD_KGDB) 489 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 490 #else 491 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 492 #endif 493 494 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 495 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 496 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 497 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 498 499 /* 500 * For booting Linux, the board info and command line data 501 * have to be in the first 8 MB of memory, since this is 502 * the maximum mapped by the Linux kernel during initialization. 503 */ 504 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 505 506 /* 507 * Internal Definitions 508 * 509 * Boot Flags 510 */ 511 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 512 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 513 514 #if defined(CONFIG_CMD_KGDB) 515 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 516 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 517 #endif 518 519 /* 520 * Environment Configuration 521 */ 522 #define CONFIG_IPADDR 192.168.1.100 523 524 #define CONFIG_HOSTNAME unknown 525 #define CONFIG_ROOTPATH /opt/nfsroot 526 #define CONFIG_BOOTFILE uImage 527 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 528 529 #define CONFIG_SERVERIP 192.168.1.1 530 #define CONFIG_GATEWAYIP 192.168.1.1 531 #define CONFIG_NETMASK 255.255.255.0 532 533 /* default location for tftp and bootm */ 534 #define CONFIG_LOADADDR 1000000 535 536 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 537 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 538 539 #define CONFIG_BAUDRATE 115200 540 541 #if defined(CONFIG_PCI1) 542 #define PCI_ENV \ 543 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 544 "echo e;md ${a}e00 9\0" \ 545 "pci1regs=setenv a e0008; run pcireg\0" \ 546 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 547 "pci d.w $b.0 56 1\0" \ 548 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 549 "pci w.w $b.0 56 ffff\0" \ 550 "pci1err=setenv a e0008; run pcierr\0" \ 551 "pci1errc=setenv a e0008; run pcierrc\0" 552 #else 553 #define PCI_ENV "" 554 #endif 555 556 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 557 #define PCIE_ENV \ 558 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 559 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 560 "pcie1regs=setenv a e000a; run pciereg\0" \ 561 "pcie2regs=setenv a e0009; run pciereg\0" \ 562 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 563 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 564 "pci d $b.0 130 1\0" \ 565 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 566 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 567 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 568 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 569 "pcie1err=setenv a e000a; run pcieerr\0" \ 570 "pcie2err=setenv a e0009; run pcieerr\0" \ 571 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 572 "pcie2errc=setenv a e0009; run pcieerrc\0" 573 #else 574 #define PCIE_ENV "" 575 #endif 576 577 #define DMA_ENV \ 578 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 579 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 580 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 581 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 582 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 583 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 584 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 585 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 586 587 #ifdef ENV_DEBUG 588 #define CONFIG_EXTRA_ENV_SETTINGS \ 589 "netdev=eth0\0" \ 590 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 591 "tftpflash=tftpboot $loadaddr $uboot; " \ 592 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 593 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 594 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 595 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 596 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 597 "consoledev=ttyS0\0" \ 598 "ramdiskaddr=2000000\0" \ 599 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 600 "fdtaddr=c00000\0" \ 601 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 602 "bdev=sda3\0" \ 603 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 604 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 605 "maxcpus=1" \ 606 "eoi=mw e00400b0 0\0" \ 607 "iack=md e00400a0 1\0" \ 608 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 609 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 610 "md ${a}f00 5\0" \ 611 "ddr1regs=setenv a e0002; run ddrreg\0" \ 612 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 613 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 614 "md ${a}e60 1; md ${a}ef0 1d\0" \ 615 "guregs=setenv a e00e0; run gureg\0" \ 616 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 617 "mcmregs=setenv a e0001; run mcmreg\0" \ 618 "diuregs=md e002c000 1d\0" \ 619 "dium=mw e002c01c\0" \ 620 "diuerr=md e002c014 1\0" \ 621 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ 622 "monitor=0-DVI\0" \ 623 "pmregs=md e00e1000 2b\0" \ 624 "lawregs=md e0000c08 4b\0" \ 625 "lbcregs=md e0005000 36\0" \ 626 "dma0regs=md e0021100 12\0" \ 627 "dma1regs=md e0021180 12\0" \ 628 "dma2regs=md e0021200 12\0" \ 629 "dma3regs=md e0021280 12\0" \ 630 PCI_ENV \ 631 PCIE_ENV \ 632 DMA_ENV 633 #else 634 #define CONFIG_EXTRA_ENV_SETTINGS \ 635 "netdev=eth0\0" \ 636 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 637 "consoledev=ttyS0\0" \ 638 "ramdiskaddr=2000000\0" \ 639 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 640 "fdtaddr=c00000\0" \ 641 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 642 "bdev=sda3\0" \ 643 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ 644 "monitor=0-DVI\0" 645 #endif 646 647 #define CONFIG_NFSBOOTCOMMAND \ 648 "setenv bootargs root=/dev/nfs rw " \ 649 "nfsroot=$serverip:$rootpath " \ 650 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 651 "console=$consoledev,$baudrate $othbootargs;" \ 652 "tftp $loadaddr $bootfile;" \ 653 "tftp $fdtaddr $fdtfile;" \ 654 "bootm $loadaddr - $fdtaddr" 655 656 #define CONFIG_RAMBOOTCOMMAND \ 657 "setenv bootargs root=/dev/ram rw " \ 658 "console=$consoledev,$baudrate $othbootargs;" \ 659 "tftp $ramdiskaddr $ramdiskfile;" \ 660 "tftp $loadaddr $bootfile;" \ 661 "tftp $fdtaddr $fdtfile;" \ 662 "bootm $loadaddr $ramdiskaddr $fdtaddr" 663 664 #define CONFIG_BOOTCOMMAND \ 665 "setenv bootargs root=/dev/$bdev rw " \ 666 "console=$consoledev,$baudrate $othbootargs;" \ 667 "tftp $loadaddr $bootfile;" \ 668 "tftp $fdtaddr $fdtfile;" \ 669 "bootm $loadaddr - $fdtaddr" 670 671 #endif /* __CONFIG_H */ 672