1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8569mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 34 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 35 36 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 37 38 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 39 #define CONFIG_PCIE1 1 /* PCIE controller */ 40 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 41 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 42 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 43 #define CONFIG_QE /* Enable QE */ 44 #define CONFIG_ENV_OVERWRITE 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #ifndef __ASSEMBLY__ 48 extern unsigned long get_clock_freq(void); 49 #endif 50 /* Replace a call to get_clock_freq (after it is implemented)*/ 51 #define CONFIG_SYS_CLK_FREQ 66666666 52 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 53 54 #ifdef CONFIG_ATM 55 #define CONFIG_PQ_MDS_PIB 56 #define CONFIG_PQ_MDS_PIB_ATM 57 #endif 58 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_L2_CACHE /* toggle L2 cache */ 63 #define CONFIG_BTB /* toggle branch predition */ 64 65 #ifdef CONFIG_NAND 66 #define CONFIG_NAND_U_BOOT 1 67 #define CONFIG_RAMBOOT_NAND 1 68 #ifdef CONFIG_NAND_SPL 69 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 70 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 71 #else 72 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 73 #endif 74 #endif 75 76 #ifndef CONFIG_SYS_TEXT_BASE 77 #define CONFIG_SYS_TEXT_BASE 0xfff80000 78 #endif 79 80 #ifndef CONFIG_SYS_MONITOR_BASE 81 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 82 #endif 83 84 /* 85 * Only possible on E500 Version 2 or newer cores. 86 */ 87 #define CONFIG_ENABLE_36BIT_PHYS 1 88 89 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 90 #define CONFIG_BOARD_EARLY_INIT_R 1 91 #define CONFIG_HWCONFIG 92 93 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 94 #define CONFIG_SYS_MEMTEST_END 0x00400000 95 96 /* 97 * Config the L2 Cache as L2 SRAM 98 */ 99 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 100 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 101 #define CONFIG_SYS_L2_SIZE (512 << 10) 102 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 103 104 /* 105 * Base addresses -- Note these are effective addresses where the 106 * actual resources get mapped (not physical addresses) 107 */ 108 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 109 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 110 /* physical addr of CCSRBAR */ 111 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 112 /* PQII uses CONFIG_SYS_IMMR */ 113 114 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 115 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 116 #else 117 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 118 #endif 119 120 /* DDR Setup */ 121 #define CONFIG_FSL_DDR3 122 #undef CONFIG_FSL_DDR_INTERACTIVE 123 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 124 #define CONFIG_DDR_SPD 125 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 126 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 127 128 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 129 130 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 131 /* DDR is system memory*/ 132 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 133 134 #define CONFIG_NUM_DDR_CONTROLLERS 1 135 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 136 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 137 138 /* I2C addresses of SPD EEPROMs */ 139 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 140 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 141 142 /* These are used when DDR doesn't use SPD. */ 143 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 144 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 145 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 146 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 147 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 148 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 149 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 150 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 151 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 152 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 153 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 154 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 155 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 156 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 157 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 158 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 159 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 160 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 161 #define CONFIG_SYS_DDR_CDR_1 0x80040000 162 #define CONFIG_SYS_DDR_CDR_2 0x00000000 163 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 164 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 165 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 166 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 167 168 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 169 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 170 #define CONFIG_SYS_DDR_SBE 0x00010000 171 172 #undef CONFIG_CLOCKS_IN_MHZ 173 174 /* 175 * Local Bus Definitions 176 */ 177 178 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 179 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 180 181 #define CONFIG_SYS_BCSR_BASE 0xf8000000 182 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 183 184 /*Chip select 0 - Flash*/ 185 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 186 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 187 188 /*Chip select 1 - BCSR*/ 189 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 190 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 191 192 /*Chip select 4 - PIB*/ 193 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 194 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 195 196 /*Chip select 5 - PIB*/ 197 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 198 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 199 200 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 201 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 202 #undef CONFIG_SYS_FLASH_CHECKSUM 203 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 204 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 205 206 #if defined(CONFIG_RAMBOOT_NAND) 207 #define CONFIG_SYS_RAMBOOT 208 #define CONFIG_SYS_EXTRA_ENV_RELOC 209 #else 210 #undef CONFIG_SYS_RAMBOOT 211 #endif 212 213 #define CONFIG_FLASH_CFI_DRIVER 214 #define CONFIG_SYS_FLASH_CFI 215 #define CONFIG_SYS_FLASH_EMPTY_INFO 216 217 /* Chip select 3 - NAND */ 218 #ifndef CONFIG_NAND_SPL 219 #define CONFIG_SYS_NAND_BASE 0xFC000000 220 #else 221 #define CONFIG_SYS_NAND_BASE 0xFFF00000 222 #endif 223 224 /* NAND boot: 4K NAND loader config */ 225 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 226 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 227 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 228 #define CONFIG_SYS_NAND_U_BOOT_START \ 229 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 230 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 231 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 232 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 233 234 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 235 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 236 #define CONFIG_SYS_MAX_NAND_DEVICE 1 237 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 238 #define CONFIG_CMD_NAND 1 239 #define CONFIG_NAND_FSL_ELBC 1 240 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 241 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 242 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 243 | BR_PS_8 /* Port Size = 8 bit */ \ 244 | BR_MS_FCM /* MSEL = FCM */ \ 245 | BR_V) /* valid */ 246 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 247 | OR_FCM_CSCT \ 248 | OR_FCM_CST \ 249 | OR_FCM_CHT \ 250 | OR_FCM_SCY_1 \ 251 | OR_FCM_TRLX \ 252 | OR_FCM_EHTR) 253 254 #ifdef CONFIG_RAMBOOT_NAND 255 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 256 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 257 #define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 258 #define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 259 #else 260 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 261 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 262 #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 263 #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 264 #endif 265 266 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 267 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 268 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 269 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 270 271 #define CONFIG_SYS_INIT_RAM_LOCK 1 272 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 273 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 274 275 #define CONFIG_SYS_GBL_DATA_OFFSET \ 276 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 277 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 278 279 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 280 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 281 282 /* Serial Port */ 283 #define CONFIG_CONS_INDEX 1 284 #define CONFIG_SERIAL_MULTI 1 285 #define CONFIG_SYS_NS16550 286 #define CONFIG_SYS_NS16550_SERIAL 287 #define CONFIG_SYS_NS16550_REG_SIZE 1 288 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 289 #ifdef CONFIG_NAND_SPL 290 #define CONFIG_NS16550_MIN_FUNCTIONS 291 #endif 292 293 #define CONFIG_SYS_BAUDRATE_TABLE \ 294 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 295 296 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 297 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 298 299 /* Use the HUSH parser*/ 300 #define CONFIG_SYS_HUSH_PARSER 301 #ifdef CONFIG_SYS_HUSH_PARSER 302 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 303 #endif 304 305 /* pass open firmware flat tree */ 306 #define CONFIG_OF_LIBFDT 1 307 #define CONFIG_OF_BOARD_SETUP 1 308 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 309 310 /* 311 * I2C 312 */ 313 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 314 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 315 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 316 #define CONFIG_I2C_MULTI_BUS 317 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 318 #define CONFIG_SYS_I2C_SLAVE 0x7F 319 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 320 #define CONFIG_SYS_I2C_OFFSET 0x3000 321 #define CONFIG_SYS_I2C2_OFFSET 0x3100 322 323 /* 324 * I2C2 EEPROM 325 */ 326 #define CONFIG_ID_EEPROM 327 #ifdef CONFIG_ID_EEPROM 328 #define CONFIG_SYS_I2C_EEPROM_NXID 329 #endif 330 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 331 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 332 #define CONFIG_SYS_EEPROM_BUS_NUM 1 333 334 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 335 #define PLPPAR1_I2C2_VAL 0x00000000 336 #define PLPPAR1_ESDHC_VAL 0x0000000A 337 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 338 #define PLPDIR1_I2C2_VAL 0x0000000F 339 #define PLPDIR1_ESDHC_VAL 0x00000006 340 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 341 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 342 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 343 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 344 345 /* 346 * General PCI 347 * Memory Addresses are mapped 1-1. I/O is mapped from 0 348 */ 349 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 350 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 351 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 352 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 353 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 354 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 355 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 356 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 357 358 #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 359 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 360 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 361 362 #ifdef CONFIG_QE 363 /* 364 * QE UEC ethernet configuration 365 */ 366 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 367 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 368 369 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 370 #define CONFIG_UEC_ETH 371 #define CONFIG_ETHPRIME "UEC0" 372 #define CONFIG_PHY_MODE_NEED_CHANGE 373 374 #define CONFIG_UEC_ETH1 /* GETH1 */ 375 #define CONFIG_HAS_ETH0 376 377 #ifdef CONFIG_UEC_ETH1 378 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 379 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 380 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 381 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 382 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 383 #define CONFIG_SYS_UEC1_PHY_ADDR 7 384 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID 385 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 386 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 387 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 388 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 389 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 390 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII 391 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 392 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 393 #endif /* CONFIG_UEC_ETH1 */ 394 395 #define CONFIG_UEC_ETH2 /* GETH2 */ 396 #define CONFIG_HAS_ETH1 397 398 #ifdef CONFIG_UEC_ETH2 399 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 400 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 401 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 402 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 403 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 404 #define CONFIG_SYS_UEC2_PHY_ADDR 1 405 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID 406 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 407 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 408 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 409 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 410 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 411 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII 412 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 413 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 414 #endif /* CONFIG_UEC_ETH2 */ 415 416 #define CONFIG_UEC_ETH3 /* GETH3 */ 417 #define CONFIG_HAS_ETH2 418 419 #ifdef CONFIG_UEC_ETH3 420 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 421 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 422 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 423 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 424 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 425 #define CONFIG_SYS_UEC3_PHY_ADDR 2 426 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID 427 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 428 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 429 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 430 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 431 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 432 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII 433 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 434 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 435 #endif /* CONFIG_UEC_ETH3 */ 436 437 #define CONFIG_UEC_ETH4 /* GETH4 */ 438 #define CONFIG_HAS_ETH3 439 440 #ifdef CONFIG_UEC_ETH4 441 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 442 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 443 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 444 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 445 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 446 #define CONFIG_SYS_UEC4_PHY_ADDR 3 447 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID 448 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 449 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 450 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 451 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 452 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 453 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII 454 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 455 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 456 #endif /* CONFIG_UEC_ETH4 */ 457 458 #undef CONFIG_UEC_ETH6 /* GETH6 */ 459 #define CONFIG_HAS_ETH5 460 461 #ifdef CONFIG_UEC_ETH6 462 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 463 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 464 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 465 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 466 #define CONFIG_SYS_UEC6_PHY_ADDR 4 467 #define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII 468 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 469 #endif /* CONFIG_UEC_ETH6 */ 470 471 #undef CONFIG_UEC_ETH8 /* GETH8 */ 472 #define CONFIG_HAS_ETH7 473 474 #ifdef CONFIG_UEC_ETH8 475 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 476 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 477 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 478 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 479 #define CONFIG_SYS_UEC8_PHY_ADDR 6 480 #define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII 481 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 482 #endif /* CONFIG_UEC_ETH8 */ 483 484 #endif /* CONFIG_QE */ 485 486 #if defined(CONFIG_PCI) 487 488 #define CONFIG_NET_MULTI 489 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 490 491 #undef CONFIG_EEPRO100 492 #undef CONFIG_TULIP 493 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 494 495 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 496 497 #endif /* CONFIG_PCI */ 498 499 #ifndef CONFIG_NET_MULTI 500 #define CONFIG_NET_MULTI 1 501 #endif 502 503 /* 504 * Environment 505 */ 506 #if defined(CONFIG_SYS_RAMBOOT) 507 #if defined(CONFIG_RAMBOOT_NAND) 508 #define CONFIG_ENV_IS_IN_NAND 1 509 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 510 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 511 #endif 512 #else 513 #define CONFIG_ENV_IS_IN_FLASH 1 514 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 515 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 516 #define CONFIG_ENV_SIZE 0x2000 517 #endif 518 519 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 520 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 521 522 /* QE microcode/firmware address */ 523 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 524 525 /* 526 * BOOTP options 527 */ 528 #define CONFIG_BOOTP_BOOTFILESIZE 529 #define CONFIG_BOOTP_BOOTPATH 530 #define CONFIG_BOOTP_GATEWAY 531 #define CONFIG_BOOTP_HOSTNAME 532 533 534 /* 535 * Command line configuration. 536 */ 537 #include <config_cmd_default.h> 538 539 #define CONFIG_CMD_PING 540 #define CONFIG_CMD_I2C 541 #define CONFIG_CMD_MII 542 #define CONFIG_CMD_ELF 543 #define CONFIG_CMD_IRQ 544 #define CONFIG_CMD_SETEXPR 545 #define CONFIG_CMD_REGINFO 546 547 #if defined(CONFIG_PCI) 548 #define CONFIG_CMD_PCI 549 #endif 550 551 552 #undef CONFIG_WATCHDOG /* watchdog disabled */ 553 554 #define CONFIG_MMC 1 555 556 #ifdef CONFIG_MMC 557 #define CONFIG_FSL_ESDHC 558 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 559 #define CONFIG_CMD_MMC 560 #define CONFIG_GENERIC_MMC 561 #define CONFIG_CMD_EXT2 562 #define CONFIG_CMD_FAT 563 #define CONFIG_DOS_PARTITION 564 #endif 565 566 /* 567 * Miscellaneous configurable options 568 */ 569 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 570 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 571 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 572 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 573 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 574 #if defined(CONFIG_CMD_KGDB) 575 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 576 #else 577 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 578 #endif 579 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 580 /* Print Buffer Size */ 581 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 582 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 583 /* Boot Argument Buffer Size */ 584 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 585 586 /* 587 * For booting Linux, the board info and command line data 588 * have to be in the first 16 MB of memory, since this is 589 * the maximum mapped by the Linux kernel during initialization. 590 */ 591 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) 592 /* Initial Memory map for Linux*/ 593 594 #if defined(CONFIG_CMD_KGDB) 595 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 596 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 597 #endif 598 599 /* 600 * Environment Configuration 601 */ 602 #define CONFIG_HOSTNAME mpc8569mds 603 #define CONFIG_ROOTPATH /nfsroot 604 #define CONFIG_BOOTFILE your.uImage 605 606 #define CONFIG_SERVERIP 192.168.1.1 607 #define CONFIG_GATEWAYIP 192.168.1.1 608 #define CONFIG_NETMASK 255.255.255.0 609 610 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 611 612 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 613 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 614 615 #define CONFIG_BAUDRATE 115200 616 617 #define CONFIG_EXTRA_ENV_SETTINGS \ 618 "netdev=eth0\0" \ 619 "consoledev=ttyS0\0" \ 620 "ramdiskaddr=600000\0" \ 621 "ramdiskfile=your.ramdisk.u-boot\0" \ 622 "fdtaddr=400000\0" \ 623 "fdtfile=your.fdt.dtb\0" \ 624 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 625 "nfsroot=$serverip:$rootpath " \ 626 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 627 "console=$consoledev,$baudrate $othbootargs\0" \ 628 "ramargs=setenv bootargs root=/dev/ram rw " \ 629 "console=$consoledev,$baudrate $othbootargs\0" \ 630 631 #define CONFIG_NFSBOOTCOMMAND \ 632 "run nfsargs;" \ 633 "tftp $loadaddr $bootfile;" \ 634 "tftp $fdtaddr $fdtfile;" \ 635 "bootm $loadaddr - $fdtaddr" 636 637 #define CONFIG_RAMBOOTCOMMAND \ 638 "run ramargs;" \ 639 "tftp $ramdiskaddr $ramdiskfile;" \ 640 "tftp $loadaddr $bootfile;" \ 641 "bootm $loadaddr $ramdiskaddr" 642 643 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 644 645 #endif /* __CONFIG_H */ 646