1 /* 2 * Copyright (C) 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8569mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 34 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 35 36 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 37 38 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 39 #define CONFIG_PCIE1 1 /* PCIE controller */ 40 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 41 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 42 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 43 #define CONFIG_QE /* Enable QE */ 44 #define CONFIG_ENV_OVERWRITE 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #ifndef __ASSEMBLY__ 48 extern unsigned long get_clock_freq(void); 49 #endif 50 /* Replace a call to get_clock_freq (after it is implemented)*/ 51 #define CONFIG_SYS_CLK_FREQ 66666666 52 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 53 54 #ifdef CONFIG_MK_ATM 55 #define CONFIG_PQ_MDS_PIB 56 #define CONFIG_PQ_MDS_PIB_ATM 57 #endif 58 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_L2_CACHE /* toggle L2 cache */ 63 #define CONFIG_BTB /* toggle branch predition */ 64 65 /* 66 * Only possible on E500 Version 2 or newer cores. 67 */ 68 #define CONFIG_ENABLE_36BIT_PHYS 1 69 70 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 71 #define CONFIG_HWCONFIG 72 73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 74 #define CONFIG_SYS_MEMTEST_END 0x00400000 75 76 /* 77 * Base addresses -- Note these are effective addresses where the 78 * actual resources get mapped (not physical addresses) 79 */ 80 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 81 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 82 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 83 /* physical addr of CCSRBAR */ 84 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 85 /* PQII uses CONFIG_SYS_IMMR */ 86 87 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 88 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 89 90 /* DDR Setup */ 91 #define CONFIG_FSL_DDR3 92 #undef CONFIG_FSL_DDR_INTERACTIVE 93 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 94 #define CONFIG_DDR_SPD 95 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 96 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 97 98 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 99 100 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 101 /* DDR is system memory*/ 102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 103 104 #define CONFIG_NUM_DDR_CONTROLLERS 1 105 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 106 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 107 108 /* I2C addresses of SPD EEPROMs */ 109 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 110 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 111 112 /* These are used when DDR doesn't use SPD. */ 113 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 114 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 115 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 116 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 117 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 118 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 119 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 120 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 121 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 122 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 123 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 124 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 125 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 126 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 127 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 128 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 129 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 130 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 131 #define CONFIG_SYS_DDR_CDR_1 0x80040000 132 #define CONFIG_SYS_DDR_CDR_2 0x00000000 133 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 134 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 135 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 136 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 137 138 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 139 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 140 #define CONFIG_SYS_DDR_SBE 0x00010000 141 142 #undef CONFIG_CLOCKS_IN_MHZ 143 144 /* 145 * Local Bus Definitions 146 */ 147 148 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 149 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 150 151 #define CONFIG_SYS_BCSR_BASE 0xf8000000 152 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 153 154 /*Chip select 0 - Flash*/ 155 #define CONFIG_SYS_BR0_PRELIM 0xfe000801 156 #define CONFIG_SYS_OR0_PRELIM 0xfe000ff7 157 158 /*Chip select 1 - BCSR*/ 159 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 160 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 161 162 /*Chip select 4 - PIB*/ 163 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 164 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 165 166 /*Chip select 5 - PIB*/ 167 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 168 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 169 170 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 171 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 172 #undef CONFIG_SYS_FLASH_CHECKSUM 173 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 174 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 175 176 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 177 178 #define CONFIG_FLASH_CFI_DRIVER 179 #define CONFIG_SYS_FLASH_CFI 180 #define CONFIG_SYS_FLASH_EMPTY_INFO 181 182 /* Chip select 3 - NAND */ 183 #define CONFIG_SYS_NAND_BASE 0xFC000000 184 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 185 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 186 #define CONFIG_SYS_MAX_NAND_DEVICE 1 187 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 188 #define CONFIG_CMD_NAND 1 189 #define CONFIG_NAND_FSL_ELBC 1 190 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 191 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 192 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 193 | BR_PS_8 /* Port Size = 8 bit */ \ 194 | BR_MS_FCM /* MSEL = FCM */ \ 195 | BR_V) /* valid */ 196 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 197 | OR_FCM_CSCT \ 198 | OR_FCM_CST \ 199 | OR_FCM_CHT \ 200 | OR_FCM_SCY_1 \ 201 | OR_FCM_TRLX \ 202 | OR_FCM_EHTR) 203 #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 204 #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 205 206 /* 207 * SDRAM on the LocalBus 208 */ 209 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 210 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 211 212 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 213 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 214 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 215 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 216 217 #define CONFIG_SYS_INIT_RAM_LOCK 1 218 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 219 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 220 221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 222 #define CONFIG_SYS_GBL_DATA_OFFSET \ 223 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 224 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 225 226 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 227 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 228 229 /* Serial Port */ 230 #define CONFIG_CONS_INDEX 1 231 #define CONFIG_SERIAL_MULTI 1 232 #undef CONFIG_SERIAL_SOFTWARE_FIFO 233 #define CONFIG_SYS_NS16550 234 #define CONFIG_SYS_NS16550_SERIAL 235 #define CONFIG_SYS_NS16550_REG_SIZE 1 236 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 237 238 #define CONFIG_SYS_BAUDRATE_TABLE \ 239 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 240 241 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 242 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 243 244 /* Use the HUSH parser*/ 245 #define CONFIG_SYS_HUSH_PARSER 246 #ifdef CONFIG_SYS_HUSH_PARSER 247 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 248 #endif 249 250 /* pass open firmware flat tree */ 251 #define CONFIG_OF_LIBFDT 1 252 #define CONFIG_OF_BOARD_SETUP 1 253 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 254 255 /* 256 * I2C 257 */ 258 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 259 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 260 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 261 #define CONFIG_I2C_MULTI_BUS 262 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 263 #define CONFIG_SYS_I2C_SLAVE 0x7F 264 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 265 #define CONFIG_SYS_I2C_OFFSET 0x3000 266 #define CONFIG_SYS_I2C2_OFFSET 0x3100 267 268 /* 269 * I2C2 EEPROM 270 */ 271 #define CONFIG_ID_EEPROM 272 #ifdef CONFIG_ID_EEPROM 273 #define CONFIG_SYS_I2C_EEPROM_NXID 274 #endif 275 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 276 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 277 #define CONFIG_SYS_EEPROM_BUS_NUM 1 278 279 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 280 #define PLPPAR1_I2C2_VAL 0x00000000 281 #define PLPPAR1_ESDHC_VAL 0x0000000A 282 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 283 #define PLPDIR1_I2C2_VAL 0x0000000F 284 #define PLPDIR1_ESDHC_VAL 0x00000006 285 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 286 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 287 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 288 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 289 290 /* 291 * General PCI 292 * Memory Addresses are mapped 1-1. I/O is mapped from 0 293 */ 294 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 295 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 296 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 297 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 298 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 299 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 300 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 301 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 302 303 #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 304 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 305 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 306 307 #ifdef CONFIG_QE 308 /* 309 * QE UEC ethernet configuration 310 */ 311 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 312 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 313 314 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 315 #define CONFIG_UEC_ETH 316 #define CONFIG_ETHPRIME "FSL UEC0" 317 #define CONFIG_PHY_MODE_NEED_CHANGE 318 319 #define CONFIG_UEC_ETH1 /* GETH1 */ 320 #define CONFIG_HAS_ETH0 321 322 #ifdef CONFIG_UEC_ETH1 323 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 324 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 325 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 326 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 327 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 328 #define CONFIG_SYS_UEC1_PHY_ADDR 7 329 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID 330 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 331 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 332 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 333 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 334 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 335 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII 336 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 337 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 338 #endif /* CONFIG_UEC_ETH1 */ 339 340 #define CONFIG_UEC_ETH2 /* GETH2 */ 341 #define CONFIG_HAS_ETH1 342 343 #ifdef CONFIG_UEC_ETH2 344 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 345 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 346 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 347 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 348 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 349 #define CONFIG_SYS_UEC2_PHY_ADDR 1 350 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID 351 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 352 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 353 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 354 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 355 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 356 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII 357 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 358 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 359 #endif /* CONFIG_UEC_ETH2 */ 360 361 #define CONFIG_UEC_ETH3 /* GETH3 */ 362 #define CONFIG_HAS_ETH2 363 364 #ifdef CONFIG_UEC_ETH3 365 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 366 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 367 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 368 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 369 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 370 #define CONFIG_SYS_UEC3_PHY_ADDR 2 371 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID 372 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 373 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 374 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 375 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 376 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 377 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII 378 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 379 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 380 #endif /* CONFIG_UEC_ETH3 */ 381 382 #define CONFIG_UEC_ETH4 /* GETH4 */ 383 #define CONFIG_HAS_ETH3 384 385 #ifdef CONFIG_UEC_ETH4 386 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 387 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 388 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 389 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 390 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 391 #define CONFIG_SYS_UEC4_PHY_ADDR 3 392 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID 393 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 394 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 395 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 396 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 397 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 398 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII 399 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 400 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 401 #endif /* CONFIG_UEC_ETH4 */ 402 403 #undef CONFIG_UEC_ETH6 /* GETH6 */ 404 #define CONFIG_HAS_ETH5 405 406 #ifdef CONFIG_UEC_ETH6 407 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 408 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 409 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 410 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 411 #define CONFIG_SYS_UEC6_PHY_ADDR 4 412 #define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII 413 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 414 #endif /* CONFIG_UEC_ETH6 */ 415 416 #undef CONFIG_UEC_ETH8 /* GETH8 */ 417 #define CONFIG_HAS_ETH7 418 419 #ifdef CONFIG_UEC_ETH8 420 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 421 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 422 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 423 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 424 #define CONFIG_SYS_UEC8_PHY_ADDR 6 425 #define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII 426 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 427 #endif /* CONFIG_UEC_ETH8 */ 428 429 #endif /* CONFIG_QE */ 430 431 #if defined(CONFIG_PCI) 432 433 #define CONFIG_NET_MULTI 434 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 435 436 #undef CONFIG_EEPRO100 437 #undef CONFIG_TULIP 438 439 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 440 441 #endif /* CONFIG_PCI */ 442 443 #ifndef CONFIG_NET_MULTI 444 #define CONFIG_NET_MULTI 1 445 #endif 446 447 /* 448 * Environment 449 */ 450 #define CONFIG_ENV_IS_IN_FLASH 1 451 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 452 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ 453 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 454 455 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 456 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 457 458 /* QE microcode/firmware address */ 459 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 460 461 /* 462 * BOOTP options 463 */ 464 #define CONFIG_BOOTP_BOOTFILESIZE 465 #define CONFIG_BOOTP_BOOTPATH 466 #define CONFIG_BOOTP_GATEWAY 467 #define CONFIG_BOOTP_HOSTNAME 468 469 470 /* 471 * Command line configuration. 472 */ 473 #include <config_cmd_default.h> 474 475 #define CONFIG_CMD_PING 476 #define CONFIG_CMD_I2C 477 #define CONFIG_CMD_MII 478 #define CONFIG_CMD_ELF 479 #define CONFIG_CMD_IRQ 480 #define CONFIG_CMD_SETEXPR 481 482 #if defined(CONFIG_PCI) 483 #define CONFIG_CMD_PCI 484 #endif 485 486 487 #undef CONFIG_WATCHDOG /* watchdog disabled */ 488 489 #define CONFIG_MMC 1 490 491 #ifdef CONFIG_MMC 492 #define CONFIG_FSL_ESDHC 493 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 494 #define CONFIG_CMD_MMC 495 #define CONFIG_GENERIC_MMC 496 #define CONFIG_CMD_EXT2 497 #define CONFIG_CMD_FAT 498 #define CONFIG_DOS_PARTITION 499 #endif 500 501 /* 502 * Miscellaneous configurable options 503 */ 504 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 505 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 506 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 507 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 508 #if defined(CONFIG_CMD_KGDB) 509 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 510 #else 511 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 512 #endif 513 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 514 /* Print Buffer Size */ 515 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 516 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 517 /* Boot Argument Buffer Size */ 518 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 519 520 /* 521 * For booting Linux, the board info and command line data 522 * have to be in the first 16 MB of memory, since this is 523 * the maximum mapped by the Linux kernel during initialization. 524 */ 525 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) 526 /* Initial Memory map for Linux*/ 527 528 /* 529 * Internal Definitions 530 * 531 * Boot Flags 532 */ 533 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 534 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 535 536 #if defined(CONFIG_CMD_KGDB) 537 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 538 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 539 #endif 540 541 /* 542 * Environment Configuration 543 */ 544 #define CONFIG_HOSTNAME mpc8569mds 545 #define CONFIG_ROOTPATH /nfsroot 546 #define CONFIG_BOOTFILE your.uImage 547 548 #define CONFIG_SERVERIP 192.168.1.1 549 #define CONFIG_GATEWAYIP 192.168.1.1 550 #define CONFIG_NETMASK 255.255.255.0 551 552 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 553 554 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 555 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 556 557 #define CONFIG_BAUDRATE 115200 558 559 #define CONFIG_EXTRA_ENV_SETTINGS \ 560 "netdev=eth0\0" \ 561 "consoledev=ttyS0\0" \ 562 "ramdiskaddr=600000\0" \ 563 "ramdiskfile=your.ramdisk.u-boot\0" \ 564 "fdtaddr=400000\0" \ 565 "fdtfile=your.fdt.dtb\0" \ 566 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 567 "nfsroot=$serverip:$rootpath " \ 568 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 569 "console=$consoledev,$baudrate $othbootargs\0" \ 570 "ramargs=setenv bootargs root=/dev/ram rw " \ 571 "console=$consoledev,$baudrate $othbootargs\0" \ 572 573 #define CONFIG_NFSBOOTCOMMAND \ 574 "run nfsargs;" \ 575 "tftp $loadaddr $bootfile;" \ 576 "tftp $fdtaddr $fdtfile;" \ 577 "bootm $loadaddr - $fdtaddr" 578 579 #define CONFIG_RAMBOOTCOMMAND \ 580 "run ramargs;" \ 581 "tftp $ramdiskaddr $ramdiskfile;" \ 582 "tftp $loadaddr $bootfile;" \ 583 "bootm $loadaddr $ramdiskaddr" 584 585 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 586 587 #endif /* __CONFIG_H */ 588