1 /* 2 * Copyright 2004-2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8568mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 34 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 35 36 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 37 #define CONFIG_PCI1 1 /* PCI controller */ 38 #define CONFIG_PCIE1 1 /* PCIE controller */ 39 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 40 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 41 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 42 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 43 #define CONFIG_QE /* Enable QE */ 44 #define CONFIG_ENV_OVERWRITE 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 /* 48 * When initializing flash, if we cannot find the manufacturer ID, 49 * assume this is the AMD flash associated with the MDS board. 50 * This allows booting from a promjet. 51 */ 52 #define CONFIG_ASSUME_AMD_FLASH 53 54 #ifndef __ASSEMBLY__ 55 extern unsigned long get_clock_freq(void); 56 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 57 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 58 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_L2_CACHE /* toggle L2 cache */ 63 #define CONFIG_BTB /* toggle branch predition */ 64 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 65 66 /* 67 * Only possible on E500 Version 2 or newer cores. 68 */ 69 #define CONFIG_ENABLE_36BIT_PHYS 1 70 71 72 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 73 74 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 75 #define CONFIG_SYS_MEMTEST_END 0x00400000 76 77 /* 78 * Base addresses -- Note these are effective addresses where the 79 * actual resources get mapped (not physical addresses) 80 */ 81 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 82 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 83 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 84 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 85 86 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 87 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 88 89 /* DDR Setup */ 90 #define CONFIG_FSL_DDR2 91 #undef CONFIG_FSL_DDR_INTERACTIVE 92 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 93 #define CONFIG_DDR_SPD 94 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 96 97 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 98 99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 101 102 #define CONFIG_NUM_DDR_CONTROLLERS 1 103 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 104 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 105 106 /* I2C addresses of SPD EEPROMs */ 107 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 108 109 /* Make sure required options are set */ 110 #ifndef CONFIG_SPD_EEPROM 111 #error ("CONFIG_SPD_EEPROM is required") 112 #endif 113 114 #undef CONFIG_CLOCKS_IN_MHZ 115 116 /* 117 * Local Bus Definitions 118 */ 119 120 /* 121 * FLASH on the Local Bus 122 * Two banks, 8M each, using the CFI driver. 123 * Boot from BR0/OR0 bank at 0xff00_0000 124 * Alternate BR1/OR1 bank at 0xff80_0000 125 * 126 * BR0, BR1: 127 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 128 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 129 * Port Size = 16 bits = BRx[19:20] = 10 130 * Use GPCM = BRx[24:26] = 000 131 * Valid = BRx[31] = 1 132 * 133 * 0 4 8 12 16 20 24 28 134 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 135 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 136 * 137 * OR0, OR1: 138 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 139 * Reserved ORx[17:18] = 11, confusion here? 140 * CSNT = ORx[20] = 1 141 * ACS = half cycle delay = ORx[21:22] = 11 142 * SCY = 6 = ORx[24:27] = 0110 143 * TRLX = use relaxed timing = ORx[29] = 1 144 * EAD = use external address latch delay = OR[31] = 1 145 * 146 * 0 4 8 12 16 20 24 28 147 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 148 */ 149 #define CONFIG_SYS_BCSR_BASE 0xf8000000 150 151 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 152 153 /*Chip select 0 - Flash*/ 154 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 155 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 156 157 /*Chip slelect 1 - BCSR*/ 158 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 159 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 160 161 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 163 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 164 #undef CONFIG_SYS_FLASH_CHECKSUM 165 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 166 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 167 168 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 169 170 #define CONFIG_FLASH_CFI_DRIVER 171 #define CONFIG_SYS_FLASH_CFI 172 #define CONFIG_SYS_FLASH_EMPTY_INFO 173 174 175 /* 176 * SDRAM on the LocalBus 177 */ 178 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 179 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 180 181 182 /*Chip select 2 - SDRAM*/ 183 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 184 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 185 186 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 187 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 188 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 189 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 190 191 /* 192 * LSDMR masks 193 */ 194 #define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1)) 195 #define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 196 #define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 197 #define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 198 #define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 199 #define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 200 #define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 201 #define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23)) 202 #define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27)) 203 #define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31)) 204 205 #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 206 #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 207 #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 208 #define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 209 #define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 210 #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 211 #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 212 #define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 213 214 /* 215 * Common settings for all Local Bus SDRAM commands. 216 * At run time, either BSMA1516 (for CPU 1.1) 217 * or BSMA1617 (for CPU 1.0) (old) 218 * is OR'ed in too. 219 */ 220 #define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \ 221 | CONFIG_SYS_LBC_LSDMR_PRETOACT7 \ 222 | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \ 223 | CONFIG_SYS_LBC_LSDMR_BL8 \ 224 | CONFIG_SYS_LBC_LSDMR_WRC4 \ 225 | CONFIG_SYS_LBC_LSDMR_CL3 \ 226 | CONFIG_SYS_LBC_LSDMR_RFEN \ 227 ) 228 229 /* 230 * The bcsr registers are connected to CS3 on MDS. 231 * The new memory map places bcsr at 0xf8000000. 232 * 233 * For BR3, need: 234 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 235 * port-size = 8-bits = BR[19:20] = 01 236 * no parity checking = BR[21:22] = 00 237 * GPMC for MSEL = BR[24:26] = 000 238 * Valid = BR[31] = 1 239 * 240 * 0 4 8 12 16 20 24 28 241 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 242 * 243 * For OR3, need: 244 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 245 * disable buffer ctrl OR[19] = 0 246 * CSNT OR[20] = 1 247 * ACS OR[21:22] = 11 248 * XACS OR[23] = 1 249 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 250 * SETA OR[28] = 0 251 * TRLX OR[29] = 1 252 * EHTR OR[30] = 1 253 * EAD extra time OR[31] = 1 254 * 255 * 0 4 8 12 16 20 24 28 256 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 257 */ 258 #define CONFIG_SYS_BCSR (0xf8000000) 259 260 /*Chip slelect 4 - PIB*/ 261 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 262 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 263 264 /*Chip select 5 - PIB*/ 265 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 266 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 267 268 #define CONFIG_SYS_INIT_RAM_LOCK 1 269 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 270 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 271 272 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 273 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 274 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 275 276 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 277 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 278 279 /* Serial Port */ 280 #define CONFIG_CONS_INDEX 1 281 #undef CONFIG_SERIAL_SOFTWARE_FIFO 282 #define CONFIG_SYS_NS16550 283 #define CONFIG_SYS_NS16550_SERIAL 284 #define CONFIG_SYS_NS16550_REG_SIZE 1 285 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 286 287 #define CONFIG_SYS_BAUDRATE_TABLE \ 288 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 289 290 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 291 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 292 293 /* Use the HUSH parser*/ 294 #define CONFIG_SYS_HUSH_PARSER 295 #ifdef CONFIG_SYS_HUSH_PARSER 296 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 297 #endif 298 299 /* pass open firmware flat tree */ 300 #define CONFIG_OF_LIBFDT 1 301 #define CONFIG_OF_BOARD_SETUP 1 302 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 303 304 #define CONFIG_SYS_64BIT_VSPRINTF 1 305 #define CONFIG_SYS_64BIT_STRTOUL 1 306 307 /* 308 * I2C 309 */ 310 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 311 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 312 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 313 #define CONFIG_I2C_MULTI_BUS 314 #define CONFIG_I2C_CMD_TREE 315 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 316 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 317 #define CONFIG_SYS_I2C_SLAVE 0x7F 318 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 319 #define CONFIG_SYS_I2C_OFFSET 0x3000 320 #define CONFIG_SYS_I2C2_OFFSET 0x3100 321 322 /* 323 * General PCI 324 * Memory Addresses are mapped 1-1. I/O is mapped from 0 325 */ 326 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 327 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 328 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 329 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 330 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 331 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 332 333 #define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 334 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE 335 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 336 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 337 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 338 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 339 340 #define CONFIG_SYS_SRIO_MEM_BASE 0xc0000000 341 342 #ifdef CONFIG_QE 343 /* 344 * QE UEC ethernet configuration 345 */ 346 #define CONFIG_UEC_ETH 347 #ifndef CONFIG_TSEC_ENET 348 #define CONFIG_ETHPRIME "FSL UEC0" 349 #endif 350 #define CONFIG_PHY_MODE_NEED_CHANGE 351 #define CONFIG_eTSEC_MDIO_BUS 352 353 #ifdef CONFIG_eTSEC_MDIO_BUS 354 #define CONFIG_MIIM_ADDRESS 0xE0024520 355 #endif 356 357 #define CONFIG_UEC_ETH1 /* GETH1 */ 358 359 #ifdef CONFIG_UEC_ETH1 360 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 361 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 362 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 363 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 364 #define CONFIG_SYS_UEC1_PHY_ADDR 7 365 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID 366 #endif 367 368 #define CONFIG_UEC_ETH2 /* GETH2 */ 369 370 #ifdef CONFIG_UEC_ETH2 371 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 372 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 373 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 374 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 375 #define CONFIG_SYS_UEC2_PHY_ADDR 1 376 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID 377 #endif 378 #endif /* CONFIG_QE */ 379 380 #if defined(CONFIG_PCI) 381 382 #define CONFIG_NET_MULTI 383 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 384 385 #undef CONFIG_EEPRO100 386 #undef CONFIG_TULIP 387 388 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 389 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 390 391 #endif /* CONFIG_PCI */ 392 393 #ifndef CONFIG_NET_MULTI 394 #define CONFIG_NET_MULTI 1 395 #endif 396 397 #if defined(CONFIG_TSEC_ENET) 398 399 #define CONFIG_MII 1 /* MII PHY management */ 400 #define CONFIG_TSEC1 1 401 #define CONFIG_TSEC1_NAME "eTSEC0" 402 #define CONFIG_TSEC2 1 403 #define CONFIG_TSEC2_NAME "eTSEC1" 404 405 #define TSEC1_PHY_ADDR 2 406 #define TSEC2_PHY_ADDR 3 407 408 #define TSEC1_PHYIDX 0 409 #define TSEC2_PHYIDX 0 410 411 #define TSEC1_FLAGS TSEC_GIGABIT 412 #define TSEC2_FLAGS TSEC_GIGABIT 413 414 /* Options are: eTSEC[0-1] */ 415 #define CONFIG_ETHPRIME "eTSEC0" 416 417 #endif /* CONFIG_TSEC_ENET */ 418 419 /* 420 * Environment 421 */ 422 #define CONFIG_ENV_IS_IN_FLASH 1 423 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 424 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 425 #define CONFIG_ENV_SIZE 0x2000 426 427 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 428 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 429 430 431 /* 432 * BOOTP options 433 */ 434 #define CONFIG_BOOTP_BOOTFILESIZE 435 #define CONFIG_BOOTP_BOOTPATH 436 #define CONFIG_BOOTP_GATEWAY 437 #define CONFIG_BOOTP_HOSTNAME 438 439 440 /* 441 * Command line configuration. 442 */ 443 #include <config_cmd_default.h> 444 445 #define CONFIG_CMD_PING 446 #define CONFIG_CMD_I2C 447 #define CONFIG_CMD_MII 448 #define CONFIG_CMD_ELF 449 #define CONFIG_CMD_IRQ 450 #define CONFIG_CMD_SETEXPR 451 452 #if defined(CONFIG_PCI) 453 #define CONFIG_CMD_PCI 454 #endif 455 456 457 #undef CONFIG_WATCHDOG /* watchdog disabled */ 458 459 /* 460 * Miscellaneous configurable options 461 */ 462 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 463 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 464 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 465 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 466 #if defined(CONFIG_CMD_KGDB) 467 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 468 #else 469 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 470 #endif 471 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 472 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 473 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 474 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 475 476 /* 477 * For booting Linux, the board info and command line data 478 * have to be in the first 8 MB of memory, since this is 479 * the maximum mapped by the Linux kernel during initialization. 480 */ 481 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 482 483 /* 484 * Internal Definitions 485 * 486 * Boot Flags 487 */ 488 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 489 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 490 491 #if defined(CONFIG_CMD_KGDB) 492 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 493 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 494 #endif 495 496 /* 497 * Environment Configuration 498 */ 499 500 /* The mac addresses for all ethernet interface */ 501 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 502 #define CONFIG_HAS_ETH0 503 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 504 #define CONFIG_HAS_ETH1 505 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 506 #define CONFIG_HAS_ETH2 507 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 508 #define CONFIG_HAS_ETH3 509 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 510 #endif 511 512 #define CONFIG_IPADDR 192.168.1.253 513 514 #define CONFIG_HOSTNAME unknown 515 #define CONFIG_ROOTPATH /nfsroot 516 #define CONFIG_BOOTFILE your.uImage 517 518 #define CONFIG_SERVERIP 192.168.1.1 519 #define CONFIG_GATEWAYIP 192.168.1.1 520 #define CONFIG_NETMASK 255.255.255.0 521 522 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 523 524 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 525 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 526 527 #define CONFIG_BAUDRATE 115200 528 529 #define CONFIG_EXTRA_ENV_SETTINGS \ 530 "netdev=eth0\0" \ 531 "consoledev=ttyS0\0" \ 532 "ramdiskaddr=600000\0" \ 533 "ramdiskfile=your.ramdisk.u-boot\0" \ 534 "fdtaddr=400000\0" \ 535 "fdtfile=your.fdt.dtb\0" \ 536 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 537 "nfsroot=$serverip:$rootpath " \ 538 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 539 "console=$consoledev,$baudrate $othbootargs\0" \ 540 "ramargs=setenv bootargs root=/dev/ram rw " \ 541 "console=$consoledev,$baudrate $othbootargs\0" \ 542 543 544 #define CONFIG_NFSBOOTCOMMAND \ 545 "run nfsargs;" \ 546 "tftp $loadaddr $bootfile;" \ 547 "tftp $fdtaddr $fdtfile;" \ 548 "bootm $loadaddr - $fdtaddr" 549 550 551 #define CONFIG_RAMBOOTCOMMAND \ 552 "run ramargs;" \ 553 "tftp $ramdiskaddr $ramdiskfile;" \ 554 "tftp $loadaddr $bootfile;" \ 555 "bootm $loadaddr $ramdiskaddr" 556 557 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 558 559 #endif /* __CONFIG_H */ 560