1 /* 2 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8568mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_BOOKE 1 /* BOOKE */ 15 #define CONFIG_E500 1 /* BOOKE e500 family */ 16 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 17 18 #define CONFIG_SYS_TEXT_BASE 0xfff80000 19 20 #define CONFIG_SYS_SRIO 21 #define CONFIG_SRIO1 /* SRIO port 1 */ 22 23 #define CONFIG_PCI1 1 /* PCI controller */ 24 #define CONFIG_PCIE1 1 /* PCIE controller */ 25 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 26 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 27 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 28 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 29 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 30 #define CONFIG_QE /* Enable QE */ 31 #define CONFIG_ENV_OVERWRITE 32 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 33 34 #ifndef __ASSEMBLY__ 35 extern unsigned long get_clock_freq(void); 36 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 37 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 38 39 /* 40 * These can be toggled for performance analysis, otherwise use default. 41 */ 42 #define CONFIG_L2_CACHE /* toggle L2 cache */ 43 #define CONFIG_BTB /* toggle branch predition */ 44 45 /* 46 * Only possible on E500 Version 2 or newer cores. 47 */ 48 #define CONFIG_ENABLE_36BIT_PHYS 1 49 50 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 51 52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 53 #define CONFIG_SYS_MEMTEST_END 0x00400000 54 55 #define CONFIG_SYS_CCSRBAR 0xe0000000 56 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 57 58 /* DDR Setup */ 59 #define CONFIG_SYS_FSL_DDR2 60 #undef CONFIG_FSL_DDR_INTERACTIVE 61 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 62 #define CONFIG_DDR_SPD 63 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 64 65 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 66 67 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 68 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 69 70 #define CONFIG_NUM_DDR_CONTROLLERS 1 71 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 72 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 73 74 /* I2C addresses of SPD EEPROMs */ 75 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 76 77 /* Make sure required options are set */ 78 #ifndef CONFIG_SPD_EEPROM 79 #error ("CONFIG_SPD_EEPROM is required") 80 #endif 81 82 #undef CONFIG_CLOCKS_IN_MHZ 83 84 /* 85 * Local Bus Definitions 86 */ 87 88 /* 89 * FLASH on the Local Bus 90 * Two banks, 8M each, using the CFI driver. 91 * Boot from BR0/OR0 bank at 0xff00_0000 92 * Alternate BR1/OR1 bank at 0xff80_0000 93 * 94 * BR0, BR1: 95 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 96 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 97 * Port Size = 16 bits = BRx[19:20] = 10 98 * Use GPCM = BRx[24:26] = 000 99 * Valid = BRx[31] = 1 100 * 101 * 0 4 8 12 16 20 24 28 102 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 103 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 104 * 105 * OR0, OR1: 106 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 107 * Reserved ORx[17:18] = 11, confusion here? 108 * CSNT = ORx[20] = 1 109 * ACS = half cycle delay = ORx[21:22] = 11 110 * SCY = 6 = ORx[24:27] = 0110 111 * TRLX = use relaxed timing = ORx[29] = 1 112 * EAD = use external address latch delay = OR[31] = 1 113 * 114 * 0 4 8 12 16 20 24 28 115 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 116 */ 117 #define CONFIG_SYS_BCSR_BASE 0xf8000000 118 119 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 120 121 /*Chip select 0 - Flash*/ 122 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 123 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 124 125 /*Chip slelect 1 - BCSR*/ 126 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 127 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 128 129 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 130 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 131 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 132 #undef CONFIG_SYS_FLASH_CHECKSUM 133 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 134 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 135 136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 137 138 #define CONFIG_FLASH_CFI_DRIVER 139 #define CONFIG_SYS_FLASH_CFI 140 #define CONFIG_SYS_FLASH_EMPTY_INFO 141 142 /* 143 * SDRAM on the LocalBus 144 */ 145 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 146 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 147 148 /*Chip select 2 - SDRAM*/ 149 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 150 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 151 152 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 153 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 154 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 155 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 156 157 /* 158 * Common settings for all Local Bus SDRAM commands. 159 * At run time, either BSMA1516 (for CPU 1.1) 160 * or BSMA1617 (for CPU 1.0) (old) 161 * is OR'ed in too. 162 */ 163 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 164 | LSDMR_PRETOACT7 \ 165 | LSDMR_ACTTORW7 \ 166 | LSDMR_BL8 \ 167 | LSDMR_WRC4 \ 168 | LSDMR_CL3 \ 169 | LSDMR_RFEN \ 170 ) 171 172 /* 173 * The bcsr registers are connected to CS3 on MDS. 174 * The new memory map places bcsr at 0xf8000000. 175 * 176 * For BR3, need: 177 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 178 * port-size = 8-bits = BR[19:20] = 01 179 * no parity checking = BR[21:22] = 00 180 * GPMC for MSEL = BR[24:26] = 000 181 * Valid = BR[31] = 1 182 * 183 * 0 4 8 12 16 20 24 28 184 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 185 * 186 * For OR3, need: 187 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 188 * disable buffer ctrl OR[19] = 0 189 * CSNT OR[20] = 1 190 * ACS OR[21:22] = 11 191 * XACS OR[23] = 1 192 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 193 * SETA OR[28] = 0 194 * TRLX OR[29] = 1 195 * EHTR OR[30] = 1 196 * EAD extra time OR[31] = 1 197 * 198 * 0 4 8 12 16 20 24 28 199 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 200 */ 201 #define CONFIG_SYS_BCSR (0xf8000000) 202 203 /*Chip slelect 4 - PIB*/ 204 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 205 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 206 207 /*Chip select 5 - PIB*/ 208 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 209 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 210 211 #define CONFIG_SYS_INIT_RAM_LOCK 1 212 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 213 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 214 215 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 216 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 217 218 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 219 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 220 221 /* Serial Port */ 222 #define CONFIG_CONS_INDEX 1 223 #define CONFIG_SYS_NS16550_SERIAL 224 #define CONFIG_SYS_NS16550_REG_SIZE 1 225 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 226 227 #define CONFIG_SYS_BAUDRATE_TABLE \ 228 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 229 230 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 231 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 232 233 /* 234 * I2C 235 */ 236 #define CONFIG_SYS_I2C 237 #define CONFIG_SYS_I2C_FSL 238 #define CONFIG_SYS_FSL_I2C_SPEED 400000 239 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 240 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 241 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 242 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 243 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 244 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 245 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 246 247 /* 248 * General PCI 249 * Memory Addresses are mapped 1-1. I/O is mapped from 0 250 */ 251 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 252 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 253 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 254 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 255 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 256 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 257 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 258 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 259 260 #define CONFIG_SYS_PCIE1_NAME "Slot" 261 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 262 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 263 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 264 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 265 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 266 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 267 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 268 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 269 270 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 271 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 272 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 273 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 274 275 #ifdef CONFIG_QE 276 /* 277 * QE UEC ethernet configuration 278 */ 279 #define CONFIG_UEC_ETH 280 #ifndef CONFIG_TSEC_ENET 281 #define CONFIG_ETHPRIME "UEC0" 282 #endif 283 #define CONFIG_PHY_MODE_NEED_CHANGE 284 #define CONFIG_eTSEC_MDIO_BUS 285 286 #ifdef CONFIG_eTSEC_MDIO_BUS 287 #define CONFIG_MIIM_ADDRESS 0xE0024520 288 #endif 289 290 #define CONFIG_UEC_ETH1 /* GETH1 */ 291 292 #ifdef CONFIG_UEC_ETH1 293 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 294 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 295 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 296 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 297 #define CONFIG_SYS_UEC1_PHY_ADDR 7 298 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 299 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 300 #endif 301 302 #define CONFIG_UEC_ETH2 /* GETH2 */ 303 304 #ifdef CONFIG_UEC_ETH2 305 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 306 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 307 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 308 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 309 #define CONFIG_SYS_UEC2_PHY_ADDR 1 310 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 311 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 312 #endif 313 #endif /* CONFIG_QE */ 314 315 #if defined(CONFIG_PCI) 316 #undef CONFIG_EEPRO100 317 #undef CONFIG_TULIP 318 319 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 320 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 321 322 #endif /* CONFIG_PCI */ 323 324 #if defined(CONFIG_TSEC_ENET) 325 326 #define CONFIG_MII 1 /* MII PHY management */ 327 #define CONFIG_TSEC1 1 328 #define CONFIG_TSEC1_NAME "eTSEC0" 329 #define CONFIG_TSEC2 1 330 #define CONFIG_TSEC2_NAME "eTSEC1" 331 332 #define TSEC1_PHY_ADDR 2 333 #define TSEC2_PHY_ADDR 3 334 335 #define TSEC1_PHYIDX 0 336 #define TSEC2_PHYIDX 0 337 338 #define TSEC1_FLAGS TSEC_GIGABIT 339 #define TSEC2_FLAGS TSEC_GIGABIT 340 341 /* Options are: eTSEC[0-1] */ 342 #define CONFIG_ETHPRIME "eTSEC0" 343 344 #endif /* CONFIG_TSEC_ENET */ 345 346 /* 347 * Environment 348 */ 349 #define CONFIG_ENV_IS_IN_FLASH 1 350 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 351 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 352 #define CONFIG_ENV_SIZE 0x2000 353 354 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 355 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 356 357 /* 358 * BOOTP options 359 */ 360 #define CONFIG_BOOTP_BOOTFILESIZE 361 #define CONFIG_BOOTP_BOOTPATH 362 #define CONFIG_BOOTP_GATEWAY 363 #define CONFIG_BOOTP_HOSTNAME 364 365 /* 366 * Command line configuration. 367 */ 368 #define CONFIG_CMD_IRQ 369 #define CONFIG_CMD_REGINFO 370 371 #if defined(CONFIG_PCI) 372 #define CONFIG_CMD_PCI 373 #endif 374 375 #undef CONFIG_WATCHDOG /* watchdog disabled */ 376 377 /* 378 * Miscellaneous configurable options 379 */ 380 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 381 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 382 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 383 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 384 #if defined(CONFIG_CMD_KGDB) 385 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 386 #else 387 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 388 #endif 389 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 390 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 391 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 392 393 /* 394 * For booting Linux, the board info and command line data 395 * have to be in the first 64 MB of memory, since this is 396 * the maximum mapped by the Linux kernel during initialization. 397 */ 398 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 399 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 400 401 #if defined(CONFIG_CMD_KGDB) 402 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 403 #endif 404 405 /* 406 * Environment Configuration 407 */ 408 409 /* The mac addresses for all ethernet interface */ 410 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 411 #define CONFIG_HAS_ETH0 412 #define CONFIG_HAS_ETH1 413 #define CONFIG_HAS_ETH2 414 #define CONFIG_HAS_ETH3 415 #endif 416 417 #define CONFIG_IPADDR 192.168.1.253 418 419 #define CONFIG_HOSTNAME unknown 420 #define CONFIG_ROOTPATH "/nfsroot" 421 #define CONFIG_BOOTFILE "your.uImage" 422 423 #define CONFIG_SERVERIP 192.168.1.1 424 #define CONFIG_GATEWAYIP 192.168.1.1 425 #define CONFIG_NETMASK 255.255.255.0 426 427 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 428 429 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 430 431 #define CONFIG_BAUDRATE 115200 432 433 #define CONFIG_EXTRA_ENV_SETTINGS \ 434 "netdev=eth0\0" \ 435 "consoledev=ttyS0\0" \ 436 "ramdiskaddr=600000\0" \ 437 "ramdiskfile=your.ramdisk.u-boot\0" \ 438 "fdtaddr=400000\0" \ 439 "fdtfile=your.fdt.dtb\0" \ 440 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 441 "nfsroot=$serverip:$rootpath " \ 442 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 443 "console=$consoledev,$baudrate $othbootargs\0" \ 444 "ramargs=setenv bootargs root=/dev/ram rw " \ 445 "console=$consoledev,$baudrate $othbootargs\0" \ 446 447 #define CONFIG_NFSBOOTCOMMAND \ 448 "run nfsargs;" \ 449 "tftp $loadaddr $bootfile;" \ 450 "tftp $fdtaddr $fdtfile;" \ 451 "bootm $loadaddr - $fdtaddr" 452 453 #define CONFIG_RAMBOOTCOMMAND \ 454 "run ramargs;" \ 455 "tftp $ramdiskaddr $ramdiskfile;" \ 456 "tftp $loadaddr $bootfile;" \ 457 "bootm $loadaddr $ramdiskaddr" 458 459 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 460 461 #endif /* __CONFIG_H */ 462