1 /* 2 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8568mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_TEXT_BASE 0xfff80000 14 15 #define CONFIG_SYS_SRIO 16 #define CONFIG_SRIO1 /* SRIO port 1 */ 17 18 #define CONFIG_PCI1 1 /* PCI controller */ 19 #define CONFIG_PCIE1 1 /* PCIE controller */ 20 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 21 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 22 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 23 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 24 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 25 #define CONFIG_QE /* Enable QE */ 26 #define CONFIG_ENV_OVERWRITE 27 28 #ifndef __ASSEMBLY__ 29 extern unsigned long get_clock_freq(void); 30 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 31 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 32 33 /* 34 * These can be toggled for performance analysis, otherwise use default. 35 */ 36 #define CONFIG_L2_CACHE /* toggle L2 cache */ 37 #define CONFIG_BTB /* toggle branch predition */ 38 39 /* 40 * Only possible on E500 Version 2 or newer cores. 41 */ 42 #define CONFIG_ENABLE_36BIT_PHYS 1 43 44 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 45 46 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 47 #define CONFIG_SYS_MEMTEST_END 0x00400000 48 49 #define CONFIG_SYS_CCSRBAR 0xe0000000 50 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 51 52 /* DDR Setup */ 53 #define CONFIG_SYS_FSL_DDR2 54 #undef CONFIG_FSL_DDR_INTERACTIVE 55 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 56 #define CONFIG_DDR_SPD 57 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 58 59 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 60 61 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 62 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 63 64 #define CONFIG_NUM_DDR_CONTROLLERS 1 65 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 66 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 67 68 /* I2C addresses of SPD EEPROMs */ 69 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 70 71 /* Make sure required options are set */ 72 #ifndef CONFIG_SPD_EEPROM 73 #error ("CONFIG_SPD_EEPROM is required") 74 #endif 75 76 #undef CONFIG_CLOCKS_IN_MHZ 77 78 /* 79 * Local Bus Definitions 80 */ 81 82 /* 83 * FLASH on the Local Bus 84 * Two banks, 8M each, using the CFI driver. 85 * Boot from BR0/OR0 bank at 0xff00_0000 86 * Alternate BR1/OR1 bank at 0xff80_0000 87 * 88 * BR0, BR1: 89 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 90 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 91 * Port Size = 16 bits = BRx[19:20] = 10 92 * Use GPCM = BRx[24:26] = 000 93 * Valid = BRx[31] = 1 94 * 95 * 0 4 8 12 16 20 24 28 96 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 97 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 98 * 99 * OR0, OR1: 100 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 101 * Reserved ORx[17:18] = 11, confusion here? 102 * CSNT = ORx[20] = 1 103 * ACS = half cycle delay = ORx[21:22] = 11 104 * SCY = 6 = ORx[24:27] = 0110 105 * TRLX = use relaxed timing = ORx[29] = 1 106 * EAD = use external address latch delay = OR[31] = 1 107 * 108 * 0 4 8 12 16 20 24 28 109 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 110 */ 111 #define CONFIG_SYS_BCSR_BASE 0xf8000000 112 113 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 114 115 /*Chip select 0 - Flash*/ 116 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 117 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 118 119 /*Chip slelect 1 - BCSR*/ 120 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 121 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 122 123 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 124 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 125 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 126 #undef CONFIG_SYS_FLASH_CHECKSUM 127 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 128 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 129 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 131 132 #define CONFIG_FLASH_CFI_DRIVER 133 #define CONFIG_SYS_FLASH_CFI 134 #define CONFIG_SYS_FLASH_EMPTY_INFO 135 136 /* 137 * SDRAM on the LocalBus 138 */ 139 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 140 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 141 142 /*Chip select 2 - SDRAM*/ 143 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 144 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 145 146 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 147 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 148 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 149 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 150 151 /* 152 * Common settings for all Local Bus SDRAM commands. 153 * At run time, either BSMA1516 (for CPU 1.1) 154 * or BSMA1617 (for CPU 1.0) (old) 155 * is OR'ed in too. 156 */ 157 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 158 | LSDMR_PRETOACT7 \ 159 | LSDMR_ACTTORW7 \ 160 | LSDMR_BL8 \ 161 | LSDMR_WRC4 \ 162 | LSDMR_CL3 \ 163 | LSDMR_RFEN \ 164 ) 165 166 /* 167 * The bcsr registers are connected to CS3 on MDS. 168 * The new memory map places bcsr at 0xf8000000. 169 * 170 * For BR3, need: 171 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 172 * port-size = 8-bits = BR[19:20] = 01 173 * no parity checking = BR[21:22] = 00 174 * GPMC for MSEL = BR[24:26] = 000 175 * Valid = BR[31] = 1 176 * 177 * 0 4 8 12 16 20 24 28 178 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 179 * 180 * For OR3, need: 181 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 182 * disable buffer ctrl OR[19] = 0 183 * CSNT OR[20] = 1 184 * ACS OR[21:22] = 11 185 * XACS OR[23] = 1 186 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 187 * SETA OR[28] = 0 188 * TRLX OR[29] = 1 189 * EHTR OR[30] = 1 190 * EAD extra time OR[31] = 1 191 * 192 * 0 4 8 12 16 20 24 28 193 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 194 */ 195 #define CONFIG_SYS_BCSR (0xf8000000) 196 197 /*Chip slelect 4 - PIB*/ 198 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 199 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 200 201 /*Chip select 5 - PIB*/ 202 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 203 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 204 205 #define CONFIG_SYS_INIT_RAM_LOCK 1 206 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 207 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 208 209 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 210 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 211 212 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 213 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 214 215 /* Serial Port */ 216 #define CONFIG_CONS_INDEX 1 217 #define CONFIG_SYS_NS16550_SERIAL 218 #define CONFIG_SYS_NS16550_REG_SIZE 1 219 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 220 221 #define CONFIG_SYS_BAUDRATE_TABLE \ 222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 223 224 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 225 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 226 227 /* 228 * I2C 229 */ 230 #define CONFIG_SYS_I2C 231 #define CONFIG_SYS_I2C_FSL 232 #define CONFIG_SYS_FSL_I2C_SPEED 400000 233 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 234 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 235 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 236 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 237 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 238 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 239 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 240 241 /* 242 * General PCI 243 * Memory Addresses are mapped 1-1. I/O is mapped from 0 244 */ 245 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 246 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 247 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 248 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 249 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 250 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 251 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 252 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 253 254 #define CONFIG_SYS_PCIE1_NAME "Slot" 255 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 256 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 257 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 258 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 259 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 260 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 261 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 262 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 263 264 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 265 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 266 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 267 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 268 269 #ifdef CONFIG_QE 270 /* 271 * QE UEC ethernet configuration 272 */ 273 #define CONFIG_UEC_ETH 274 #ifndef CONFIG_TSEC_ENET 275 #define CONFIG_ETHPRIME "UEC0" 276 #endif 277 #define CONFIG_PHY_MODE_NEED_CHANGE 278 #define CONFIG_eTSEC_MDIO_BUS 279 280 #ifdef CONFIG_eTSEC_MDIO_BUS 281 #define CONFIG_MIIM_ADDRESS 0xE0024520 282 #endif 283 284 #define CONFIG_UEC_ETH1 /* GETH1 */ 285 286 #ifdef CONFIG_UEC_ETH1 287 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 288 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 289 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 290 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 291 #define CONFIG_SYS_UEC1_PHY_ADDR 7 292 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 293 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 294 #endif 295 296 #define CONFIG_UEC_ETH2 /* GETH2 */ 297 298 #ifdef CONFIG_UEC_ETH2 299 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 300 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 301 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 302 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 303 #define CONFIG_SYS_UEC2_PHY_ADDR 1 304 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 305 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 306 #endif 307 #endif /* CONFIG_QE */ 308 309 #if defined(CONFIG_PCI) 310 #undef CONFIG_EEPRO100 311 #undef CONFIG_TULIP 312 313 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 314 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 315 316 #endif /* CONFIG_PCI */ 317 318 #if defined(CONFIG_TSEC_ENET) 319 320 #define CONFIG_MII 1 /* MII PHY management */ 321 #define CONFIG_TSEC1 1 322 #define CONFIG_TSEC1_NAME "eTSEC0" 323 #define CONFIG_TSEC2 1 324 #define CONFIG_TSEC2_NAME "eTSEC1" 325 326 #define TSEC1_PHY_ADDR 2 327 #define TSEC2_PHY_ADDR 3 328 329 #define TSEC1_PHYIDX 0 330 #define TSEC2_PHYIDX 0 331 332 #define TSEC1_FLAGS TSEC_GIGABIT 333 #define TSEC2_FLAGS TSEC_GIGABIT 334 335 /* Options are: eTSEC[0-1] */ 336 #define CONFIG_ETHPRIME "eTSEC0" 337 338 #endif /* CONFIG_TSEC_ENET */ 339 340 /* 341 * Environment 342 */ 343 #define CONFIG_ENV_IS_IN_FLASH 1 344 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 345 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 346 #define CONFIG_ENV_SIZE 0x2000 347 348 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 349 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 350 351 /* 352 * BOOTP options 353 */ 354 #define CONFIG_BOOTP_BOOTFILESIZE 355 #define CONFIG_BOOTP_BOOTPATH 356 #define CONFIG_BOOTP_GATEWAY 357 #define CONFIG_BOOTP_HOSTNAME 358 359 /* 360 * Command line configuration. 361 */ 362 #define CONFIG_CMD_IRQ 363 #define CONFIG_CMD_REGINFO 364 365 #if defined(CONFIG_PCI) 366 #define CONFIG_CMD_PCI 367 #endif 368 369 #undef CONFIG_WATCHDOG /* watchdog disabled */ 370 371 /* 372 * Miscellaneous configurable options 373 */ 374 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 375 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 376 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 377 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 378 #if defined(CONFIG_CMD_KGDB) 379 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 380 #else 381 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 382 #endif 383 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 384 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 385 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 386 387 /* 388 * For booting Linux, the board info and command line data 389 * have to be in the first 64 MB of memory, since this is 390 * the maximum mapped by the Linux kernel during initialization. 391 */ 392 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 393 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 394 395 #if defined(CONFIG_CMD_KGDB) 396 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 397 #endif 398 399 /* 400 * Environment Configuration 401 */ 402 403 /* The mac addresses for all ethernet interface */ 404 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 405 #define CONFIG_HAS_ETH0 406 #define CONFIG_HAS_ETH1 407 #define CONFIG_HAS_ETH2 408 #define CONFIG_HAS_ETH3 409 #endif 410 411 #define CONFIG_IPADDR 192.168.1.253 412 413 #define CONFIG_HOSTNAME unknown 414 #define CONFIG_ROOTPATH "/nfsroot" 415 #define CONFIG_BOOTFILE "your.uImage" 416 417 #define CONFIG_SERVERIP 192.168.1.1 418 #define CONFIG_GATEWAYIP 192.168.1.1 419 #define CONFIG_NETMASK 255.255.255.0 420 421 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 422 423 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 424 425 #define CONFIG_BAUDRATE 115200 426 427 #define CONFIG_EXTRA_ENV_SETTINGS \ 428 "netdev=eth0\0" \ 429 "consoledev=ttyS0\0" \ 430 "ramdiskaddr=600000\0" \ 431 "ramdiskfile=your.ramdisk.u-boot\0" \ 432 "fdtaddr=400000\0" \ 433 "fdtfile=your.fdt.dtb\0" \ 434 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 435 "nfsroot=$serverip:$rootpath " \ 436 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 437 "console=$consoledev,$baudrate $othbootargs\0" \ 438 "ramargs=setenv bootargs root=/dev/ram rw " \ 439 "console=$consoledev,$baudrate $othbootargs\0" \ 440 441 #define CONFIG_NFSBOOTCOMMAND \ 442 "run nfsargs;" \ 443 "tftp $loadaddr $bootfile;" \ 444 "tftp $fdtaddr $fdtfile;" \ 445 "bootm $loadaddr - $fdtaddr" 446 447 #define CONFIG_RAMBOOTCOMMAND \ 448 "run ramargs;" \ 449 "tftp $ramdiskaddr $ramdiskfile;" \ 450 "tftp $loadaddr $bootfile;" \ 451 "bootm $loadaddr $ramdiskaddr" 452 453 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 454 455 #endif /* __CONFIG_H */ 456