1 /* 2 * Copyright 2004-2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8568mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 34 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 35 36 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 37 #define CONFIG_PCI1 1 /* PCI controller */ 38 #define CONFIG_PCIE1 1 /* PCIE controller */ 39 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 40 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 41 #define CONFIG_QE /* Enable QE */ 42 #define CONFIG_ENV_OVERWRITE 43 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 44 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 45 /*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ 46 47 /*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ 48 /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ 49 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 50 51 52 /* 53 * When initializing flash, if we cannot find the manufacturer ID, 54 * assume this is the AMD flash associated with the MDS board. 55 * This allows booting from a promjet. 56 */ 57 #define CONFIG_ASSUME_AMD_FLASH 58 59 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 60 61 #ifndef __ASSEMBLY__ 62 extern unsigned long get_clock_freq(void); 63 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 64 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 72 73 /* 74 * Only possible on E500 Version 2 or newer cores. 75 */ 76 #define CONFIG_ENABLE_36BIT_PHYS 1 77 78 79 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 80 81 #undef CFG_DRAM_TEST /* memory test, takes time */ 82 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 83 #define CFG_MEMTEST_END 0x00400000 84 85 /* 86 * Base addresses -- Note these are effective addresses where the 87 * actual resources get mapped (not physical addresses) 88 */ 89 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 90 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 91 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 92 93 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 94 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 95 96 /* 97 * DDR Setup 98 */ 99 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 100 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 101 102 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 103 104 /* 105 * Make sure required options are set 106 */ 107 #ifndef CONFIG_SPD_EEPROM 108 #error ("CONFIG_SPD_EEPROM is required") 109 #endif 110 111 #undef CONFIG_CLOCKS_IN_MHZ 112 113 114 /* 115 * Local Bus Definitions 116 */ 117 118 /* 119 * FLASH on the Local Bus 120 * Two banks, 8M each, using the CFI driver. 121 * Boot from BR0/OR0 bank at 0xff00_0000 122 * Alternate BR1/OR1 bank at 0xff80_0000 123 * 124 * BR0, BR1: 125 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 126 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 127 * Port Size = 16 bits = BRx[19:20] = 10 128 * Use GPCM = BRx[24:26] = 000 129 * Valid = BRx[31] = 1 130 * 131 * 0 4 8 12 16 20 24 28 132 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 133 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 134 * 135 * OR0, OR1: 136 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 137 * Reserved ORx[17:18] = 11, confusion here? 138 * CSNT = ORx[20] = 1 139 * ACS = half cycle delay = ORx[21:22] = 11 140 * SCY = 6 = ORx[24:27] = 0110 141 * TRLX = use relaxed timing = ORx[29] = 1 142 * EAD = use external address latch delay = OR[31] = 1 143 * 144 * 0 4 8 12 16 20 24 28 145 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 146 */ 147 #define CFG_BCSR_BASE 0xf8000000 148 149 #define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 150 151 /*Chip select 0 - Flash*/ 152 #define CFG_BR0_PRELIM 0xfe001001 153 #define CFG_OR0_PRELIM 0xfe006ff7 154 155 /*Chip slelect 1 - BCSR*/ 156 #define CFG_BR1_PRELIM 0xf8000801 157 #define CFG_OR1_PRELIM 0xffffe9f7 158 159 /*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */ 160 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 161 #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ 162 #undef CFG_FLASH_CHECKSUM 163 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 164 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 165 166 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 167 168 #define CFG_FLASH_CFI_DRIVER 169 #define CFG_FLASH_CFI 170 #define CFG_FLASH_EMPTY_INFO 171 172 173 /* 174 * SDRAM on the LocalBus 175 */ 176 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 177 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 178 179 180 /*Chip select 2 - SDRAM*/ 181 #define CFG_BR2_PRELIM 0xf0001861 182 #define CFG_OR2_PRELIM 0xfc006901 183 184 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 185 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 186 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 187 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 188 189 /* 190 * LSDMR masks 191 */ 192 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 193 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 194 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 195 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 196 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 197 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 198 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 199 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 200 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 201 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 202 203 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 204 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 205 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 206 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 207 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 208 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 209 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 210 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 211 212 /* 213 * Common settings for all Local Bus SDRAM commands. 214 * At run time, either BSMA1516 (for CPU 1.1) 215 * or BSMA1617 (for CPU 1.0) (old) 216 * is OR'ed in too. 217 */ 218 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 219 | CFG_LBC_LSDMR_PRETOACT7 \ 220 | CFG_LBC_LSDMR_ACTTORW7 \ 221 | CFG_LBC_LSDMR_BL8 \ 222 | CFG_LBC_LSDMR_WRC4 \ 223 | CFG_LBC_LSDMR_CL3 \ 224 | CFG_LBC_LSDMR_RFEN \ 225 ) 226 227 /* 228 * The bcsr registers are connected to CS3 on MDS. 229 * The new memory map places bcsr at 0xf8000000. 230 * 231 * For BR3, need: 232 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 233 * port-size = 8-bits = BR[19:20] = 01 234 * no parity checking = BR[21:22] = 00 235 * GPMC for MSEL = BR[24:26] = 000 236 * Valid = BR[31] = 1 237 * 238 * 0 4 8 12 16 20 24 28 239 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 240 * 241 * For OR3, need: 242 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 243 * disable buffer ctrl OR[19] = 0 244 * CSNT OR[20] = 1 245 * ACS OR[21:22] = 11 246 * XACS OR[23] = 1 247 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 248 * SETA OR[28] = 0 249 * TRLX OR[29] = 1 250 * EHTR OR[30] = 1 251 * EAD extra time OR[31] = 1 252 * 253 * 0 4 8 12 16 20 24 28 254 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 255 */ 256 #define CFG_BCSR (0xf8000000) 257 258 /*Chip slelect 4 - PIB*/ 259 #define CFG_BR4_PRELIM 0xf8008801 260 #define CFG_OR4_PRELIM 0xffffe9f7 261 262 /*Chip select 5 - PIB*/ 263 #define CFG_BR5_PRELIM 0xf8010801 264 #define CFG_OR5_PRELIM 0xffff69f7 265 266 #define CONFIG_L1_INIT_RAM 267 #define CFG_INIT_RAM_LOCK 1 268 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 269 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 270 271 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 272 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 273 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 274 275 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 276 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 277 278 /* Serial Port */ 279 #define CONFIG_CONS_INDEX 1 280 #undef CONFIG_SERIAL_SOFTWARE_FIFO 281 #define CFG_NS16550 282 #define CFG_NS16550_SERIAL 283 #define CFG_NS16550_REG_SIZE 1 284 #define CFG_NS16550_CLK get_bus_freq(0) 285 286 #define CFG_BAUDRATE_TABLE \ 287 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 288 289 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 290 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 291 292 /* Use the HUSH parser*/ 293 #define CFG_HUSH_PARSER 294 #ifdef CFG_HUSH_PARSER 295 #define CFG_PROMPT_HUSH_PS2 "> " 296 #endif 297 298 /* pass open firmware flat tree */ 299 #define CONFIG_OF_FLAT_TREE 1 300 #define CONFIG_OF_BOARD_SETUP 1 301 302 #define OF_CPU "PowerPC,8568@0" 303 #define OF_SOC "soc8568@e0000000" 304 #define OF_QE "qe@e0080000" 305 #define OF_TBCLK (bd->bi_busfreq / 8) 306 #define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500" 307 308 /* 309 * I2C 310 */ 311 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 312 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 313 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 314 #define CONFIG_I2C_MULTI_BUS 315 #define CONFIG_I2C_CMD_TREE 316 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 317 #define CFG_I2C_EEPROM_ADDR 0x52 318 #define CFG_I2C_SLAVE 0x7F 319 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 320 #define CFG_I2C_OFFSET 0x3000 321 #define CFG_I2C2_OFFSET 0x3100 322 323 /* 324 * General PCI 325 * Memory Addresses are mapped 1-1. I/O is mapped from 0 326 */ 327 #define CFG_PCI1_MEM_BASE 0x80000000 328 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 329 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 330 #define CFG_PCI1_IO_BASE 0x00000000 331 #define CFG_PCI1_IO_PHYS 0xe2000000 332 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ 333 334 #define CFG_PCIE1_MEM_BASE 0xa0000000 335 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 336 #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 337 #define CFG_PCIE1_IO_BASE 0x00000000 338 #define CFG_PCIE1_IO_PHYS 0xe2800000 339 #define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */ 340 341 #define CFG_SRIO_MEM_BASE 0xc0000000 342 343 #ifdef CONFIG_QE 344 /* 345 * QE UEC ethernet configuration 346 */ 347 #define CONFIG_UEC_ETH 348 #ifndef CONFIG_TSEC_ENET 349 #define CONFIG_ETHPRIME "FSL UEC0" 350 #endif 351 #define CONFIG_PHY_MODE_NEED_CHANGE 352 #define CONFIG_eTSEC_MDIO_BUS 353 354 #ifdef CONFIG_eTSEC_MDIO_BUS 355 #define CONFIG_MIIM_ADDRESS 0xE0024520 356 #endif 357 358 #define CONFIG_UEC_ETH1 /* GETH1 */ 359 360 #ifdef CONFIG_UEC_ETH1 361 #define CFG_UEC1_UCC_NUM 0 /* UCC1 */ 362 #define CFG_UEC1_RX_CLK QE_CLK_NONE 363 #define CFG_UEC1_TX_CLK QE_CLK16 364 #define CFG_UEC1_ETH_TYPE GIGA_ETH 365 #define CFG_UEC1_PHY_ADDR 7 366 #define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII 367 #endif 368 369 #define CONFIG_UEC_ETH2 /* GETH2 */ 370 371 #ifdef CONFIG_UEC_ETH2 372 #define CFG_UEC2_UCC_NUM 1 /* UCC2 */ 373 #define CFG_UEC2_RX_CLK QE_CLK_NONE 374 #define CFG_UEC2_TX_CLK QE_CLK16 375 #define CFG_UEC2_ETH_TYPE GIGA_ETH 376 #define CFG_UEC2_PHY_ADDR 1 377 #define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII 378 #endif 379 #endif /* CONFIG_QE */ 380 381 #if defined(CONFIG_PCI) 382 383 #define CONFIG_NET_MULTI 384 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 385 386 #undef CONFIG_EEPRO100 387 #undef CONFIG_TULIP 388 389 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 390 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 391 392 /* PCI view of System Memory */ 393 #define CFG_PCI_MEMORY_BUS 0x00000000 394 #define CFG_PCI_MEMORY_PHYS 0x00000000 395 #define CFG_PCI_MEMORY_SIZE 0x80000000 396 397 #endif /* CONFIG_PCI */ 398 399 #ifndef CONFIG_NET_MULTI 400 #define CONFIG_NET_MULTI 1 401 #endif 402 403 #if defined(CONFIG_TSEC_ENET) 404 405 #define CONFIG_MII 1 /* MII PHY management */ 406 #define CONFIG_TSEC1 1 407 #define CONFIG_TSEC1_NAME "eTSEC0" 408 #define CONFIG_TSEC2 1 409 #define CONFIG_TSEC2_NAME "eTSEC1" 410 411 #define TSEC1_PHY_ADDR 2 412 #define TSEC2_PHY_ADDR 3 413 414 #define TSEC1_PHYIDX 0 415 #define TSEC2_PHYIDX 0 416 417 #define TSEC1_FLAGS TSEC_GIGABIT 418 #define TSEC2_FLAGS TSEC_GIGABIT 419 420 /* Options are: eTSEC[0-1] */ 421 #define CONFIG_ETHPRIME "eTSEC0" 422 423 #endif /* CONFIG_TSEC_ENET */ 424 425 /* 426 * Environment 427 */ 428 #define CFG_ENV_IS_IN_FLASH 1 429 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 430 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 431 #define CFG_ENV_SIZE 0x2000 432 433 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 434 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 435 436 437 /* 438 * BOOTP options 439 */ 440 #define CONFIG_BOOTP_BOOTFILESIZE 441 #define CONFIG_BOOTP_BOOTPATH 442 #define CONFIG_BOOTP_GATEWAY 443 #define CONFIG_BOOTP_HOSTNAME 444 445 446 /* 447 * Command line configuration. 448 */ 449 #include <config_cmd_default.h> 450 451 #define CONFIG_CMD_PING 452 #define CONFIG_CMD_I2C 453 #define CONFIG_CMD_MII 454 455 #if defined(CONFIG_PCI) 456 #define CONFIG_CMD_PCI 457 #endif 458 459 460 #undef CONFIG_WATCHDOG /* watchdog disabled */ 461 462 /* 463 * Miscellaneous configurable options 464 */ 465 #define CFG_LONGHELP /* undef to save memory */ 466 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 467 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 468 #if defined(CONFIG_CMD_KGDB) 469 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 470 #else 471 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 472 #endif 473 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 474 #define CFG_MAXARGS 16 /* max number of command args */ 475 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 476 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 477 478 /* 479 * For booting Linux, the board info and command line data 480 * have to be in the first 8 MB of memory, since this is 481 * the maximum mapped by the Linux kernel during initialization. 482 */ 483 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 484 485 /* Cache Configuration */ 486 #define CFG_DCACHE_SIZE 32768 487 #define CFG_CACHELINE_SIZE 32 488 #if defined(CONFIG_CMD_KGDB) 489 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 490 #endif 491 492 /* 493 * Internal Definitions 494 * 495 * Boot Flags 496 */ 497 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 498 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 499 500 #if defined(CONFIG_CMD_KGDB) 501 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 502 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 503 #endif 504 505 /* 506 * Environment Configuration 507 */ 508 509 /* The mac addresses for all ethernet interface */ 510 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 511 #define CONFIG_HAS_ETH0 512 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 513 #define CONFIG_HAS_ETH1 514 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 515 #define CONFIG_HAS_ETH2 516 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 517 #define CONFIG_HAS_ETH3 518 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 519 #endif 520 521 #define CONFIG_IPADDR 192.168.1.253 522 523 #define CONFIG_HOSTNAME unknown 524 #define CONFIG_ROOTPATH /nfsroot 525 #define CONFIG_BOOTFILE your.uImage 526 527 #define CONFIG_SERVERIP 192.168.1.1 528 #define CONFIG_GATEWAYIP 192.168.1.1 529 #define CONFIG_NETMASK 255.255.255.0 530 531 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 532 533 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 534 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 535 536 #define CONFIG_BAUDRATE 115200 537 538 #define CONFIG_EXTRA_ENV_SETTINGS \ 539 "netdev=eth0\0" \ 540 "consoledev=ttyS0\0" \ 541 "ramdiskaddr=600000\0" \ 542 "ramdiskfile=your.ramdisk.u-boot\0" \ 543 "fdtaddr=400000\0" \ 544 "fdtfile=your.fdt.dtb\0" \ 545 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 546 "nfsroot=$serverip:$rootpath " \ 547 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 548 "console=$consoledev,$baudrate $othbootargs\0" \ 549 "ramargs=setenv bootargs root=/dev/ram rw " \ 550 "console=$consoledev,$baudrate $othbootargs\0" \ 551 552 553 #define CONFIG_NFSBOOTCOMMAND \ 554 "run nfsargs;" \ 555 "tftp $loadaddr $bootfile;" \ 556 "tftp $fdtaddr $fdtfile;" \ 557 "bootm $loadaddr - $fdtaddr" 558 559 560 #define CONFIG_RAMBOOTCOMMAND \ 561 "run ramargs;" \ 562 "tftp $ramdiskaddr $ramdiskfile;" \ 563 "tftp $loadaddr $bootfile;" \ 564 "bootm $loadaddr $ramdiskaddr" 565 566 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 567 568 #endif /* __CONFIG_H */ 569