1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8560ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8560 1 /* MPC8560 specific */ 42 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 43 44 #define CONFIG_PCI 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 49 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 50 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 51 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 52 53 /* 54 * Use Localbus SDRAM to emulate flash before we can program the flash. 55 * Normally you need a flash-boot image(u-boot.bin). 56 * If unsure #undef this. 57 */ 58 #undef CONFIG_RAM_AS_FLASH 59 60 /* 61 * sysclk for MPC85xx 62 * 63 * Two valid values are: 64 * 33000000 65 * 66000000 66 * 67 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 68 * is likely the desired value here. The board, however, can run and 69 * defaults to 66Mhz. In any event, this value must match the settings 70 * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well. 71 * 72 * SW17[8] ------+ SW6 73 * SW15[1] ----+ | [0:1] 74 * V V V V 75 * 33MHz 1 1 1 0 76 * 66MHz 0 0 0 1 77 */ 78 79 #define CONFIG_SYS_CLK_FREQ 66000000 80 81 82 #if !defined(CONFIG_SPD_EEPROM) 83 #define CONFIG_DDR_SETTING /* manually set up DDR parameters */ 84 #endif 85 86 /* 87 * These can be toggled for performance analysis, otherwise use default. 88 */ 89 #define CONFIG_L2_CACHE /* toggle L2 cache */ 90 #define CONFIG_BTB /* toggle branch predition */ 91 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 92 93 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 94 95 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 96 97 #undef CFG_DRAM_TEST /* memory test, takes time */ 98 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 99 #define CFG_MEMTEST_END 0x00400000 100 101 102 /* 103 * Base addresses -- Note these are effective addresses where the 104 * actual resources get mapped (not physical addresses) 105 */ 106 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 107 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 108 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 109 110 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 111 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 112 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 113 114 /* 115 * SDRAM on the Local Bus 116 */ 117 #if defined(CONFIG_RAM_AS_FLASH) 118 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ 119 #else 120 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 121 #endif 122 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 123 124 #if defined(CONFIG_RAM_AS_FLASH) 125 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ 126 #define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ 127 #else /* Boot from real Flash */ 128 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 129 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 130 #endif 131 132 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 133 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 134 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 135 #undef CFG_FLASH_CHECKSUM 136 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 137 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 138 139 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 140 141 142 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 143 #define CFG_RAMBOOT 144 #else 145 #undef CFG_RAMBOOT 146 #endif 147 148 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 149 150 #undef CONFIG_CLOCKS_IN_MHZ 151 152 #if defined(CONFIG_DDR_SETTING) 153 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 154 #define CFG_DDR_CS0_CONFIG 0x80000002 155 #define CFG_DDR_TIMING_1 0x37344321 156 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 157 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 158 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 159 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 160 #endif 161 162 163 /* 164 * Local Bus Definitions 165 */ 166 167 /* 168 * Base Register 2 and Option Register 2 configure SDRAM. 169 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 170 * 171 * For BR2, need: 172 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 173 * port-size = 32-bits = BR2[19:20] = 11 174 * no parity checking = BR2[21:22] = 00 175 * SDRAM for MSEL = BR2[24:26] = 011 176 * Valid = BR[31] = 1 177 * 178 * 0 4 8 12 16 20 24 28 179 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 180 * 181 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 182 * FIXME: the top 17 bits of BR2. 183 */ 184 185 #define CFG_BR2_PRELIM 0xf0001861 186 187 /* 188 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 189 * 190 * For OR2, need: 191 * 64MB mask for AM, OR2[0:7] = 1111 1100 192 * XAM, OR2[17:18] = 11 193 * 9 columns OR2[19-21] = 010 194 * 13 rows OR2[23-25] = 100 195 * EAD set for extra time OR[31] = 1 196 * 197 * 0 4 8 12 16 20 24 28 198 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 199 */ 200 201 #define CFG_OR2_PRELIM 0xfc006901 202 203 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 204 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 205 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 206 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 207 208 /* 209 * LSDMR masks 210 */ 211 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 212 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 213 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 214 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 215 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 216 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 217 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 218 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 219 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 220 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 221 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 222 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 223 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 224 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 225 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 226 227 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 231 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 232 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 233 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 234 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 235 236 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 237 | CFG_LBC_LSDMR_RFCR5 \ 238 | CFG_LBC_LSDMR_PRETOACT3 \ 239 | CFG_LBC_LSDMR_ACTTORW3 \ 240 | CFG_LBC_LSDMR_BL8 \ 241 | CFG_LBC_LSDMR_WRC2 \ 242 | CFG_LBC_LSDMR_CL3 \ 243 | CFG_LBC_LSDMR_RFEN \ 244 ) 245 246 /* 247 * SDRAM Controller configuration sequence. 248 */ 249 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 250 | CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/ 251 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 252 | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/ 253 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 254 | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/ 255 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 256 | CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/ 257 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 258 | CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/ 259 260 261 #if defined(CONFIG_RAM_AS_FLASH) 262 #define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ 263 #else 264 #define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ 265 #endif 266 #define CFG_OR4_PRELIM 0xffffe1f1 267 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 268 269 #define CONFIG_L1_INIT_RAM 270 #define CFG_INIT_RAM_LOCK 1 271 #define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ 272 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 273 274 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 275 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 276 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 277 278 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 279 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 280 281 /* Serial Port */ 282 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 283 #undef CONFIG_CONS_NONE /* define if console on something else */ 284 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 285 286 #define CONFIG_BAUDRATE 115200 287 288 #define CFG_BAUDRATE_TABLE \ 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 290 291 /* Use the HUSH parser */ 292 #define CFG_HUSH_PARSER 293 #ifdef CFG_HUSH_PARSER 294 #define CFG_PROMPT_HUSH_PS2 "> " 295 #endif 296 297 /* I2C */ 298 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 299 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 300 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 301 #define CFG_I2C_SLAVE 0x7F 302 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 303 304 /* RapidIO MMU */ 305 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 306 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 307 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 308 309 /* 310 * General PCI 311 * Addresses are mapped 1-1. 312 */ 313 #define CFG_PCI1_MEM_BASE 0x80000000 314 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 315 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 316 #define CFG_PCI1_IO_BASE 0xe2000000 317 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 318 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 319 320 #if defined(CONFIG_PCI) 321 322 #define CONFIG_NET_MULTI 323 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 324 325 #undef CONFIG_EEPRO100 326 #undef CONFIG_TULIP 327 328 #if !defined(CONFIG_PCI_PNP) 329 #define PCI_ENET0_IOADDR 0xe0000000 330 #define PCI_ENET0_MEMADDR 0xe0000000 331 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 332 #endif 333 334 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 335 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 336 337 #endif /* CONFIG_PCI */ 338 339 340 #if defined(CONFIG_TSEC_ENET) 341 342 #ifndef CONFIG_NET_MULTI 343 #define CONFIG_NET_MULTI 1 344 #endif 345 346 #define CONFIG_MII 1 /* MII PHY management */ 347 #define CONFIG_MPC85XX_TSEC1 1 348 #define CONFIG_MPC85XX_TSEC2 1 349 #undef CONFIG_MPC85XX_FEC 350 #define TSEC1_PHY_ADDR 0 351 #define TSEC2_PHY_ADDR 1 352 #define TSEC1_PHYIDX 0 353 #define TSEC2_PHYIDX 0 354 #define CONFIG_ETHPRIME "MOTO ENET0" 355 356 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ 357 358 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 359 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 360 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 361 362 #if (CONFIG_ETHER_INDEX == 2) 363 /* 364 * - Rx-CLK is CLK13 365 * - Tx-CLK is CLK14 366 * - Select bus for bd/buffers 367 * - Full duplex 368 */ 369 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 370 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 371 #define CFG_CPMFCR_RAMTYPE 0 372 #define CFG_FCC_PSMR (FCC_PSMR_FDE) 373 #define FETH2_RST 0x01 374 #elif (CONFIG_ETHER_INDEX == 3) 375 /* need more definitions here for FE3 */ 376 #define FETH3_RST 0x80 377 #endif /* CONFIG_ETHER_INDEX */ 378 379 #define CONFIG_MII /* MII PHY management */ 380 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 381 382 /* 383 * GPIO pins used for bit-banged MII communications 384 */ 385 #define MDIO_PORT 2 /* Port C */ 386 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 387 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 388 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 389 390 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 391 else iop->pdat &= ~0x00400000 392 393 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 394 else iop->pdat &= ~0x00200000 395 396 #define MIIDELAY udelay(1) 397 398 #endif 399 400 401 /* 402 * Environment 403 */ 404 #ifndef CFG_RAMBOOT 405 #if defined(CONFIG_RAM_AS_FLASH) 406 #define CFG_ENV_IS_NOWHERE 407 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) 408 #define CFG_ENV_SIZE 0x2000 409 #else 410 #define CFG_ENV_IS_IN_FLASH 1 411 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 412 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 413 #endif 414 #define CFG_ENV_SIZE 0x2000 415 #else 416 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 417 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 418 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 419 #define CFG_ENV_SIZE 0x2000 420 #endif 421 422 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 423 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 424 425 #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) 426 #if defined(CONFIG_PCI) 427 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 428 | CFG_CMD_PCI \ 429 | CFG_CMD_PING \ 430 | CFG_CMD_I2C) \ 431 & \ 432 ~(CFG_CMD_ENV \ 433 | CFG_CMD_LOADS)) 434 #elif defined(CONFIG_TSEC_ENET) 435 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 436 | CFG_CMD_PING \ 437 | CFG_CMD_I2C) \ 438 & ~(CFG_CMD_ENV)) 439 #elif defined(CONFIG_ETHER_ON_FCC) 440 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 441 | CFG_CMD_MII \ 442 | CFG_CMD_PING \ 443 | CFG_CMD_I2C) \ 444 & ~(CFG_CMD_ENV)) 445 #endif 446 #else 447 #if defined(CONFIG_PCI) 448 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 449 | CFG_CMD_PCI \ 450 | CFG_CMD_PING \ 451 | CFG_CMD_I2C) 452 #elif defined(CONFIG_TSEC_ENET) 453 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 454 | CFG_CMD_PING \ 455 | CFG_CMD_I2C) 456 #elif defined(CONFIG_ETHER_ON_FCC) 457 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 458 | CFG_CMD_MII \ 459 | CFG_CMD_PING \ 460 | CFG_CMD_I2C) 461 #endif 462 #endif 463 464 #include <cmd_confdefs.h> 465 466 #undef CONFIG_WATCHDOG /* watchdog disabled */ 467 468 /* 469 * Miscellaneous configurable options 470 */ 471 #define CFG_LONGHELP /* undef to save memory */ 472 #define CFG_LOAD_ADDR 0x1000000 /* default load address */ 473 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 474 475 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 476 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 477 #else 478 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 479 #endif 480 481 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 482 #define CFG_MAXARGS 16 /* max number of command args */ 483 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 484 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 485 486 /* 487 * For booting Linux, the board info and command line data 488 * have to be in the first 8 MB of memory, since this is 489 * the maximum mapped by the Linux kernel during initialization. 490 */ 491 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 492 493 /* Cache Configuration */ 494 #define CFG_DCACHE_SIZE 32768 495 #define CFG_CACHELINE_SIZE 32 496 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 497 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 498 #endif 499 500 /* 501 * Internal Definitions 502 * 503 * Boot Flags 504 */ 505 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 506 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 507 508 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 509 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 510 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 511 #endif 512 513 /* The mac addresses for all ethernet interface */ 514 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 515 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 516 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 517 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 518 #endif 519 520 #define CONFIG_IPADDR 192.168.1.253 521 522 #define CONFIG_HOSTNAME unknown 523 #define CONFIG_ROOTPATH /nfsroot 524 #define CONFIG_BOOTFILE your.uImage 525 526 #define CONFIG_SERVERIP 192.168.1.1 527 #define CONFIG_GATEWAYIP 192.168.1.1 528 #define CONFIG_NETMASK 255.255.255.0 529 530 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 531 532 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 533 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 534 535 #define CONFIG_BAUDRATE 115200 536 537 #define CONFIG_EXTRA_ENV_SETTINGS \ 538 "netdev=eth0\0" \ 539 "consoledev=ttyS0\0" \ 540 "ramdiskaddr=400000\0" \ 541 "ramdiskfile=your.ramdisk.u-boot\0" 542 543 #define CONFIG_NFSBOOTCOMMAND \ 544 "setenv bootargs root=/dev/nfs rw " \ 545 "nfsroot=$serverip:$rootpath " \ 546 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 547 "console=$consoledev,$baudrate $othbootargs;" \ 548 "tftp $loadaddr $bootfile;" \ 549 "bootm $loadaddr" 550 551 #define CONFIG_RAMBOOTCOMMAND \ 552 "setenv bootargs root=/dev/ram rw " \ 553 "console=$consoledev,$baudrate $othbootargs;" \ 554 "tftp $ramdiskaddr $ramdiskfile;" \ 555 "tftp $loadaddr $bootfile;" \ 556 "bootm $loadaddr $ramdiskaddr" 557 558 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 559 560 #endif /* __CONFIG_H */ 561