1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc. in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_CPM2 1 /* has CPM2 */ 23 24 /* 25 * default CCARBAR is at 0xff700000 26 * assume U-Boot is less than 0.5MB 27 */ 28 #define CONFIG_SYS_TEXT_BASE 0xfff80000 29 30 #define CONFIG_PCI_INDIRECT_BRIDGE 31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 32 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 33 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 34 #define CONFIG_ENV_OVERWRITE 35 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 36 37 /* 38 * sysclk for MPC85xx 39 * 40 * Two valid values are: 41 * 33000000 42 * 66000000 43 * 44 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 45 * is likely the desired value here, so that is now the default. 46 * The board, however, can run at 66MHz. In any event, this value 47 * must match the settings of some switches. Details can be found 48 * in the README.mpc85xxads. 49 */ 50 51 #ifndef CONFIG_SYS_CLK_FREQ 52 #define CONFIG_SYS_CLK_FREQ 33000000 53 #endif 54 55 /* 56 * These can be toggled for performance analysis, otherwise use default. 57 */ 58 #define CONFIG_L2_CACHE /* toggle L2 cache */ 59 #define CONFIG_BTB /* toggle branch predition */ 60 61 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 62 63 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 64 #define CONFIG_SYS_MEMTEST_END 0x00400000 65 66 #define CONFIG_SYS_CCSRBAR 0xe0000000 67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 68 69 /* DDR Setup */ 70 #define CONFIG_SYS_FSL_DDR1 71 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 72 #define CONFIG_DDR_SPD 73 #undef CONFIG_FSL_DDR_INTERACTIVE 74 75 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 76 77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 79 80 #define CONFIG_NUM_DDR_CONTROLLERS 1 81 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 82 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 83 84 /* I2C addresses of SPD EEPROMs */ 85 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 86 87 /* These are used when DDR doesn't use SPD. */ 88 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 89 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 91 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 92 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 93 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 94 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 95 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 96 97 /* 98 * SDRAM on the Local Bus 99 */ 100 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 101 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 102 103 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 104 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 105 106 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 107 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 108 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 109 #undef CONFIG_SYS_FLASH_CHECKSUM 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 113 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 114 115 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 116 #define CONFIG_SYS_RAMBOOT 117 #else 118 #undef CONFIG_SYS_RAMBOOT 119 #endif 120 121 #define CONFIG_FLASH_CFI_DRIVER 122 #define CONFIG_SYS_FLASH_CFI 123 #define CONFIG_SYS_FLASH_EMPTY_INFO 124 125 #undef CONFIG_CLOCKS_IN_MHZ 126 127 /* 128 * Local Bus Definitions 129 */ 130 131 /* 132 * Base Register 2 and Option Register 2 configure SDRAM. 133 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 134 * 135 * For BR2, need: 136 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 137 * port-size = 32-bits = BR2[19:20] = 11 138 * no parity checking = BR2[21:22] = 00 139 * SDRAM for MSEL = BR2[24:26] = 011 140 * Valid = BR[31] = 1 141 * 142 * 0 4 8 12 16 20 24 28 143 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 144 * 145 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 146 * FIXME: the top 17 bits of BR2. 147 */ 148 149 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 150 151 /* 152 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 153 * 154 * For OR2, need: 155 * 64MB mask for AM, OR2[0:7] = 1111 1100 156 * XAM, OR2[17:18] = 11 157 * 9 columns OR2[19-21] = 010 158 * 13 rows OR2[23-25] = 100 159 * EAD set for extra time OR[31] = 1 160 * 161 * 0 4 8 12 16 20 24 28 162 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 163 */ 164 165 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 166 167 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 168 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 169 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 170 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 171 172 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 173 | LSDMR_RFCR5 \ 174 | LSDMR_PRETOACT3 \ 175 | LSDMR_ACTTORW3 \ 176 | LSDMR_BL8 \ 177 | LSDMR_WRC2 \ 178 | LSDMR_CL3 \ 179 | LSDMR_RFEN \ 180 ) 181 182 /* 183 * SDRAM Controller configuration sequence. 184 */ 185 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 186 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 187 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 188 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 189 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 190 191 /* 192 * 32KB, 8-bit wide for ADS config reg 193 */ 194 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 195 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 196 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 197 198 #define CONFIG_SYS_INIT_RAM_LOCK 1 199 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 200 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 201 202 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 203 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 204 205 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 206 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 207 208 /* Serial Port */ 209 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 210 #undef CONFIG_CONS_NONE /* define if console on something else */ 211 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 212 213 #define CONFIG_BAUDRATE 115200 214 215 #define CONFIG_SYS_BAUDRATE_TABLE \ 216 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 217 218 /* 219 * I2C 220 */ 221 #define CONFIG_SYS_I2C 222 #define CONFIG_SYS_I2C_FSL 223 #define CONFIG_SYS_FSL_I2C_SPEED 400000 224 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 225 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 226 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 227 228 /* RapidIO MMU */ 229 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 230 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 231 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 232 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 233 234 /* 235 * General PCI 236 * Memory space is mapped 1-1, but I/O space must start from 0. 237 */ 238 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 239 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 240 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 241 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 242 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 243 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 244 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 245 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 246 247 #if defined(CONFIG_PCI) 248 #undef CONFIG_EEPRO100 249 #undef CONFIG_TULIP 250 251 #if !defined(CONFIG_PCI_PNP) 252 #define PCI_ENET0_IOADDR 0xe0000000 253 #define PCI_ENET0_MEMADDR 0xe0000000 254 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 255 #endif 256 257 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 258 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 259 260 #endif /* CONFIG_PCI */ 261 262 #ifdef CONFIG_TSEC_ENET 263 264 #ifndef CONFIG_MII 265 #define CONFIG_MII 1 /* MII PHY management */ 266 #endif 267 #define CONFIG_TSEC1 1 268 #define CONFIG_TSEC1_NAME "TSEC0" 269 #define CONFIG_TSEC2 1 270 #define CONFIG_TSEC2_NAME "TSEC1" 271 #define TSEC1_PHY_ADDR 0 272 #define TSEC2_PHY_ADDR 1 273 #define TSEC1_PHYIDX 0 274 #define TSEC2_PHYIDX 0 275 #define TSEC1_FLAGS TSEC_GIGABIT 276 #define TSEC2_FLAGS TSEC_GIGABIT 277 278 /* Options are: TSEC[0-1] */ 279 #define CONFIG_ETHPRIME "TSEC0" 280 281 #endif /* CONFIG_TSEC_ENET */ 282 283 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 284 285 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 286 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 287 288 #if (CONFIG_ETHER_INDEX == 2) 289 /* 290 * - Rx-CLK is CLK13 291 * - Tx-CLK is CLK14 292 * - Select bus for bd/buffers 293 * - Full duplex 294 */ 295 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 296 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 297 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 298 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 299 #define FETH2_RST 0x01 300 #elif (CONFIG_ETHER_INDEX == 3) 301 /* need more definitions here for FE3 */ 302 #define FETH3_RST 0x80 303 #endif /* CONFIG_ETHER_INDEX */ 304 305 #ifndef CONFIG_MII 306 #define CONFIG_MII 1 /* MII PHY management */ 307 #endif 308 309 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 310 311 /* 312 * GPIO pins used for bit-banged MII communications 313 */ 314 #define MDIO_PORT 2 /* Port C */ 315 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 316 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 317 #define MDC_DECLARE MDIO_DECLARE 318 319 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 320 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 321 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 322 323 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 324 else iop->pdat &= ~0x00400000 325 326 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 327 else iop->pdat &= ~0x00200000 328 329 #define MIIDELAY udelay(1) 330 331 #endif 332 333 /* 334 * Environment 335 */ 336 #ifndef CONFIG_SYS_RAMBOOT 337 #define CONFIG_ENV_IS_IN_FLASH 1 338 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 339 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 340 #define CONFIG_ENV_SIZE 0x2000 341 #else 342 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 343 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 344 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 345 #define CONFIG_ENV_SIZE 0x2000 346 #endif 347 348 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 349 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 350 351 /* 352 * BOOTP options 353 */ 354 #define CONFIG_BOOTP_BOOTFILESIZE 355 #define CONFIG_BOOTP_BOOTPATH 356 #define CONFIG_BOOTP_GATEWAY 357 #define CONFIG_BOOTP_HOSTNAME 358 359 /* 360 * Command line configuration. 361 */ 362 #define CONFIG_CMD_IRQ 363 #define CONFIG_CMD_REGINFO 364 365 #if defined(CONFIG_PCI) 366 #define CONFIG_CMD_PCI 367 #endif 368 369 #if defined(CONFIG_ETHER_ON_FCC) 370 #endif 371 372 #undef CONFIG_WATCHDOG /* watchdog disabled */ 373 374 /* 375 * Miscellaneous configurable options 376 */ 377 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 378 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 379 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 380 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 381 382 #if defined(CONFIG_CMD_KGDB) 383 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 384 #else 385 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 386 #endif 387 388 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 389 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 390 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 391 392 /* 393 * For booting Linux, the board info and command line data 394 * have to be in the first 64 MB of memory, since this is 395 * the maximum mapped by the Linux kernel during initialization. 396 */ 397 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 398 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 399 400 #if defined(CONFIG_CMD_KGDB) 401 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 402 #endif 403 404 /* 405 * Environment Configuration 406 */ 407 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 408 #define CONFIG_HAS_ETH0 409 #define CONFIG_HAS_ETH1 410 #define CONFIG_HAS_ETH2 411 #define CONFIG_HAS_ETH3 412 #endif 413 414 #define CONFIG_IPADDR 192.168.1.253 415 416 #define CONFIG_HOSTNAME unknown 417 #define CONFIG_ROOTPATH "/nfsroot" 418 #define CONFIG_BOOTFILE "your.uImage" 419 420 #define CONFIG_SERVERIP 192.168.1.1 421 #define CONFIG_GATEWAYIP 192.168.1.1 422 #define CONFIG_NETMASK 255.255.255.0 423 424 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 425 426 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 427 428 #define CONFIG_BAUDRATE 115200 429 430 #define CONFIG_EXTRA_ENV_SETTINGS \ 431 "netdev=eth0\0" \ 432 "consoledev=ttyCPM\0" \ 433 "ramdiskaddr=1000000\0" \ 434 "ramdiskfile=your.ramdisk.u-boot\0" \ 435 "fdtaddr=400000\0" \ 436 "fdtfile=mpc8560ads.dtb\0" 437 438 #define CONFIG_NFSBOOTCOMMAND \ 439 "setenv bootargs root=/dev/nfs rw " \ 440 "nfsroot=$serverip:$rootpath " \ 441 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 442 "console=$consoledev,$baudrate $othbootargs;" \ 443 "tftp $loadaddr $bootfile;" \ 444 "tftp $fdtaddr $fdtfile;" \ 445 "bootm $loadaddr - $fdtaddr" 446 447 #define CONFIG_RAMBOOTCOMMAND \ 448 "setenv bootargs root=/dev/ram rw " \ 449 "console=$consoledev,$baudrate $othbootargs;" \ 450 "tftp $ramdiskaddr $ramdiskfile;" \ 451 "tftp $loadaddr $bootfile;" \ 452 "tftp $fdtaddr $fdtfile;" \ 453 "bootm $loadaddr $ramdiskaddr $fdtaddr" 454 455 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 456 457 #endif /* __CONFIG_H */ 458