1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8544ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8544 1 35 #define CONFIG_MPC8544DS 1 36 37 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 38 #define CONFIG_PCI1 1 /* PCI controller 1 */ 39 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 44 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 45 46 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 47 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 48 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 52 53 #ifndef __ASSEMBLY__ 54 extern unsigned long get_board_sys_clk(unsigned long dummy); 55 #endif 56 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 57 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_L2_CACHE /* toggle L2 cache */ 62 #define CONFIG_BTB /* toggle branch predition */ 63 64 /* 65 * Only possible on E500 Version 2 or newer cores. 66 */ 67 #define CONFIG_ENABLE_36BIT_PHYS 1 68 69 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 70 #define CONFIG_SYS_MEMTEST_END 0x00400000 71 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 72 73 /* 74 * Base addresses -- Note these are effective addresses where the 75 * actual resources get mapped (not physical addresses) 76 */ 77 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 78 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 79 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 81 82 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 83 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 84 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 85 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) 86 87 /* DDR Setup */ 88 #define CONFIG_FSL_DDR2 89 #undef CONFIG_FSL_DDR_INTERACTIVE 90 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 91 #define CONFIG_DDR_SPD 92 93 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 94 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 95 96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 98 #define CONFIG_VERY_BIG_RAM 99 100 #define CONFIG_NUM_DDR_CONTROLLERS 1 101 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 102 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 103 104 /* I2C addresses of SPD EEPROMs */ 105 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 106 107 /* Make sure required options are set */ 108 #ifndef CONFIG_SPD_EEPROM 109 #error ("CONFIG_SPD_EEPROM is required") 110 #endif 111 112 #undef CONFIG_CLOCKS_IN_MHZ 113 114 /* 115 * Memory map 116 * 117 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 118 * 119 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 120 * 121 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 122 * 123 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 124 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 125 * 126 * Localbus cacheable 127 * 128 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 129 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 130 * 131 * Localbus non-cacheable 132 * 133 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 134 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 135 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 136 * 137 */ 138 139 /* 140 * Local Bus Definitions 141 */ 142 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 143 144 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 145 146 #define CONFIG_SYS_BR0_PRELIM 0xff801001 147 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 148 149 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 150 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 151 152 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 153 154 #define CONFIG_SYS_FLASH_QUIET_TEST 155 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 156 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 157 #undef CONFIG_SYS_FLASH_CHECKSUM 158 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 159 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 160 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 161 162 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 163 164 #define CONFIG_FLASH_CFI_DRIVER 165 #define CONFIG_SYS_FLASH_CFI 166 #define CONFIG_SYS_FLASH_EMPTY_INFO 167 168 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 169 170 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 171 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 172 173 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 174 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 175 176 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 177 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 178 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 179 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 180 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 181 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 182 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 183 * register */ 184 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 185 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 186 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 187 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 188 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 189 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 190 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 191 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 192 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 193 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 194 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 195 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 196 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 197 #define PIXIS_VSPEED2_TSEC1SER 0x2 198 #define PIXIS_VSPEED2_TSEC3SER 0x1 199 #define PIXIS_VCFGEN1_TSEC1SER 0x20 200 #define PIXIS_VCFGEN1_TSEC3SER 0x40 201 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 202 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 203 204 205 #define CONFIG_SYS_INIT_RAM_LOCK 1 206 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 207 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 208 209 210 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 211 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 212 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 213 214 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 215 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 216 217 /* Serial Port - controlled on board with jumper J8 218 * open - index 2 219 * shorted - index 1 220 */ 221 #define CONFIG_CONS_INDEX 1 222 #undef CONFIG_SERIAL_SOFTWARE_FIFO 223 #define CONFIG_SYS_NS16550 224 #define CONFIG_SYS_NS16550_SERIAL 225 #define CONFIG_SYS_NS16550_REG_SIZE 1 226 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 227 228 #define CONFIG_SYS_BAUDRATE_TABLE \ 229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 230 231 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 232 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 233 234 /* Use the HUSH parser */ 235 #define CONFIG_SYS_HUSH_PARSER 236 #ifdef CONFIG_SYS_HUSH_PARSER 237 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 238 #endif 239 240 /* pass open firmware flat tree */ 241 #define CONFIG_OF_LIBFDT 1 242 #define CONFIG_OF_BOARD_SETUP 1 243 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 244 245 #define CONFIG_SYS_64BIT_STRTOUL 1 246 #define CONFIG_SYS_64BIT_VSPRINTF 1 247 248 /* I2C */ 249 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 250 #define CONFIG_HARD_I2C /* I2C with hardware support */ 251 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 252 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 253 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 254 #define CONFIG_SYS_I2C_SLAVE 0x7F 255 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 256 #define CONFIG_SYS_I2C_OFFSET 0x3100 257 258 /* 259 * General PCI 260 * Memory space is mapped 1-1, but I/O space must start from 0. 261 */ 262 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 263 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 264 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 265 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 266 267 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 268 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 269 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 270 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 271 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 272 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 273 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 274 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 275 276 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 277 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 278 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 279 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 280 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 281 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 282 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 283 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 284 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 285 286 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 287 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 288 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 289 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 290 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 291 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 292 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 293 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 294 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 295 296 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 297 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 298 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 299 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 300 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 301 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 302 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 303 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 304 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 305 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 306 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 307 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 308 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 309 310 #if defined(CONFIG_PCI) 311 312 /*PCIE video card used*/ 313 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 314 315 /*PCI video card used*/ 316 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 317 318 /* video */ 319 #define CONFIG_VIDEO 320 321 #if defined(CONFIG_VIDEO) 322 #define CONFIG_BIOSEMU 323 #define CONFIG_CFB_CONSOLE 324 #define CONFIG_VIDEO_SW_CURSOR 325 #define CONFIG_VGA_AS_SINGLE_DEVICE 326 #define CONFIG_ATI_RADEON_FB 327 #define CONFIG_VIDEO_LOGO 328 /*#define CONFIG_CONSOLE_CURSOR*/ 329 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 330 #endif 331 332 #define CONFIG_NET_MULTI 333 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 334 335 #undef CONFIG_EEPRO100 336 #undef CONFIG_TULIP 337 #define CONFIG_RTL8139 338 339 #ifndef CONFIG_PCI_PNP 340 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 341 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 342 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 343 #endif 344 345 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 346 #define CONFIG_DOS_PARTITION 347 #define CONFIG_SCSI_AHCI 348 349 #ifdef CONFIG_SCSI_AHCI 350 #define CONFIG_SATA_ULI5288 351 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 352 #define CONFIG_SYS_SCSI_MAX_LUN 1 353 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 354 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 355 #endif /* SCSCI */ 356 357 #endif /* CONFIG_PCI */ 358 359 360 #if defined(CONFIG_TSEC_ENET) 361 362 #ifndef CONFIG_NET_MULTI 363 #define CONFIG_NET_MULTI 1 364 #endif 365 366 #define CONFIG_MII 1 /* MII PHY management */ 367 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 368 #define CONFIG_TSEC1 1 369 #define CONFIG_TSEC1_NAME "eTSEC1" 370 #define CONFIG_TSEC3 1 371 #define CONFIG_TSEC3_NAME "eTSEC3" 372 373 #define CONFIG_PIXIS_SGMII_CMD 374 #define CONFIG_FSL_SGMII_RISER 1 375 #define SGMII_RISER_PHY_OFFSET 0x1c 376 377 #define TSEC1_PHY_ADDR 0 378 #define TSEC3_PHY_ADDR 1 379 380 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 381 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 382 383 #define TSEC1_PHYIDX 0 384 #define TSEC3_PHYIDX 0 385 386 #define CONFIG_ETHPRIME "eTSEC1" 387 388 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 389 #endif /* CONFIG_TSEC_ENET */ 390 391 /* 392 * Environment 393 */ 394 #define CONFIG_ENV_IS_IN_FLASH 1 395 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 396 #define CONFIG_ENV_ADDR 0xfff80000 397 #else 398 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) 399 #endif 400 #define CONFIG_ENV_SIZE 0x2000 401 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 402 403 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 404 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 405 406 /* 407 * BOOTP options 408 */ 409 #define CONFIG_BOOTP_BOOTFILESIZE 410 #define CONFIG_BOOTP_BOOTPATH 411 #define CONFIG_BOOTP_GATEWAY 412 #define CONFIG_BOOTP_HOSTNAME 413 414 415 /* 416 * Command line configuration. 417 */ 418 #include <config_cmd_default.h> 419 420 #define CONFIG_CMD_PING 421 #define CONFIG_CMD_I2C 422 #define CONFIG_CMD_MII 423 #define CONFIG_CMD_ELF 424 #define CONFIG_CMD_IRQ 425 #define CONFIG_CMD_SETEXPR 426 427 #if defined(CONFIG_PCI) 428 #define CONFIG_CMD_PCI 429 #define CONFIG_CMD_NET 430 #define CONFIG_CMD_SCSI 431 #define CONFIG_CMD_EXT2 432 #endif 433 434 435 #undef CONFIG_WATCHDOG /* watchdog disabled */ 436 437 /* 438 * Miscellaneous configurable options 439 */ 440 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 441 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 442 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 443 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 444 #if defined(CONFIG_CMD_KGDB) 445 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 446 #else 447 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 448 #endif 449 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 450 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 451 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 452 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 453 454 /* 455 * For booting Linux, the board info and command line data 456 * have to be in the first 16 MB of memory, since this is 457 * the maximum mapped by the Linux kernel during initialization. 458 */ 459 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 460 461 /* 462 * Internal Definitions 463 * 464 * Boot Flags 465 */ 466 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 467 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 468 469 #if defined(CONFIG_CMD_KGDB) 470 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 471 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 472 #endif 473 474 /* 475 * Environment Configuration 476 */ 477 478 /* The mac addresses for all ethernet interface */ 479 #if defined(CONFIG_TSEC_ENET) 480 #define CONFIG_HAS_ETH0 481 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 482 #define CONFIG_HAS_ETH1 483 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 484 #endif 485 486 #define CONFIG_IPADDR 192.168.1.251 487 488 #define CONFIG_HOSTNAME 8544ds_unknown 489 #define CONFIG_ROOTPATH /nfs/mpc85xx 490 #define CONFIG_BOOTFILE 8544ds/uImage.uboot 491 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 492 493 #define CONFIG_SERVERIP 192.168.1.1 494 #define CONFIG_GATEWAYIP 192.168.1.1 495 #define CONFIG_NETMASK 255.255.0.0 496 497 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 498 499 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 500 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 501 502 #define CONFIG_BAUDRATE 115200 503 504 #define CONFIG_EXTRA_ENV_SETTINGS \ 505 "netdev=eth0\0" \ 506 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 507 "tftpflash=tftpboot $loadaddr $uboot; " \ 508 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 509 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 510 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 511 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 512 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 513 "consoledev=ttyS0\0" \ 514 "ramdiskaddr=2000000\0" \ 515 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 516 "fdtaddr=c00000\0" \ 517 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 518 "bdev=sda3\0" 519 520 #define CONFIG_NFSBOOTCOMMAND \ 521 "setenv bootargs root=/dev/nfs rw " \ 522 "nfsroot=$serverip:$rootpath " \ 523 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 524 "console=$consoledev,$baudrate $othbootargs;" \ 525 "tftp $loadaddr $bootfile;" \ 526 "tftp $fdtaddr $fdtfile;" \ 527 "bootm $loadaddr - $fdtaddr" 528 529 #define CONFIG_RAMBOOTCOMMAND \ 530 "setenv bootargs root=/dev/ram rw " \ 531 "console=$consoledev,$baudrate $othbootargs;" \ 532 "tftp $ramdiskaddr $ramdiskfile;" \ 533 "tftp $loadaddr $bootfile;" \ 534 "tftp $fdtaddr $fdtfile;" \ 535 "bootm $loadaddr $ramdiskaddr $fdtaddr" 536 537 #define CONFIG_BOOTCOMMAND \ 538 "setenv bootargs root=/dev/$bdev rw " \ 539 "console=$consoledev,$baudrate $othbootargs;" \ 540 "tftp $loadaddr $bootfile;" \ 541 "tftp $fdtaddr $fdtfile;" \ 542 "bootm $loadaddr - $fdtaddr" 543 544 #endif /* __CONFIG_H */ 545